Name of user not set #1002723 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37724 )
Change subject: toolchain added
......................................................................
toolchain added
Change-Id: I08276324846ec8091909a1e4d124d089a34a0f88
---
M 3rdparty/vboot
A src/mainboard/dell/Kconfig
A src/mainboard/dell/Kconfig.name
A src/mainboard/dell/dell_system_vostro_3360/Kconfig
A src/mainboard/dell/dell_system_vostro_3360/Kconfig.name
A src/mainboard/dell/dell_system_vostro_3360/Makefile.inc
A src/mainboard/dell/dell_system_vostro_3360/acpi/ec.asl
A src/mainboard/dell/dell_system_vostro_3360/acpi/platform.asl
A src/mainboard/dell/dell_system_vostro_3360/acpi/superio.asl
A src/mainboard/dell/dell_system_vostro_3360/acpi_tables.c
A src/mainboard/dell/dell_system_vostro_3360/board_info.txt
A src/mainboard/dell/dell_system_vostro_3360/devicetree.cb
A src/mainboard/dell/dell_system_vostro_3360/dsdt.asl
A src/mainboard/dell/dell_system_vostro_3360/gma-mainboard.ads
A src/mainboard/dell/dell_system_vostro_3360/gpio.c
A src/mainboard/dell/dell_system_vostro_3360/hda_verb.c
A src/mainboard/dell/dell_system_vostro_3360/mainboard.c
A src/mainboard/dell/dell_system_vostro_3360/romstage.c
A util/autoport/logs/acpidump.log
A util/autoport/logs/codec_0
A util/autoport/logs/codec_3
A util/autoport/logs/cpuinfo.log
A util/autoport/logs/dmidecode.log
A util/autoport/logs/ectool.log
A util/autoport/logs/input_bustypes.log
A util/autoport/logs/inteltool.log
A util/autoport/logs/ioports.log
A util/autoport/logs/lspci.log
A util/autoport/logs/pin_hwC0D0
A util/autoport/logs/pin_hwC0D3
A util/autoport/logs/superiotool.log
31 files changed, 30,233 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/37724/1
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I08276324846ec8091909a1e4d124d089a34a0f88
Gerrit-Change-Number: 37724
Gerrit-PatchSet: 1
Gerrit-Owner: Name of user not set #1002723
Gerrit-MessageType: newchange
Hello Edward O'Callaghan,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/37696
to review the following change.
Change subject: mainboard/google/puff: Toggle on DqPinsInterleaved
......................................................................
mainboard/google/puff: Toggle on DqPinsInterleaved
BUG=b:146172098
TEST=none
Change-Id: Ib2da3baace9255ef25c0f03390a064fd77ef9ae5
Signed-off-by: Edward O'Callaghan <quasisec(a)google.com>
---
M src/mainboard/google/hatch/romstage_spd_smbus.c
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/37696/1
diff --git a/src/mainboard/google/hatch/romstage_spd_smbus.c b/src/mainboard/google/hatch/romstage_spd_smbus.c
index 74d59a5..4a93a36 100644
--- a/src/mainboard/google/hatch/romstage_spd_smbus.c
+++ b/src/mainboard/google/hatch/romstage_spd_smbus.c
@@ -45,6 +45,7 @@
/* set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B. */
memcfg.vref_ca_config = 2;
+ memcfg.DqPinsInterleaved = 1;
cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
}
--
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Gerrit-Change-Id: Ib2da3baace9255ef25c0f03390a064fd77ef9ae5
Gerrit-Change-Number: 37696
Gerrit-PatchSet: 1
Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org>
Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)google.com>
Gerrit-MessageType: newchange
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36830 )
Change subject: sc7180: Add I2C driver
......................................................................
Patch Set 10: Code-Review+2
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I61221ffff8afe5c7ede5abb9e194e242ab0274d8
Gerrit-Change-Number: 36830
Gerrit-PatchSet: 10
Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
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Gerrit-Reviewer: Ravi kumar <rbokka(a)codeaurora.org>
Gerrit-Reviewer: Satya Priya Kakitapalli <c_skakit(a)qualcomm.corp-partner.google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org>
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Gerrit-Comment-Date: Fri, 13 Dec 2019 23:49:44 +0000
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Gerrit-MessageType: comment
Hello Srinidhi N Kaushik, Raj Astekar, Subrata Banik, Arthur Heymans, Wonkyu Kim, John Zhao, build bot (Jenkins), Shaunak Saha, Furquan Shaikh, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36091
to look at the new patch set (#13).
Change subject: mb/intel/tglrvp: Do initial mainboard commit
......................................................................
mb/intel/tglrvp: Do initial mainboard commit
1. Add tglrvp baseboard files
2. Add tglrvp UP3 variant board files
3. Add board id support
4. Add SPD memory support
TEST=Build and boot tigerlake rvp board
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com>
Change-Id: I79a05881d2ea50ff4113243bf5ae26207db63322
---
A src/mainboard/intel/tglrvp/Kconfig
A src/mainboard/intel/tglrvp/Kconfig.name
A src/mainboard/intel/tglrvp/Makefile.inc
A src/mainboard/intel/tglrvp/acpi/mainboard.asl
A src/mainboard/intel/tglrvp/acpi/mipi_camera.asl
A src/mainboard/intel/tglrvp/acpi_tables.c
A src/mainboard/intel/tglrvp/board_id.c
A src/mainboard/intel/tglrvp/board_id.h
A src/mainboard/intel/tglrvp/board_info.txt
A src/mainboard/intel/tglrvp/bootblock.c
A src/mainboard/intel/tglrvp/chromeos.c
A src/mainboard/intel/tglrvp/chromeos.fmd
A src/mainboard/intel/tglrvp/dsdt.asl
A src/mainboard/intel/tglrvp/ec.c
A src/mainboard/intel/tglrvp/romstage.c
A src/mainboard/intel/tglrvp/smihandler.c
A src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex
A src/mainboard/intel/tglrvp/spd/Makefile.inc
A src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex
A src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex
A src/mainboard/intel/tglrvp/spd/spd.h
A src/mainboard/intel/tglrvp/variants/baseboard/Makefile.inc
A src/mainboard/intel/tglrvp/variants/baseboard/devicetree.cb
A src/mainboard/intel/tglrvp/variants/baseboard/gpio.c
A src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h
A src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h
A src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h
A src/mainboard/intel/tglrvp/variants/baseboard/mainboard.c
A src/mainboard/intel/tglrvp/variants/baseboard/memory.c
A src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc
A src/mainboard/intel/tglrvp/variants/tglrvp_up3/include/variant/ec.h
A src/mainboard/intel/tglrvp/variants/tglrvp_up3/include/variant/gpio.h
32 files changed, 2,115 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/36091/13
--
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Gerrit-MessageType: newpatchset
Hello Srinidhi N Kaushik, Raj Astekar, Patrick Rudolph, Venkata Krishna Nimmagadda, Subrata Banik, Wonkyu Kim, build bot (Jenkins), Shaunak Saha, Jamie Ryu, Francois Toguo Fotso,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37426
to look at the new patch set (#6).
Change subject: soc/intel/tigerlake: Fix build issues
......................................................................
soc/intel/tigerlake: Fix build issues
Add following to fix build issues:
1. Update ASL files:
a. Add new PMC, SMBUS files
b. Remove unused files
c. Update tigerlake specific changes on top of icelake
2. Update tigerlake PMC_REG_BASE
3. Update SOC header files to include tigerlake specific
4. Update chip files to include tigerlake PCH DEVFNs
TEST=Build and boot tigerlake rvp board
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com>
Change-Id: I04020d55f1063d521b15f8d0dabbd6f1dabf577c
---
M src/soc/intel/tigerlake/Kconfig
M src/soc/intel/tigerlake/acpi/northbridge.asl
A src/soc/intel/tigerlake/acpi/norththbridge.asl
A src/soc/intel/tigerlake/acpi/pch_clock_ctl.asl
M src/soc/intel/tigerlake/acpi/pci_irqs.asl
M src/soc/intel/tigerlake/acpi/pcie.asl
M src/soc/intel/tigerlake/acpi/platform.asl
A src/soc/intel/tigerlake/acpi/pmc.asl
M src/soc/intel/tigerlake/acpi/serialio.asl
A src/soc/intel/tigerlake/acpi/sleepstates.asl
A src/soc/intel/tigerlake/acpi/smbus.asl
M src/soc/intel/tigerlake/acpi/southbridge.asl
M src/soc/intel/tigerlake/bootblock/pch.c
M src/soc/intel/tigerlake/chip.c
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/include/soc/iomap.h
M src/soc/intel/tigerlake/include/soc/irq.h
M src/soc/intel/tigerlake/include/soc/pci_devs.h
M src/soc/intel/tigerlake/include/soc/pmc.h
M src/soc/intel/tigerlake/include/soc/ramstage.h
M src/soc/intel/tigerlake/include/soc/romstage.h
M src/soc/intel/tigerlake/include/soc/serialio.h
M src/soc/intel/tigerlake/pmutil.c
23 files changed, 1,219 insertions(+), 354 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/37426/6
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