Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37449 )
Change subject: amd/agesa/family14: Expand and remove platform_once() ......................................................................
amd/agesa/family14: Expand and remove platform_once()
It is expected that the call will move into a common bootblock file once boards switch to C environment bootblock.
Change-Id: I3a28eaa2cf70b770b022760a2380ded0f43e9a6f Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/amd/agesa/family14/Makefile.inc D src/cpu/amd/agesa/family14/romstage.c M src/drivers/amd/agesa/romstage.c M src/mainboard/amd/inagua/romstage.c M src/mainboard/amd/persimmon/romstage.c M src/mainboard/amd/south_station/romstage.c M src/mainboard/amd/union_station/romstage.c M src/mainboard/asrock/e350m1/romstage.c M src/mainboard/elmex/pcm205400/romstage.c M src/mainboard/gizmosphere/gizmo/romstage.c M src/mainboard/jetway/nf81-t56n-lf/romstage.c M src/mainboard/lippert/frontrunner-af/romstage.c M src/mainboard/lippert/toucan-af/romstage.c M src/mainboard/pcengines/apu1/romstage.c M src/northbridge/amd/agesa/state_machine.h 15 files changed, 24 insertions(+), 31 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/37449/1
diff --git a/src/cpu/amd/agesa/family14/Makefile.inc b/src/cpu/amd/agesa/family14/Makefile.inc index 7db1fe4..1d68113 100644 --- a/src/cpu/amd/agesa/family14/Makefile.inc +++ b/src/cpu/amd/agesa/family14/Makefile.inc @@ -12,7 +12,6 @@ #
romstage-y += fixme.c -romstage-y += romstage.c
ramstage-y += fixme.c ramstage-y += chip_name.c diff --git a/src/cpu/amd/agesa/family14/romstage.c b/src/cpu/amd/agesa/family14/romstage.c deleted file mode 100644 index 54069cc3..0000000 --- a/src/cpu/amd/agesa/family14/romstage.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#include <northbridge/amd/agesa/state_machine.h> - -#include <sb_cimx.h> - -void platform_once(struct sysinfo *cb) -{ - sb_Poweron_Init(); - - board_BeforeAgesa(cb); -} diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index 684fa66..ee4d45e 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -27,10 +27,7 @@ #include <northbridge/amd/agesa/agesa_helper.h> #include <northbridge/amd/agesa/state_machine.h>
-void __weak platform_once(struct sysinfo *cb) -{ - board_BeforeAgesa(cb); -} +void __weak board_BeforeAgesa(struct sysinfo *cb) { }
static void fill_sysinfo(struct sysinfo *cb) { @@ -65,7 +62,7 @@ timestamp_init(timestamp_get()); timestamp_add_now(TS_START_ROMSTAGE);
- platform_once(cb); + board_BeforeAgesa(cb);
console_init(); } diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c index 3454ef8..43d9da9 100644 --- a/src/mainboard/amd/inagua/romstage.c +++ b/src/mainboard/amd/inagua/romstage.c @@ -15,11 +15,13 @@
#include <northbridge/amd/agesa/state_machine.h> #include <superio/smsc/kbc1100/kbc1100.h> +#include <sb_cimx.h>
#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
void board_BeforeAgesa(struct sysinfo *cb) { + sb_Poweron_Init(); kbc1100_early_init(0x2e); kbc1100_early_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index 1fbdd4b..7ccf167 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -16,10 +16,12 @@ #include <northbridge/amd/agesa/state_machine.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f81865f/f81865f.h> +#include <sb_cimx.h>
#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1)
void board_BeforeAgesa(struct sysinfo *cb) { + sb_Poweron_Init(); fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c index 1fbdd4b..7ccf167 100644 --- a/src/mainboard/amd/south_station/romstage.c +++ b/src/mainboard/amd/south_station/romstage.c @@ -16,10 +16,12 @@ #include <northbridge/amd/agesa/state_machine.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f81865f/f81865f.h> +#include <sb_cimx.h>
#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1)
void board_BeforeAgesa(struct sysinfo *cb) { + sb_Poweron_Init(); fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c index f2b00bc..af64ad8 100644 --- a/src/mainboard/amd/union_station/romstage.c +++ b/src/mainboard/amd/union_station/romstage.c @@ -14,7 +14,9 @@ */
#include <northbridge/amd/agesa/state_machine.h> +#include <sb_cimx.h>
void board_BeforeAgesa(struct sysinfo *cb) { + sb_Poweron_Init(); } diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index 292ecf2..27a1fac 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -16,11 +16,13 @@ #include <northbridge/amd/agesa/state_machine.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct5572d/nct5572d.h> +#include <sb_cimx.h>
#define SERIAL_DEV PNP_DEV(0x2e, NCT5572D_SP1)
void board_BeforeAgesa(struct sysinfo *cb) { + sb_Poweron_Init(); nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/elmex/pcm205400/romstage.c b/src/mainboard/elmex/pcm205400/romstage.c index 1fbdd4b..7ccf167 100644 --- a/src/mainboard/elmex/pcm205400/romstage.c +++ b/src/mainboard/elmex/pcm205400/romstage.c @@ -16,10 +16,12 @@ #include <northbridge/amd/agesa/state_machine.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f81865f/f81865f.h> +#include <sb_cimx.h>
#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1)
void board_BeforeAgesa(struct sysinfo *cb) { + sb_Poweron_Init(); fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c index 8dec7fe..7c3f534 100644 --- a/src/mainboard/gizmosphere/gizmo/romstage.c +++ b/src/mainboard/gizmosphere/gizmo/romstage.c @@ -15,7 +15,9 @@ */
#include <northbridge/amd/agesa/state_machine.h> +#include <sb_cimx.h>
void board_BeforeAgesa(struct sysinfo *cb) { + sb_Poweron_Init(); } diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c index a971c15..5e61bdd 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c @@ -17,11 +17,13 @@ #include <northbridge/amd/agesa/state_machine.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f71869ad/f71869ad.h> +#include <sb_cimx.h>
/* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */ #define SERIAL_DEV PNP_DEV(0x2e, F71869AD_SP1)
void board_BeforeAgesa(struct sysinfo *cb) { + sb_Poweron_Init(); fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c index 83d5a6d..f8e6091 100644 --- a/src/mainboard/lippert/frontrunner-af/romstage.c +++ b/src/mainboard/lippert/frontrunner-af/romstage.c @@ -15,10 +15,12 @@
#include <northbridge/amd/agesa/state_machine.h> #include <superio/smsc/smscsuperio/smscsuperio.h> +#include <sb_cimx.h>
#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)
void board_BeforeAgesa(struct sysinfo *cb) { + sb_Poweron_Init(); smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c index 7ca9dcb..ebbe4fc 100644 --- a/src/mainboard/lippert/toucan-af/romstage.c +++ b/src/mainboard/lippert/toucan-af/romstage.c @@ -16,10 +16,12 @@ #include <northbridge/amd/agesa/state_machine.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627dhg/w83627dhg.h> +#include <sb_cimx.h>
#define SERIAL_DEV PNP_DEV(0x4e, W83627DHG_SP1)
void board_BeforeAgesa(struct sysinfo *cb) { + sb_Poweron_Init(); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/pcengines/apu1/romstage.c b/src/mainboard/pcengines/apu1/romstage.c index 89bf304..da0e0d3 100644 --- a/src/mainboard/pcengines/apu1/romstage.c +++ b/src/mainboard/pcengines/apu1/romstage.c @@ -21,6 +21,7 @@ #include <superio/nuvoton/nct5104d/nct5104d.h> #include "gpio_ftns.h" #include <SB800.h> +#include <sb_cimx.h>
#define SIO_PORT 0x2e #define SERIAL_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1) @@ -60,6 +61,7 @@
void board_BeforeAgesa(struct sysinfo *cb) { + sb_Poweron_Init(); early_lpc_init(); nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/northbridge/amd/agesa/state_machine.h b/src/northbridge/amd/agesa/state_machine.h index 02a7a41..89a6c9b 100644 --- a/src/northbridge/amd/agesa/state_machine.h +++ b/src/northbridge/amd/agesa/state_machine.h @@ -48,7 +48,6 @@ void agesa_postcar(struct sysinfo *cb);
void board_BeforeAgesa(struct sysinfo *cb); -void platform_once(struct sysinfo *cb);
void agesa_set_interface(struct sysinfo *cb);
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37449 )
Change subject: amd/agesa/family14: Expand and remove platform_once() ......................................................................
Patch Set 4:
So far no regression spotted on apu1.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37449 )
Change subject: amd/agesa/family14: Expand and remove platform_once() ......................................................................
Patch Set 4:
I would prefer if we do not need to pull this call into bootblock, but could put this into platform_BeforeInitReset() instead.
Hello Piotr Król, build bot (Jenkins), Michał Żygowski, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37449
to look at the new patch set (#5).
Change subject: sb/amd/cimx/sb800: Postpone Sb_Poweron_Init() call ......................................................................
sb/amd/cimx/sb800: Postpone Sb_Poweron_Init() call
With LPC decode enables explicitly set in C env bootblock, this call can be delayd to happen before AMD_INIT_RESET.
Change-Id: I3a28eaa2cf70b770b022760a2380ded0f43e9a6f Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/amd/agesa/family14/Makefile.inc D src/cpu/amd/agesa/family14/romstage.c M src/drivers/amd/agesa/romstage.c M src/mainboard/amd/inagua/romstage.c M src/mainboard/amd/persimmon/romstage.c M src/mainboard/amd/south_station/romstage.c M src/mainboard/amd/union_station/romstage.c M src/mainboard/asrock/e350m1/romstage.c M src/mainboard/elmex/pcm205400/romstage.c M src/mainboard/gizmosphere/gizmo/romstage.c M src/mainboard/jetway/nf81-t56n-lf/romstage.c M src/mainboard/lippert/frontrunner-af/romstage.c M src/mainboard/lippert/toucan-af/romstage.c M src/mainboard/pcengines/apu1/romstage.c M src/northbridge/amd/agesa/family14/state_machine.c M src/northbridge/amd/agesa/state_machine.h 16 files changed, 26 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/37449/5
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37449 )
Change subject: sb/amd/cimx/sb800: Postpone Sb_Poweron_Init() call ......................................................................
Patch Set 5:
(1 comment)
Patch Set 4:
I would prefer if we do not need to pull this call into bootblock, but could put this into platform_BeforeInitReset() instead.
I see
https://review.coreboot.org/c/coreboot/+/37449/5/src/northbridge/amd/agesa/f... File src/northbridge/amd/agesa/family14/state_machine.c:
https://review.coreboot.org/c/coreboot/+/37449/5/src/northbridge/amd/agesa/f... PS5, Line 52: sb_Poweron_Init(); sb_Poweron_Init is still called in board_BeforeAgesa for each mainboard making it a doubled call.
Additionally, I think the sb_Poweron_Init can be moved to the IF statement above so you could avoid calling boot_cpu() again.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37449 )
Change subject: sb/amd/cimx/sb800: Postpone Sb_Poweron_Init() call ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37449/5/src/northbridge/amd/agesa/f... File src/northbridge/amd/agesa/family14/state_machine.c:
https://review.coreboot.org/c/coreboot/+/37449/5/src/northbridge/amd/agesa/f... PS5, Line 52: sb_Poweron_Init();
sb_Poweron_Init is still called in board_BeforeAgesa for each mainboard making it a doubled call. […]
The one in board_BeforeAgesa() is supposed to be removed with !ROMCC_BOOTBLOCK transition.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37449 )
Change subject: sb/amd/cimx/sb800: Postpone Sb_Poweron_Init() call ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37449/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37449/5//COMMIT_MSG@10 PS5, Line 10: delayd delayed
Hello Piotr Król, build bot (Jenkins), Michał Żygowski, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37449
to look at the new patch set (#9).
Change subject: sb/amd/cimx/sb800: Postpone Sb_Poweron_Init() call ......................................................................
sb/amd/cimx/sb800: Postpone Sb_Poweron_Init() call
With LPC decode enables explicitly set in C env bootblock, this call can be delayd to happen before AMD_INIT_RESET.
Change-Id: I3a28eaa2cf70b770b022760a2380ded0f43e9a6f Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/amd/agesa/family14/Makefile.inc D src/cpu/amd/agesa/family14/romstage.c M src/drivers/amd/agesa/romstage.c M src/mainboard/amd/inagua/romstage.c M src/mainboard/amd/persimmon/romstage.c M src/mainboard/amd/south_station/romstage.c M src/mainboard/amd/union_station/romstage.c M src/mainboard/asrock/e350m1/romstage.c M src/mainboard/elmex/pcm205400/romstage.c M src/mainboard/gizmosphere/gizmo/romstage.c M src/mainboard/jetway/nf81-t56n-lf/romstage.c M src/mainboard/lippert/frontrunner-af/romstage.c M src/mainboard/lippert/toucan-af/romstage.c M src/mainboard/pcengines/apu1/romstage.c M src/northbridge/amd/agesa/family14/state_machine.c M src/northbridge/amd/agesa/state_machine.h 16 files changed, 35 insertions(+), 38 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/37449/9
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37449 )
Change subject: sb/amd/cimx/sb800: Postpone Sb_Poweron_Init() call ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37449/9/src/northbridge/amd/agesa/f... File src/northbridge/amd/agesa/family14/state_machine.c:
https://review.coreboot.org/c/coreboot/+/37449/9/src/northbridge/amd/agesa/f... PS9, Line 51: if (mct_cfg_lo & (1<<19)) {! trailing statements should be on next line
Hello Piotr Król, build bot (Jenkins), Michał Żygowski, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37449
to look at the new patch set (#10).
Change subject: sb/amd/cimx/sb800: Postpone Sb_Poweron_Init() call ......................................................................
sb/amd/cimx/sb800: Postpone Sb_Poweron_Init() call
With LPC decode enables explicitly set in C env bootblock, this call can be delayd to happen before AMD_INIT_RESET.
Change-Id: I3a28eaa2cf70b770b022760a2380ded0f43e9a6f Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/amd/agesa/family14/Makefile.inc D src/cpu/amd/agesa/family14/romstage.c M src/drivers/amd/agesa/romstage.c M src/mainboard/amd/inagua/romstage.c M src/mainboard/amd/persimmon/romstage.c M src/mainboard/amd/south_station/romstage.c M src/mainboard/amd/union_station/romstage.c M src/mainboard/asrock/e350m1/romstage.c M src/mainboard/elmex/pcm205400/romstage.c M src/mainboard/gizmosphere/gizmo/romstage.c M src/mainboard/jetway/nf81-t56n-lf/romstage.c M src/mainboard/lippert/frontrunner-af/romstage.c M src/mainboard/lippert/toucan-af/romstage.c M src/mainboard/pcengines/apu1/romstage.c M src/northbridge/amd/agesa/family14/state_machine.c M src/northbridge/amd/agesa/state_machine.h 16 files changed, 35 insertions(+), 38 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/37449/10
Hello Piotr Król, build bot (Jenkins), Michał Żygowski, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37449
to look at the new patch set (#12).
Change subject: sb/amd/cimx/sb800: Postpone Sb_Poweron_Init() call ......................................................................
sb/amd/cimx/sb800: Postpone Sb_Poweron_Init() call
With LPC decode enables explicitly set in C env bootblock, this call can be delayed to happen before AMD_INIT_RESET.
Change-Id: I3a28eaa2cf70b770b022760a2380ded0f43e9a6f Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/amd/agesa/family14/Makefile.inc D src/cpu/amd/agesa/family14/romstage.c M src/drivers/amd/agesa/romstage.c M src/mainboard/amd/inagua/romstage.c M src/mainboard/amd/persimmon/romstage.c M src/mainboard/amd/south_station/romstage.c M src/mainboard/amd/union_station/romstage.c M src/mainboard/asrock/e350m1/romstage.c M src/mainboard/elmex/pcm205400/romstage.c M src/mainboard/gizmosphere/gizmo/romstage.c M src/mainboard/jetway/nf81-t56n-lf/romstage.c M src/mainboard/lippert/frontrunner-af/romstage.c M src/mainboard/lippert/toucan-af/romstage.c M src/mainboard/pcengines/apu1/romstage.c M src/northbridge/amd/agesa/family14/state_machine.c M src/northbridge/amd/agesa/state_machine.h 16 files changed, 35 insertions(+), 38 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/37449/12
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37449 )
Change subject: sb/amd/cimx/sb800: Postpone Sb_Poweron_Init() call ......................................................................
Patch Set 12: Code-Review+2
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37449 )
Change subject: sb/amd/cimx/sb800: Postpone Sb_Poweron_Init() call ......................................................................
Patch Set 12:
(2 comments)
https://review.coreboot.org/c/coreboot/+/37449/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37449/5//COMMIT_MSG@10 PS5, Line 10: delayd
delayed
Done
https://review.coreboot.org/c/coreboot/+/37449/5/src/northbridge/amd/agesa/f... File src/northbridge/amd/agesa/family14/state_machine.c:
https://review.coreboot.org/c/coreboot/+/37449/5/src/northbridge/amd/agesa/f... PS5, Line 52: sb_Poweron_Init();
The one in board_BeforeAgesa() is supposed to be removed with !ROMCC_BOOTBLOCK transition.
Ack
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37449 )
Change subject: sb/amd/cimx/sb800: Postpone Sb_Poweron_Init() call ......................................................................
sb/amd/cimx/sb800: Postpone Sb_Poweron_Init() call
With LPC decode enables explicitly set in C env bootblock, this call can be delayed to happen before AMD_INIT_RESET.
Change-Id: I3a28eaa2cf70b770b022760a2380ded0f43e9a6f Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/37449 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Michał Żygowski michal.zygowski@3mdeb.com --- M src/cpu/amd/agesa/family14/Makefile.inc D src/cpu/amd/agesa/family14/romstage.c M src/drivers/amd/agesa/romstage.c M src/mainboard/amd/inagua/romstage.c M src/mainboard/amd/persimmon/romstage.c M src/mainboard/amd/south_station/romstage.c M src/mainboard/amd/union_station/romstage.c M src/mainboard/asrock/e350m1/romstage.c M src/mainboard/elmex/pcm205400/romstage.c M src/mainboard/gizmosphere/gizmo/romstage.c M src/mainboard/jetway/nf81-t56n-lf/romstage.c M src/mainboard/lippert/frontrunner-af/romstage.c M src/mainboard/lippert/toucan-af/romstage.c M src/mainboard/pcengines/apu1/romstage.c M src/northbridge/amd/agesa/family14/state_machine.c M src/northbridge/amd/agesa/state_machine.h 16 files changed, 35 insertions(+), 38 deletions(-)
Approvals: build bot (Jenkins): Verified Michał Żygowski: Looks good to me, approved
diff --git a/src/cpu/amd/agesa/family14/Makefile.inc b/src/cpu/amd/agesa/family14/Makefile.inc index 7db1fe4..1d68113 100644 --- a/src/cpu/amd/agesa/family14/Makefile.inc +++ b/src/cpu/amd/agesa/family14/Makefile.inc @@ -12,7 +12,6 @@ #
romstage-y += fixme.c -romstage-y += romstage.c
ramstage-y += fixme.c ramstage-y += chip_name.c diff --git a/src/cpu/amd/agesa/family14/romstage.c b/src/cpu/amd/agesa/family14/romstage.c deleted file mode 100644 index 54069cc3..0000000 --- a/src/cpu/amd/agesa/family14/romstage.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#include <northbridge/amd/agesa/state_machine.h> - -#include <sb_cimx.h> - -void platform_once(struct sysinfo *cb) -{ - sb_Poweron_Init(); - - board_BeforeAgesa(cb); -} diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index dbf8bd6..ee4d45e 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -29,11 +29,6 @@
void __weak board_BeforeAgesa(struct sysinfo *cb) { }
-void __weak platform_once(struct sysinfo *cb) -{ - board_BeforeAgesa(cb); -} - static void fill_sysinfo(struct sysinfo *cb) { memset(cb, 0, sizeof(*cb)); @@ -67,7 +62,7 @@ timestamp_init(timestamp_get()); timestamp_add_now(TS_START_ROMSTAGE);
- platform_once(cb); + board_BeforeAgesa(cb);
console_init(); } diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c index 3454ef8..43d9da9 100644 --- a/src/mainboard/amd/inagua/romstage.c +++ b/src/mainboard/amd/inagua/romstage.c @@ -15,11 +15,13 @@
#include <northbridge/amd/agesa/state_machine.h> #include <superio/smsc/kbc1100/kbc1100.h> +#include <sb_cimx.h>
#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
void board_BeforeAgesa(struct sysinfo *cb) { + sb_Poweron_Init(); kbc1100_early_init(0x2e); kbc1100_early_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index 1fbdd4b..7ccf167 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -16,10 +16,12 @@ #include <northbridge/amd/agesa/state_machine.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f81865f/f81865f.h> +#include <sb_cimx.h>
#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1)
void board_BeforeAgesa(struct sysinfo *cb) { + sb_Poweron_Init(); fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c index 1fbdd4b..7ccf167 100644 --- a/src/mainboard/amd/south_station/romstage.c +++ b/src/mainboard/amd/south_station/romstage.c @@ -16,10 +16,12 @@ #include <northbridge/amd/agesa/state_machine.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f81865f/f81865f.h> +#include <sb_cimx.h>
#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1)
void board_BeforeAgesa(struct sysinfo *cb) { + sb_Poweron_Init(); fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c index f2b00bc..af64ad8 100644 --- a/src/mainboard/amd/union_station/romstage.c +++ b/src/mainboard/amd/union_station/romstage.c @@ -14,7 +14,9 @@ */
#include <northbridge/amd/agesa/state_machine.h> +#include <sb_cimx.h>
void board_BeforeAgesa(struct sysinfo *cb) { + sb_Poweron_Init(); } diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index 292ecf2..27a1fac 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -16,11 +16,13 @@ #include <northbridge/amd/agesa/state_machine.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct5572d/nct5572d.h> +#include <sb_cimx.h>
#define SERIAL_DEV PNP_DEV(0x2e, NCT5572D_SP1)
void board_BeforeAgesa(struct sysinfo *cb) { + sb_Poweron_Init(); nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/elmex/pcm205400/romstage.c b/src/mainboard/elmex/pcm205400/romstage.c index 1fbdd4b..7ccf167 100644 --- a/src/mainboard/elmex/pcm205400/romstage.c +++ b/src/mainboard/elmex/pcm205400/romstage.c @@ -16,10 +16,12 @@ #include <northbridge/amd/agesa/state_machine.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f81865f/f81865f.h> +#include <sb_cimx.h>
#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1)
void board_BeforeAgesa(struct sysinfo *cb) { + sb_Poweron_Init(); fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c index 8dec7fe..7c3f534 100644 --- a/src/mainboard/gizmosphere/gizmo/romstage.c +++ b/src/mainboard/gizmosphere/gizmo/romstage.c @@ -15,7 +15,9 @@ */
#include <northbridge/amd/agesa/state_machine.h> +#include <sb_cimx.h>
void board_BeforeAgesa(struct sysinfo *cb) { + sb_Poweron_Init(); } diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c index a971c15..5e61bdd 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c @@ -17,11 +17,13 @@ #include <northbridge/amd/agesa/state_machine.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f71869ad/f71869ad.h> +#include <sb_cimx.h>
/* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */ #define SERIAL_DEV PNP_DEV(0x2e, F71869AD_SP1)
void board_BeforeAgesa(struct sysinfo *cb) { + sb_Poweron_Init(); fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c index 83d5a6d..f8e6091 100644 --- a/src/mainboard/lippert/frontrunner-af/romstage.c +++ b/src/mainboard/lippert/frontrunner-af/romstage.c @@ -15,10 +15,12 @@
#include <northbridge/amd/agesa/state_machine.h> #include <superio/smsc/smscsuperio/smscsuperio.h> +#include <sb_cimx.h>
#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)
void board_BeforeAgesa(struct sysinfo *cb) { + sb_Poweron_Init(); smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c index 7ca9dcb..ebbe4fc 100644 --- a/src/mainboard/lippert/toucan-af/romstage.c +++ b/src/mainboard/lippert/toucan-af/romstage.c @@ -16,10 +16,12 @@ #include <northbridge/amd/agesa/state_machine.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627dhg/w83627dhg.h> +#include <sb_cimx.h>
#define SERIAL_DEV PNP_DEV(0x4e, W83627DHG_SP1)
void board_BeforeAgesa(struct sysinfo *cb) { + sb_Poweron_Init(); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/pcengines/apu1/romstage.c b/src/mainboard/pcengines/apu1/romstage.c index 89bf304..da0e0d3 100644 --- a/src/mainboard/pcengines/apu1/romstage.c +++ b/src/mainboard/pcengines/apu1/romstage.c @@ -21,6 +21,7 @@ #include <superio/nuvoton/nct5104d/nct5104d.h> #include "gpio_ftns.h" #include <SB800.h> +#include <sb_cimx.h>
#define SIO_PORT 0x2e #define SERIAL_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1) @@ -60,6 +61,7 @@
void board_BeforeAgesa(struct sysinfo *cb) { + sb_Poweron_Init(); early_lpc_init(); nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/northbridge/amd/agesa/family14/state_machine.c b/src/northbridge/amd/agesa/family14/state_machine.c index df55efa..91a8f70 100644 --- a/src/northbridge/amd/agesa/family14/state_machine.c +++ b/src/northbridge/amd/agesa/family14/state_machine.c @@ -29,24 +29,30 @@
void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) { + if (!boot_cpu()) + return; + + if (!CONFIG(ROMCC_BOOTBLOCK)) + sb_Poweron_Init(); + /* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all * would fail later in AmdInitPost(), when DRAM is already configured * and C6DramLock bit has been set. * * As a workaround, do a hard reset to clear C6DramLock bit. */ + #ifdef __SIMPLE_DEVICE__ pci_devfn_t dev = PCI_DEV(0, 0x18, 2); #else struct device *dev = pcidev_on_root(0x18, 2); #endif - if (boot_cpu()) { - u32 mct_cfg_lo = pci_read_config32(dev, 0x118); - if (mct_cfg_lo & (1<<19)) { - printk(BIOS_CRIT, "C6DramLock is set, resetting\n"); - system_reset(); - } + u32 mct_cfg_lo = pci_read_config32(dev, 0x118); + if (mct_cfg_lo & (1<<19)) { + printk(BIOS_CRIT, "C6DramLock is set, resetting\n"); + system_reset(); } + }
void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early) diff --git a/src/northbridge/amd/agesa/state_machine.h b/src/northbridge/amd/agesa/state_machine.h index 9de011a..c4a3054 100644 --- a/src/northbridge/amd/agesa/state_machine.h +++ b/src/northbridge/amd/agesa/state_machine.h @@ -45,7 +45,6 @@ };
void board_BeforeAgesa(struct sysinfo *cb); -void platform_once(struct sysinfo *cb);
void agesa_set_interface(struct sysinfo *cb);
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