Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37332 )
Change subject: mb/pcengines/apu1: initialize serial port in bootblock ......................................................................
mb/pcengines/apu1: initialize serial port in bootblock
TEST=boot PC Engines apu1 with C bootblock patch and launch Debian with Linux kernel 4.14.50
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I36af6d3871a57f462a7508745663d9759de1c47d --- A src/mainboard/pcengines/apu1/bootblock.c M src/mainboard/pcengines/apu1/romstage.c 2 files changed, 26 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/37332/1
diff --git a/src/mainboard/pcengines/apu1/bootblock.c b/src/mainboard/pcengines/apu1/bootblock.c new file mode 100644 index 0000000..5a3d97c --- /dev/null +++ b/src/mainboard/pcengines/apu1/bootblock.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <device/pnp.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct5104d/nct5104d.h> + +#define SIO_PORT 0x2e +#define SERIAL_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1) + + +void bootblock_mainboard_early_init(void) +{ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/pcengines/apu1/romstage.c b/src/mainboard/pcengines/apu1/romstage.c index 89bf304..134382f 100644 --- a/src/mainboard/pcengines/apu1/romstage.c +++ b/src/mainboard/pcengines/apu1/romstage.c @@ -61,5 +61,4 @@ void board_BeforeAgesa(struct sysinfo *cb) { early_lpc_init(); - nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); }
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37332 )
Change subject: mb/pcengines/apu1: initialize serial port in bootblock ......................................................................
Patch Set 1: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/37332/1/src/mainboard/pcengines/apu... File src/mainboard/pcengines/apu1/bootblock.c:
https://review.coreboot.org/c/coreboot/+/37332/1/src/mainboard/pcengines/apu... PS1, Line 15: #include <device/pnp.h> why?
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37332 )
Change subject: mb/pcengines/apu1: initialize serial port in bootblock ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37332/1/src/mainboard/pcengines/apu... File src/mainboard/pcengines/apu1/bootblock.c:
https://review.coreboot.org/c/coreboot/+/37332/1/src/mainboard/pcengines/apu... PS1, Line 15: #include <device/pnp.h>
why?
Doesn't PNP_DEV macro require include?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37332 )
Change subject: mb/pcengines/apu1: initialize serial port in bootblock ......................................................................
Patch Set 1: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/37332/1/src/mainboard/pcengines/apu... File src/mainboard/pcengines/apu1/bootblock.c:
https://review.coreboot.org/c/coreboot/+/37332/1/src/mainboard/pcengines/apu... PS1, Line 15: #include <device/pnp.h>
Doesn't PNP_DEV macro require include?
Yes, but not this one. Rather:
src/include/device/pnp_type.h: #define PNP_DEV(PORT, FUNC) (((PORT) << 8) | (FUNC))
Kyösti Mälkki has uploaded a new patch set (#2) to the change originally created by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/37332 )
Change subject: mb/pcengines/apu1: initialize serial port in bootblock ......................................................................
mb/pcengines/apu1: initialize serial port in bootblock
TEST=boot PC Engines apu1 with C bootblock patch and launch Debian with Linux kernel 4.14.50
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I36af6d3871a57f462a7508745663d9759de1c47d --- M src/mainboard/pcengines/apu1/Kconfig A src/mainboard/pcengines/apu1/bootblock.c M src/mainboard/pcengines/apu1/romstage.c 3 files changed, 26 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/37332/2
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37332 )
Change subject: mb/pcengines/apu1: initialize serial port in bootblock ......................................................................
Patch Set 2:
Added file bootblock.c might not get linked in yet.
Kyösti Mälkki has uploaded a new patch set (#3) to the change originally created by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/37332 )
Change subject: pcengines/apu1: Switch away from ROMCC_BOOTBLOCK ......................................................................
pcengines/apu1: Switch away from ROMCC_BOOTBLOCK
TEST=boot PC Engines apu1 with C bootblock patch and launch Debian with Linux kernel 4.14.50
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I36af6d3871a57f462a7508745663d9759de1c47d --- M src/mainboard/pcengines/apu1/Kconfig M src/mainboard/pcengines/apu1/Makefile.inc A src/mainboard/pcengines/apu1/bootblock.c M src/mainboard/pcengines/apu1/romstage.c 4 files changed, 28 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/37332/3
Hello Kyösti Mälkki, HAOUAS Elyes, Piotr Król, Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37332
to look at the new patch set (#6).
Change subject: pcengines/apu1: Switch away from ROMCC_BOOTBLOCK ......................................................................
pcengines/apu1: Switch away from ROMCC_BOOTBLOCK
TEST=boot PC Engines apu1 with C bootblock patch and launch Debian with Linux kernel 4.14.50
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I36af6d3871a57f462a7508745663d9759de1c47d --- M src/mainboard/pcengines/apu1/Kconfig M src/mainboard/pcengines/apu1/Makefile.inc A src/mainboard/pcengines/apu1/bootblock.c M src/mainboard/pcengines/apu1/romstage.c 4 files changed, 27 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/37332/6
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37332 )
Change subject: pcengines/apu1: Switch away from ROMCC_BOOTBLOCK ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37332/1/src/mainboard/pcengines/apu... File src/mainboard/pcengines/apu1/bootblock.c:
https://review.coreboot.org/c/coreboot/+/37332/1/src/mainboard/pcengines/apu... PS1, Line 15: #include <device/pnp.h>
Yes, but not this one. Rather: […]
Done
Kyösti Mälkki has uploaded a new patch set (#12) to the change originally created by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/37332 )
Change subject: pcengines/apu1: Switch away from ROMCC_BOOTBLOCK ......................................................................
pcengines/apu1: Switch away from ROMCC_BOOTBLOCK
TEST=boot PC Engines apu1 with C bootblock patch and launch Debian with Linux kernel 4.14.50
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I36af6d3871a57f462a7508745663d9759de1c47d --- M src/mainboard/pcengines/apu1/Kconfig M src/mainboard/pcengines/apu1/Makefile.inc A src/mainboard/pcengines/apu1/bootblock.c M src/mainboard/pcengines/apu1/romstage.c 4 files changed, 27 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/37332/12
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37332 )
Change subject: pcengines/apu1: Switch away from ROMCC_BOOTBLOCK ......................................................................
Patch Set 14: Code-Review+1
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37332 )
Change subject: pcengines/apu1: Switch away from ROMCC_BOOTBLOCK ......................................................................
Patch Set 14: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37332 )
Change subject: pcengines/apu1: Switch away from ROMCC_BOOTBLOCK ......................................................................
Patch Set 15: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37332 )
Change subject: pcengines/apu1: Switch away from ROMCC_BOOTBLOCK ......................................................................
pcengines/apu1: Switch away from ROMCC_BOOTBLOCK
TEST=boot PC Engines apu1 with C bootblock patch and launch Debian with Linux kernel 4.14.50
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I36af6d3871a57f462a7508745663d9759de1c47d Reviewed-on: https://review.coreboot.org/c/coreboot/+/37332 Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: HAOUAS Elyes ehaouas@noos.fr Reviewed-by: Kyösti Mälkki kyosti.malkki@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/pcengines/apu1/Kconfig M src/mainboard/pcengines/apu1/Makefile.inc A src/mainboard/pcengines/apu1/bootblock.c M src/mainboard/pcengines/apu1/romstage.c 4 files changed, 27 insertions(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved HAOUAS Elyes: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved
diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig index 1684236..3396845 100644 --- a/src/mainboard/pcengines/apu1/Kconfig +++ b/src/mainboard/pcengines/apu1/Kconfig @@ -18,7 +18,6 @@
config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/pcengines/apu1/Makefile.inc b/src/mainboard/pcengines/apu1/Makefile.inc index 543ac97..3aa3bbe 100644 --- a/src/mainboard/pcengines/apu1/Makefile.inc +++ b/src/mainboard/pcengines/apu1/Makefile.inc @@ -21,6 +21,8 @@ pci$(stripped_ahcibios_id).rom-type := optionrom endif
+bootblock-y += bootblock.c + romstage-y += buildOpts.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/pcengines/apu1/bootblock.c b/src/mainboard/pcengines/apu1/bootblock.c new file mode 100644 index 0000000..2d34cba --- /dev/null +++ b/src/mainboard/pcengines/apu1/bootblock.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <device/pnp_type.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct5104d/nct5104d.h> + +#define SIO_PORT 0x2e +#define SERIAL_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1) + +void bootblock_mainboard_early_init(void) +{ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/pcengines/apu1/romstage.c b/src/mainboard/pcengines/apu1/romstage.c index da0e0d3..20a6318 100644 --- a/src/mainboard/pcengines/apu1/romstage.c +++ b/src/mainboard/pcengines/apu1/romstage.c @@ -61,7 +61,5 @@
void board_BeforeAgesa(struct sysinfo *cb) { - sb_Poweron_Init(); early_lpc_init(); - nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); }
-
Angel Pons (Code Review) -
HAOUAS Elyes (Code Review)
-
Kyösti Mälkki (Code Review)
-
Michał Żygowski (Code Review)
-
Patrick Georgi (Code Review)