Change in coreboot[master]: mb/google/drallion: Enable/disable GPIO clock gating

[John Su (Code Review)]

John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37665 )

Change subject: mb/google/drallion: Enable/disable GPIO clock gating
......................................................................

mb/google/drallion: Enable/disable GPIO clock gating

Follow CB:34180. Before the system enters S0ix, each GPIO community
will have its dynamic clock gating turned on. Upon return
to S0, the dynamic clock gating will be turned back off.

BUG=b:144002424
BRANCH=none

Change-Id: Iff121dfb0cd3d37a1da6ca31e1aff06ac33e037a
Signed-off-by: John Su 
---
M src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl
1 file changed, 13 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/37665/1

diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl b/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl
index dbe487e..608e4e0 100644
--- a/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl
+++ b/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl
@@ -16,6 +16,15 @@
 #define CAM_EN GPP_B11 /* Active low */
 #define TS_PD GPP_E7
 #define HDMI_PD GPP_E16
+#include <intelblocks/gpio.h>
+
+Method (LOCL, 1, Serialized)
+{
+	For (Local0 = 0, Local0 < 5, Local0++)
+	{
+		_SB.PCI0.CGPM (Local0, Arg0)
+	}
+}

/* Method called from LPIT prior to enter s0ix state */
 Method (MS0X, 1)
@@ -25,11 +34,13 @@
    	_SB.PCI0.STXS (CAM_EN)
    	/* Turn off HDMI power */
    	_SB.PCI0.CTXS (HDMI_PD)
+		LOCL (MISCCFG_ENABLE_GPIO_PM_CONFIG)
    } Else {
    	/* Turn on camera power */
    	_SB.PCI0.CTXS (CAM_EN)
    	/* Turn on HDMI power */
    	_SB.PCI0.STXS (HDMI_PD)
+		LOCL (0)
    }
 }

@@ -42,10 +53,12 @@
    _SB.PCI0.CTXS (TS_PD)
    /* Clear HDMI power to avoid leakage */
    _SB.PCI0.CTXS (HDMI_PD)
+	LOCL (MISCCFG_ENABLE_GPIO_PM_CONFIG)
 }

/* Method called from _WAK prior to wakeup */
 Method (MWAK, 1)
 {
    _SB.PCI0.LPCB.EC0.WAK (Arg0)
+	LOCL (0)
 }

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37665 )

Change subject: mb/google/drallion: Enable/disable GPIO clock gating
......................................................................

Patch Set 1:

(2 comments)

https://review.coreboot.org/c/coreboot/+/37665/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/37665/1//COMMIT_MSG@9 
PS1, Line 9: CB:34180
Please add the git commit message summary in ().

https://review.coreboot.org/c/coreboot/+/37665/1//COMMIT_MSG@11 
PS1, Line 11: to S0, the
Fits on the line above?

[Mathew King (Code Review)]

Mathew King has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37665 )

Change subject: mb/google/drallion: Enable/disable GPIO clock gating
......................................................................

Patch Set 1: Code-Review+1

[Duncan Laurie (Code Review)]

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37665 )

Change subject: mb/google/drallion: Enable/disable GPIO clock gating
......................................................................

Patch Set 1:

I think should be able to go into the SOC code at src/soc/intel/cannonlake/acpi/lpit.asl

Subrata, do you see any issue with that?

[John Su (Code Review)]

Hello EricR Lai, Subrata Banik, Mathew King, Duncan Laurie, Tim Wawrzynczak, build bot (Jenkins), Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/37665

to look at the new patch set (#2).

Change subject: mb/google/drallion: Enable/disable GPIO clock gating
......................................................................

mb/google/drallion: Enable/disable GPIO clock gating

Before the system enters S0ix, each GPIO community will have
its dynamic clock gating turned on. Upon return to S0,
the dynamic clock gating will be turned back off.

BUG=b:144002424
BRANCH=none

Change-Id: Iff121dfb0cd3d37a1da6ca31e1aff06ac33e037a
Signed-off-by: John Su 
---
M src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl
1 file changed, 13 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/37665/2

[John Su (Code Review)]

John Su has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37665 )

Change subject: mb/google/drallion: Enable/disable GPIO clock gating
......................................................................

Patch Set 2:

(2 comments)

https://review.coreboot.org/c/coreboot/+/37665/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/37665/1//COMMIT_MSG@9 
PS1, Line 9: CB:34180
> Please add the git commit message summary in ().

Ack

https://review.coreboot.org/c/coreboot/+/37665/1//COMMIT_MSG@11 
PS1, Line 11: to S0, the
> Fits on the line above?

Ack

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37665 )

Change subject: mb/google/drallion: Enable/disable GPIO clock gating
......................................................................

Patch Set 2:
> Patch Set 1:
>
> I think should be able to go into the SOC code at src/soc/intel/cannonlake/acpi/lpit.asl
>
> Subrata, do you see any issue with that?

This is generic, should go to soc directory

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37665 )

Change subject: mb/google/drallion: Enable/disable GPIO clock gating
......................................................................

Patch Set 2: Code-Review+1

Lets move into soc directory

[EricR Lai (Code Review)]

EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37665 )

Change subject: mb/google/drallion: Enable/disable GPIO clock gating
......................................................................

Patch Set 3:
> Patch Set 2: Code-Review+1
>
> Lets move into soc directory

please try this CL:https://review.coreboot.org/c/coreboot/+/37685

[John Su (Code Review)]

John Su has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/37665 )

Change subject: mb/google/drallion: Enable/disable GPIO clock gating
......................................................................

Abandoned