John Su has uploaded this change for review.
mb/google/drallion: Enable/disable GPIO clock gating
Follow CB:34180. Before the system enters S0ix, each GPIO community
will have its dynamic clock gating turned on. Upon return
to S0, the dynamic clock gating will be turned back off.
BUG=b:144002424
BRANCH=none
Change-Id: Iff121dfb0cd3d37a1da6ca31e1aff06ac33e037a
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
---
M src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl
1 file changed, 13 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/37665/1
diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl b/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl
index dbe487e..608e4e0 100644
--- a/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl
+++ b/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl
@@ -16,6 +16,15 @@
#define CAM_EN GPP_B11 /* Active low */
#define TS_PD GPP_E7
#define HDMI_PD GPP_E16
+#include <intelblocks/gpio.h>
+
+Method (LOCL, 1, Serialized)
+{
+ For (Local0 = 0, Local0 < 5, Local0++)
+ {
+ \_SB.PCI0.CGPM (Local0, Arg0)
+ }
+}
/* Method called from LPIT prior to enter s0ix state */
Method (MS0X, 1)
@@ -25,11 +34,13 @@
\_SB.PCI0.STXS (CAM_EN)
/* Turn off HDMI power */
\_SB.PCI0.CTXS (HDMI_PD)
+ LOCL (MISCCFG_ENABLE_GPIO_PM_CONFIG)
} Else {
/* Turn on camera power */
\_SB.PCI0.CTXS (CAM_EN)
/* Turn on HDMI power */
\_SB.PCI0.STXS (HDMI_PD)
+ LOCL (0)
}
}
@@ -42,10 +53,12 @@
\_SB.PCI0.CTXS (TS_PD)
/* Clear HDMI power to avoid leakage */
\_SB.PCI0.CTXS (HDMI_PD)
+ LOCL (MISCCFG_ENABLE_GPIO_PM_CONFIG)
}
/* Method called from _WAK prior to wakeup */
Method (MWAK, 1)
{
\_SB.PCI0.LPCB.EC0.WAK (Arg0)
+ LOCL (0)
}
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