coreboot-gerrit January 2019

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Change in ...coreboot[master]: mb/(ICH7): Do not try to rewrite on V1CAP register
by HAOUAS Elyes (Code Review) 18 Mar '19

18 Mar '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31004 Change subject: mb/(ICH7): Do not try to rewrite on V1CAP register ...................................................................... mb/(ICH7): Do not try to rewrite on V1CAP register V1CAP is a write-once register, and it is already programmd in intel/i945/early_init.c Change-Id: I4469cb7505d584f10c98aec579a2d78bf1950bf3 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/apple/macbook21/romstage.c M src/mainboard/getac/p470/romstage.c M src/mainboard/ibase/mb899/romstage.c M src/mainboard/intel/d945gclf/romstage.c M src/mainboard/lenovo/t60/romstage.c M src/mainboard/lenovo/x60/romstage.c M src/mainboard/lenovo/z61t/romstage.c 7 files changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/31004/1 diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index ad184a8..4e1fd96 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -143,8 +143,6 @@ { /* V0CTL Virtual Channel 0 Resource Control */ RCBA32(0x0014) = 0x80000001; - /* V1CAP Virtual Channel 1 Resource Capability */ - RCBA32(0x001c) = 0x03128010; /* Device 1f interrupt pin register */ RCBA32(0x3100) = 0x00042210; diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index 471977f..6c5b441 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -146,7 +146,6 @@ { /* Set up virtual channel 0 */ //RCBA32(0x0014) = 0x80000001; - //RCBA32(0x001c) = 0x03128010; /* Device 1f interrupt pin register */ RCBA32(D31IP) = 0x00042220; diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 9eaa8de..aa8878d 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -124,7 +124,6 @@ { /* Set up virtual channel 0 */ //RCBA32(0x0014) = 0x80000001; - //RCBA32(0x001c) = 0x03128010; /* Device 1f interrupt pin register */ RCBA32(D31IP) = 0x00042210; diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index 5e3535a..35213a9 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -48,7 +48,6 @@ { /* Set up virtual channel 0 */ //RCBA32(0x0014) = 0x80000001; - //RCBA32(0x001c) = 0x03128010; /* dev irq route register */ RCBA16(D31IR) = 0x0132; diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index 3017357..f10f447 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -75,7 +75,6 @@ { /* Set up virtual channel 0 */ RCBA32(V0CTL) = 0x80000001; - RCBA32(V1CAP) = 0x03128010; /* Device 1f interrupt pin register */ RCBA32(D31IP) = 0x00001230; diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 6f66c88..1a2bc28 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -74,7 +74,6 @@ { /* Set up virtual channel 0 */ RCBA32(V0CTL) = 0x80000001; - RCBA32(V1CAP) = 0x03128010; /* Device 1f interrupt pin register */ RCBA32(D31IP) = 0x00001230; diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c index 6eceaeb..5dae395 100644 --- a/src/mainboard/lenovo/z61t/romstage.c +++ b/src/mainboard/lenovo/z61t/romstage.c @@ -75,7 +75,6 @@ { /* Set up virtual channel 0 */ RCBA32(V0CTL) = 0x80000001; - RCBA32(V1CAP) = 0x03128010; /* Device 1f interrupt pin register */ RCBA32(D31IP) = 0x00001230; -- To view, visit https://review.coreboot.org/c/coreboot/+/31004 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4469cb7505d584f10c98aec579a2d78bf1950bf3 Gerrit-Change-Number: 31004 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 11

Change in ...coreboot[master]: nb/intel/i945: Don't try to rewrite on SLOTCAP
by HAOUAS Elyes (Code Review) 18 Mar '19

18 Mar '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31036 Change subject: nb/intel/i945: Don't try to rewrite on SLOTCAP ...................................................................... nb/intel/i945: Don't try to rewrite on SLOTCAP SLOTCAP is R/WO, it becomes RO after the first write. Change-Id: I27579bc634e357490defabb041457aaa010fb1c8 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/early_init.c 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/31036/1 diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 09a18e3..15c3a33 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -719,9 +719,6 @@ reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x328); pci_write_config32(PCI_DEV(0, 0x01, 0), 0x328, reg32); - reg8 = pci_read_config8(PCI_DEV(0, 0x01, 0), SLOTCAP); - pci_write_config8(PCI_DEV(0, 0x01, 0), SLOTCAP, reg8); - /* Additional PCIe graphics setup */ reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xf0); reg32 |= (3 << 26); -- To view, visit https://review.coreboot.org/c/coreboot/+/31036 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27579bc634e357490defabb041457aaa010fb1c8 Gerrit-Change-Number: 31036 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 8

Change in ...coreboot[master]: src/mb/sifive/hifive-unleashed: initialize Gigabit Ethernet Controller
by Xiang Wang (Code Review) 18 Mar '19

18 Mar '19

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31059 Change subject: src/mb/sifive/hifive-unleashed: initialize Gigabit Ethernet Controller ...................................................................... src/mb/sifive/hifive-unleashed: initialize Gigabit Ethernet Controller Initialize the clock of Gigabit Ethernet Controller and reset the PHY. Change-Id: I172dc518c9b48c122289bba5a65beece925410d4 Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/mainboard/sifive/hifive-unleashed/romstage.c M src/soc/sifive/fu540/clock.c 2 files changed, 61 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/31059/1 diff --git a/src/mainboard/sifive/hifive-unleashed/romstage.c b/src/mainboard/sifive/hifive-unleashed/romstage.c index 17d1aef..4eb7d55 100644 --- a/src/mainboard/sifive/hifive-unleashed/romstage.c +++ b/src/mainboard/sifive/hifive-unleashed/romstage.c @@ -27,6 +27,7 @@ #include <symbols.h> #include <cbfs.h> #include <soc/otp.h> +#include <soc/addressmap.h> static void update_dtb(void) { @@ -52,6 +53,30 @@ OTHER_HLS(i)->fdt = (void *)dtb_target; } +static void nsleep(long nsec) +{ + long setp = 600; + while(*(volatile long*)&nsec > 0) + *(volatile long*)&nsec -= setp; +} + +#define GPIO_REG(n) (*(uint32_t*)(FU540_GPIO + (n))) +#define GPIO_OUTPUT_EN 0x08 +#define GPIO_OUTPUT_VAL 0x0c + +static void phy_init(void) +{ +#define PHY_NRESET 0x1000 + nsleep(2000000); + __sync_fetch_and_or(&GPIO_REG(GPIO_OUTPUT_VAL), PHY_NRESET); + __sync_fetch_and_or(&GPIO_REG(GPIO_OUTPUT_EN), PHY_NRESET); + nsleep(100); + __sync_fetch_and_and(&GPIO_REG(GPIO_OUTPUT_VAL), ~PHY_NRESET); + nsleep(100); + __sync_fetch_and_or(&GPIO_REG(GPIO_OUTPUT_VAL), PHY_NRESET); + nsleep(15000000); +} + void main(void) { console_init(); @@ -71,6 +96,7 @@ uart_init(CONFIG_UART_FOR_CONSOLE); sdram_init(); + phy_init(); cbmem_initialize_empty(); diff --git a/src/soc/sifive/fu540/clock.c b/src/soc/sifive/fu540/clock.c index 597b206..7194c3c 100644 --- a/src/soc/sifive/fu540/clock.c +++ b/src/soc/sifive/fu540/clock.c @@ -59,6 +59,8 @@ #define PRCI_DDRPLLCFG1_MASK (1u << 31) +#define PRCI_GEMGXLPPLCFG1_MASK (1u << 31) + #define PRCI_CORECLKSEL_CORECLKSEL 1 #define PRCI_DEVICESRESET_DDR_CTRL_RST_N(x) (((x) & 0x1) << 0) @@ -141,6 +143,15 @@ .fse = 1, }; +static const struct pll_settings gemgxlpll_settings = { + .divr = 0, + .divf = 59, + .divq = 5, + .range = 4, + .bypass = 0, + .fse = 1, +}; + static void init_coreclk(void) { // switch coreclk to input reference frequency before modifying PLL @@ -168,6 +179,19 @@ write32(&prci->ddrpllcfg1, cfg1); } +static void init_gemgxlclk(void) +{ + u32 cfg1 = read32(&prci->gemgxlpllcfg1); + clrbits_le32(&cfg1, PRCI_GEMGXLPPLCFG1_MASK); + write32(&prci->gemgxlpllcfg1,cfg1); + + configure_pll(&prci->gemgxlpllcfg0, &gemgxlpll_settings); + + setbits_le32(&cfg1, PRCI_GEMGXLPPLCFG1_MASK); + write32(&prci->gemgxlpllcfg1,cfg1); +} + + #define FU540_UART_DEVICES 2 #define FU540_UART_REG_DIV 0x18 #define FU540_UART_DIV_VAL 4 @@ -227,6 +251,17 @@ // device? for (int i = 0; i < 256; i++) asm volatile ("nop"); + + init_gemgxlclk(); + + write32(&prci->devicesresetreg, + PRCI_DEVICESRESET_DDR_CTRL_RST_N(1) | + PRCI_DEVICESRESET_DDR_AXI_RST_N(1) | + PRCI_DEVICESRESET_DDR_AHB_RST_N(1) | + PRCI_DEVICESRESET_DDR_PHY_RST_N(1) | + PRCI_DEVICESRESET_GEMGXL_RST_N(1)); + + asm volatile ("fence"); } #endif /* ENV_ROMSTAGE */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31059 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I172dc518c9b48c122289bba5a65beece925410d4 Gerrit-Change-Number: 31059 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-MessageType: newchange

6 20

Change in ...coreboot[master]: mb/google/hatch: Reconfigure SD card detect GPIO host software ownership
by Krishna P Bhat D (Code Review) 18 Mar '19

18 Mar '19

Krishna P Bhat D has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31178 Change subject: mb/google/hatch: Reconfigure SD card detect GPIO host software ownership ...................................................................... mb/google/hatch: Reconfigure SD card detect GPIO host software ownership This implementation reconfigures SD card detect GPIO(GPP_G5) host ownership to GPIO driver mode. BUG=b:123432607 BRANCH=None TEST=Check SD card gets detected and data transfer working. Change-Id: Id214184f3e183f6feb6887484cd4ccd3bab65b1a Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> --- M src/mainboard/google/hatch/variants/baseboard/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/31178/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index a078997..4b923829 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -138,7 +138,7 @@ /* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), /* SD_CD# */ - PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), + PAD_CFG_GPI_GPIO_DRIVER(GPP_G5, NONE, DEEP), /* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), /* SD_WP => NC */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31178 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id214184f3e183f6feb6887484cd4ccd3bab65b1a Gerrit-Change-Number: 31178 Gerrit-PatchSet: 1 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-MessageType: newchange

7 15

Change in ...coreboot[master]: 1st version 1:1 copy from old wiki https://www.coreboot.org/Board:asu...
by Balázs Vinarz (Code Review) 15 Mar '19

15 Mar '19

Balázs Vinarz has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30895 Change subject: 1st version 1:1 copy from old wiki https://www.coreboot.org/Board:asus/f2a85-m ...................................................................... 1st version 1:1 copy from old wiki https://www.coreboot.org/Board:asus/f2a85-m Change-Id: I4d195f4833ba71fdc559815cafb0f5d0d254e897 Signed-off-by: Balazs Vinarz <vinibali1(a)gmail.com> --- A Documentation/mainboard/asus/f2a85-m.md 1 file changed, 271 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/30895/1 diff --git a/Documentation/mainboard/asus/f2a85-m.md b/Documentation/mainboard/asus/f2a85-m.md new file mode 100644 index 0000000..c4ee0cf --- /dev/null +++ b/Documentation/mainboard/asus/f2a85-m.md @@ -0,0 +1,271 @@ +Disclaimer: This board is not widely sold any longer. However, refer to F2A85 series status for newer models. ASUS F2A85 PRO should be work in progress (WIP). +Contents + + 1 Status + 1.1 Supported processing units + 1.1.1 CPUs + 1.1.2 APUs + 1.2 Notes + 1.3 TODOs + 2 UEFI builds that allow flash chip access + 3 Hardware info + 3.1 DDR voltage controller + 3.2 The ASUS digi VRM + 3.3 Memory + 4 See also + 4.1 F2A85 series status + 5 References + +Status +Device/functionality Status Comments +CPU +CPU works OK the board will start with an AMD A8-5500 +L1 cache enabled OK +L2 cache enabled OK +L3 cache enabled N/A +Multiple CPU support OK +Multi-core support OK +Hardware virtualization Untested +RAM +EDO N/A +SDRAM N/A +SO-DIMM N/A +DDR N/A +DDR2 N/A +DDR3 OK Please select right voltage in menuconfig! Default is 1.5V but some DIMMs need more or less! +Dual channel support OK +ECC support N/A +On-board Hardware +On-board IDE 3.5" N/A +On-board IDE 2.5" N/A +On-board SATA OK Tested all ports of sixpack. +On-board SCSI N/A +On-board USB OK Issues with XHCI exist with Asus' BIOS as well +On-board VGA OK Use dd to extract the legacy BIOS, HDMI untested +On-board Ethernet OK +On-board Audio OK tested with headphones in line-out (lime colored) +On-board Modem N/A +On-board FireWire N/A +On-board Smartcard reader N/A +On-board CompactFlash N/A +On-board PCMCIA N/A +On-board Wifi N/A +On-board Bluetooth N/A +On-board SD card reader N/A +Add-on slots/cards +ISA add-on cards N/A +Audio/Modem-Riser (AMR/CNR) cards N/A +PCI add-on cards OK +Mini-PCI add-on cards N/A +Mini-PCI-Express add-on cards Unknown +PCI-X add-on cards N/A +AGP graphics cards N/A +PCI Express x1 add-on cards OK +PCI Express x2 add-on cards N/A +PCI Express x4 add-on cards OK +PCI Express x8 add-on cards N/A +PCI Express x16 add-on cards OK +PCI Express x32 add-on cards N/A +HTX add-on cards N/A +Legacy / Super I/O +Floppy N/A +Serial port 1 (COM1) OK +Serial port 2 (COM2) N/A +Parallel port N/A +PS/2 keyboard OK +PS/2 mouse Untested +Game port N/A +Infrared ? +PC speaker OK +DiskOnChip N/A +Input +Trackpoint N/A +Touchpad N/A +Fn Hotkeys N/A +Fingerprint Reader N/A +Laptop +Docking VGA N/A +Docking LAN N/A +Docking USB N/A +Docking Audio N/A +Docking Displayport N/A +Thinklight N/A +Webcam N/A +Miscellaneous +Sensors / fan control Untested +Hardware watchdog Unknown +SMBus Unknown +CAN bus N/A +CPU frequency scaling OK +Other powersaving features ? +ACPI OK ACPI power button event works, suspend is WIP (work in progress). +Reboot OK warm reboot from Asus' BIOS to coreboot does not work, use reset button after the first time you flash coreboot +Poweroff OK +Suspend OK +Nonstandard LEDs OK +High precision event timers (HPET) OK +Random number generator (RNG) ? +Wake on modem ring Untested +Wake on LAN Untested +Wake on keyboard Untested +Wake on mouse Untested +TPM Unknown +Flashrom OK +Supported processing units + +ASUS F2A85-M CPU specification:[1] + + AMD Socket FM2 Athlon�/A- Series Processors + Supports CPU up to 4 cores + Supports AMD� Turbo Core 3.0 Technology + Addenum: AMD Sempron X2 250[2] + +Note: Only AMD Virgo: "Trinity" desktop processing units are supported (see list below) but with a hack also Richland desktop processing units might work (contact via mailing list for details). Wikipedia's list of Trinity processors might be more actively maintained. +CPUs + + AMD Athlon X2 340 + AMD Athlon X4 740 + AMD Athlon X4 750k + +APUs + +The CPU architecture in these APUs are Piledriver, and their GPU is TeraScale 3 (VLIW4-based). + + AMD A4-5300 + AMD A4-5300B + AMD A6-5400K + AMD A6-5400B + AMD A8-5500 + AMD A8-5500B + AMD A8-5600K + AMD A10-5700 + AMD A10-5800B + AMD A10-5800K + AMD FirePro A300 - Only sold by OEM + AMD FirePro A320 - Only sold by OEM + +Notes + + Retrieve the VGA optionrom from the vendor EFI binary by running: + +dd if=/dev/mem of=vgabios.bin bs=1k count=64 skip=768 + +(source) + +For internal VGA: Boot the legacy BIOS, and use VGA_support chapter + + Add the extracted VGA optionrom in menuconfig. The device ID for the APU graphics varies, run 'lspci -nn | grep VGA' to find the right ID. + If you use PS/2 de-select legacy free + De-select running option ROMs, Seabios will run the ROMs that coreboot loads into memory so you should get a text display from Seabios + It is required that seabios is the coreboot payload for the F2A85-M or the internal VGA will not be initialized. But read SeaBIOS for how to add payloads to SeaBIOS and set SeaBIOS' boot order to run your payload. + its internal VGA comes up just fine (using Change ID I9e0df1669d73863c95c36a3a7fee40d58f6f097e), with unpatched SeaBIOS and these settings: + CONFIG_VGA_ROM_RUN=y + CONFIG_PCI_ROM_RUN=y + CONFIG_ON_DEVICE_ROM_RUN=y + Hotswapping the PDIP BIOS chip has some issues (most likely USB3 XHCI, disable it in original bios before hot-flashing to coreboot). Drop a mail to mailing list if you have issues. + +TODOs + + test virtualization + test IOMMU + test HDMI: video over hdmi works with the extracted vga optionrom, audio is untested. + blink in suspend mode (GP43, program LDN7 F8=23 and blink with F9=2 for 1s blinks) + fix mptable + fix resume with USB3.0 used (perhaps there is a bug in resume.c) + fix immediate resume after suspend (perhaps PCIe STS needs to be cleared) + +UEFI builds that allow flash chip access + + v5016 is untested, but expected to work as well + v5018 + v5103 + v5104 + v5107 + v5202 + v6002 + v6004 + v6102 + v6402 + v6404 (requires downgrading to v6402 to flash coreboot) + v6501 (requires downgrading to v6402 to flash coreboot) + v6502 (requires downgrading to v6402 to flash coreboot) + +Build v6502, v6501 and v6404 do not allow access to the flash chip. + +Fortunately it is possible to downgrade build v6502, v6501 and v6404 to v6402, with EZFlash. + +Downgrading is done by downloading build v6402 from ASUS' F2A85-M download page and copying it to (the root directory of) a FAT32 formatted USB flash drive. + +Enter the EFI setup, switch to advanced mode if necessary, open the 'Tool' tab and select "ASUS EZ Flash 2 Utility". +Hardware info + +This board ships with a socketed Winbond 25Q64F, 64 Mbit (8 Mbyte) chip, in PDIP 300 mil package: +Winbond 25Q64F + +The chip manual is available here + +For out of band flashing, I use a + + 3M test clip model 923739-08-ND + +It has .300" spacing, 8 pin DIP clip, gold finish and 'headless heads'. I hook this up to a bus pirate. This works but reading and writing take forever: + +\# time /usr/src/flashrom/flashrom -p buspirate_spi:dev=/dev/ttyUSB0 -w 20130826-coreboot.rom +flashrom v0.9.6.1-r1669 on Linux 3.8-2-amd64 (x86_64) +flashrom is free software, get the source code at http://www.flashrom.org + +Calibrating delay loop... OK. +Found Winbond flash chip "W25Q64" (8192 kB, SPI) on buspirate_spi. +Reading old flash chip contents... done. +Erasing and writing flash chip... Erase/write done. +Verifying flash... VERIFIED. + +real 35m35.409s +user 0m55.976s +sys 0m12.920s + +DDR voltage controller + +The DDR voltage controller is accessible through the AUX SMBUS device 0x15 and it is most likely driven by programmable current source NCT3933U (datasheet on nuvoton website). +The ASUS digi VRM + +The ASUS digi voltage controller is accessible through the SMBUS device 0x20 and it is most likely driven by CHL8318 or similar chip (re-branded) +Memory + +If you use single dimm plug it to DIMM_A2 or DIMM_B2. + +I use: + +2x 2GB DDR3 modules in blue slots: + +\#modprobe i2c-piix4 +\#modprobe eeprom +\#decode-dimms + +---=== Memory Characteristics ===--- +Fine time base 2.500 ps +Medium time base 0.125 ns +Maximum module speed 1333MHz (PC3-10666) +Size 2048 MB +Banks x Rows x Columns x Bits 8 x 14 x 10 x 64 +Ranks 2 +SDRAM Device Width 8 bits +tCL-tRCD-tRP-tRAS 8-8-8-24 +Supported CAS Latencies (tCL) 9T, 8T, 7T, 6T + +See also +F2A85 series status + +Only boards with internal wiki page links are Supported Motherboards. + + ASUS F2A85-M + ASUS F2A85-M LE + ASUS F2A85-M PRO[3] - the most available model in the entire F2A85 series. Be sure to check its status to see what works and what doesn't. + ASUS F2A85-M2 - Confirmed working in the #coreboot IRC channel 2015-03-04. Unsure if WIP. + ASUS F2A85-M/CSM - Unsure if WIP. + +References + + Jump up ↑ https://www.asus.com/Motherboards/F2A85M/specifications/ + Jump up ↑ http://support.asus.com/Cpusupport/List.aspx?SLanguage=en&m=F2A85-M&p=1&s=43 + Jump up ↑ http://www.asus.com/Motherboards/F2A85M_PRO/ -- To view, visit https://review.coreboot.org/c/coreboot/+/30895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d195f4833ba71fdc559815cafb0f5d0d254e897 Gerrit-Change-Number: 30895 Gerrit-PatchSet: 1 Gerrit-Owner: Balázs Vinarz <vinibali1(a)gmail.com> Gerrit-MessageType: newchange

5 29

Change in ...coreboot[master]: [TEST_ONLY, DO_NOT_MERGE] mb/google/octopus: Create phasal variant
by Raymond Chung (Code Review) 15 Mar '19

15 Mar '19

Raymond Chung has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31023 Change subject: [TEST_ONLY, DO_NOT_MERGE] mb/google/octopus: Create phasal variant ...................................................................... [TEST_ONLY, DO_NOT_MERGE] mb/google/octopus: Create phasal variant This creates a phasal variant for octopus. Nothing is set in the variant files here; everything is picked up from baseboard. BUG=b:None TEST=None Change-Id: Id2c26195d44a268df2aff64b224c4376f0e9059e Signed-off-by: “raymondchung” <“raymondchung(a)ami.corp-partner.google.xn--com-9o0a> --- M src/mainboard/google/octopus/Kconfig M src/mainboard/google/octopus/Kconfig.name A src/mainboard/google/octopus/variants/phasal/Makefile.inc A src/mainboard/google/octopus/variants/phasal/gpio.c A src/mainboard/google/octopus/variants/phasal/include/variant/acpi/dptf.asl A src/mainboard/google/octopus/variants/phasal/include/variant/ec.h A src/mainboard/google/octopus/variants/phasal/include/variant/gpio.h A src/mainboard/google/octopus/variants/phasal/overridetree.cb A src/mainboard/google/octopus/variants/phasal/variant.c 9 files changed, 358 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/31023/1 diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index a237741..a62cd19 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -56,6 +56,7 @@ default "meep" if BOARD_GOOGLE_MEEP default "ampton" if BOARD_GOOGLE_AMPTON default "casta" if BOARD_GOOGLE_CASTA + default "phasal" if BOARD_GOOGLE_PHASAL default "octopus" if BOARD_GOOGLE_OCTOPUS config DEVICETREE @@ -76,6 +77,7 @@ default "Meep" if BOARD_GOOGLE_MEEP default "Ampton" if BOARD_GOOGLE_AMPTON default "Casta" if BOARD_GOOGLE_CASTA + default "Phasal" if BOARD_GOOGLE_PHASAL default "Octopus" if BOARD_GOOGLE_OCTOPUS config MAINBOARD_FAMILY @@ -93,6 +95,7 @@ default "MEEP TEST 1118" if BOARD_GOOGLE_MEEP default "AMPTON TEST 1285" if BOARD_GOOGLE_AMPTON default "CASTA TEST 8105" if BOARD_GOOGLE_CASTA + default "PHASAL TEST 7167" if BOARD_GOOGLE_PHASAL default "OCTOPUS TEST 6859" if BOARD_GOOGLE_OCTOPUS config MAX_CPUS diff --git a/src/mainboard/google/octopus/Kconfig.name b/src/mainboard/google/octopus/Kconfig.name index 498da36..71e5197 100644 --- a/src/mainboard/google/octopus/Kconfig.name +++ b/src/mainboard/google/octopus/Kconfig.name @@ -52,3 +52,9 @@ select BASEBOARD_OCTOPUS_LAPTOP select BOARD_GOOGLE_BASEBOARD_OCTOPUS select NHLT_DA7219 if INCLUDE_NHLT_BLOBS + +config BOARD_GOOGLE_PHASAL + bool "-> Phasal" + select BASEBOARD_OCTOPUS_LAPTOP + select BOARD_GOOGLE_BASEBOARD_OCTOPUS + select NHLT_DA7219 if INCLUDE_NHLT_BLOBS diff --git a/src/mainboard/google/octopus/variants/phasal/Makefile.inc b/src/mainboard/google/octopus/variants/phasal/Makefile.inc new file mode 100644 index 0000000..d54ed40 --- /dev/null +++ b/src/mainboard/google/octopus/variants/phasal/Makefile.inc @@ -0,0 +1,4 @@ +bootblock-y += gpio.c + +ramstage-y += variant.c +ramstage-y += gpio.c diff --git a/src/mainboard/google/octopus/variants/phasal/gpio.c b/src/mainboard/google/octopus/variants/phasal/gpio.c new file mode 100644 index 0000000..322b44b --- /dev/null +++ b/src/mainboard/google/octopus/variants/phasal/gpio.c @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <boardid.h> +#include <gpio.h> +#include <soc/gpio.h> +#include <ec/google/chromeec/ec.h> +#include <console/console.h> + +#define SKU_UNKNOWN 0xFFFFFFFF + +static const struct pad_config default_override_table[] = { + PAD_NC(GPIO_52, UP_20K), + PAD_NC(GPIO_53, UP_20K), + PAD_NC(GPIO_67, UP_20K), + PAD_NC(GPIO_117, UP_20K), + PAD_NC(GPIO_143, UP_20K), + + /* EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, + DISPUPD), + + PAD_NC(GPIO_161, DN_20K), + + /* EN_PP3300_WLAN_L */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_178, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), + + PAD_NC(GPIO_213, DN_20K), + PAD_NC(GPIO_214, DN_20K), +}; + +static const struct pad_config sku1_default_override_table[] = { + /* disable I2C7 SCL and SDA */ + PAD_NC(GPIO_114, UP_20K), /* LPSS_I2C7_SDA */ + PAD_NC(GPIO_115, UP_20K), /* LPSS_I2C7_SCL */ + + PAD_NC(GPIO_52, UP_20K), + PAD_NC(GPIO_53, UP_20K), + PAD_NC(GPIO_67, UP_20K), + PAD_NC(GPIO_117, UP_20K), + PAD_NC(GPIO_143, UP_20K), + + /* EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, + DISPUPD), + + PAD_NC(GPIO_161, DN_20K), + + /* EN_PP3300_WLAN_L */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_178, 0, DEEP, NONE, Tx0RxDCRx0, + DISPUPD), + + PAD_NC(GPIO_213, DN_20K), + PAD_NC(GPIO_214, DN_20K), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + const struct pad_config *c; + uint32_t sku_id = SKU_UNKNOWN; + + google_chromeec_cbi_get_sku_id(&sku_id); + if (sku_id == 1) { + c = sku1_default_override_table; + *num = ARRAY_SIZE(sku1_default_override_table); + } else { + c = default_override_table; + *num = ARRAY_SIZE(default_override_table); + } + + return c; +} diff --git a/src/mainboard/google/octopus/variants/phasal/include/variant/acpi/dptf.asl b/src/mainboard/google/octopus/variants/phasal/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..cc17d56 --- /dev/null +++ b/src/mainboard/google/octopus/variants/phasal/include/variant/acpi/dptf.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/octopus/variants/phasal/include/variant/ec.h b/src/mainboard/google/octopus/variants/phasal/include/variant/ec.h new file mode 100644 index 0000000..16f931b --- /dev/null +++ b/src/mainboard/google/octopus/variants/phasal/include/variant/ec.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/octopus/variants/phasal/include/variant/gpio.h b/src/mainboard/google/octopus/variants/phasal/include/variant/gpio.h new file mode 100644 index 0000000..1fd1e11 --- /dev/null +++ b/src/mainboard/google/octopus/variants/phasal/include/variant/gpio.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <baseboard/gpio.h> + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/octopus/variants/phasal/overridetree.cb b/src/mainboard/google/octopus/variants/phasal/overridetree.cb new file mode 100644 index 0000000..b131173 --- /dev/null +++ b/src/mainboard/google/octopus/variants/phasal/overridetree.cb @@ -0,0 +1,164 @@ +chip soc/intel/apollolake + + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-16.32. + # [14:8] steps of delay for DDR mode, each 125ps. + # [6:0] steps of delay for SDR mode, each 125ps. + register "emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-16.33. + # [14:8] steps of delay for HS400, each 125ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps. + register "emmc_tx_data_cntl1" = "0x0b0c" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-16.34. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_tx_data_cntl2" = "0x1c282929" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-16.35. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_rx_cmd_data_cntl1" = "0x00181b1b" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-16.37. + # [17:16] stands for Rx Clock before Output Buffer + # [14:8] steps of delay for Auto Tuning Mode, each 125ps. + # [6:0] steps of delay for HS200, each 125ps. + register "emmc_rx_cmd_data_cntl2" = "0x10028" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-16.36. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps. + register "emmc_rx_strobe_cntl" = "0x0b0b" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Digitizer | + #| I2C5 | Audio | + #| I2C6 | Trackpad | + #| I2C7 | Touchscreen | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 66, + .fall_time_ns = 90, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 104, + .fall_time_ns = 52, + }, + .i2c[6] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 66, + .fall_time_ns = 90, + .data_hold_time_ns = 350, + }, + .i2c[7] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 76, + .fall_time_ns = 164, + }, + }" + + device domain 0 on + device pci 16.0 on + chip drivers/i2c/hid + register "generic.hid" = ""WCOM50C1"" + register "generic.desc" = ""WCOM Digitizer"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_139_IRQ)" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "generic.reset_delay_ms" = "20" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x1" + device i2c 0x9 on end + end + end # - I2C 0 + device pci 17.1 on + chip drivers/i2c/da7219 + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + device i2c 1a on end + end + end # - I2C 5 + device pci 17.2 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)" + register "wake" = "GPE0_DW3_27" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)" + register "generic.wake" = "GPE0_DW3_27" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x2c on end + end + end # - I2C 6 + device pci 17.3 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 10 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""SYTS7817"" + register "generic.desc" = ""Synaptics Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "generic.reset_delay_ms" = "45" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 20 on end + end + end # - I2C 7 + end +end diff --git a/src/mainboard/google/octopus/variants/phasal/variant.c b/src/mainboard/google/octopus/variants/phasal/variant.c new file mode 100644 index 0000000..22f4f71 --- /dev/null +++ b/src/mainboard/google/octopus/variants/phasal/variant.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <soc/pci_devs.h> +#include <string.h> +#include <ec/google/chromeec/ec.h> + +#define SKU_UNKNOWN 0xFFFFFFFF + +void variant_update_devtree(struct device *dev) +{ + uint32_t sku_id = SKU_UNKNOWN; + struct device *touchscreen_i2c_host; + + touchscreen_i2c_host = pcidev_path_on_root(PCH_DEVFN_I2C7); + + if (touchscreen_i2c_host == NULL) + return; + + /* SKU ID 1 does not have a touchscreen device, hence disable it. */ + google_chromeec_cbi_get_sku_id(&sku_id); + if (sku_id == 1) + touchscreen_i2c_host->enabled = 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/31023 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id2c26195d44a268df2aff64b224c4376f0e9059e Gerrit-Change-Number: 31023 Gerrit-PatchSet: 1 Gerrit-Owner: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/autoport: Add missing IDs
by Angel Pons (Code Review) 13 Mar '19

13 Mar '19

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30962 Change subject: util/autoport: Add missing IDs ...................................................................... util/autoport: Add missing IDs Add four IDs found in PCIe root ports on the CPU. Change-Id: I04b5220c460f1930accd64b63c11f512581f2c6c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/autoport/bd82x6x.go 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/30962/1 diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go index 29b1c21..2f24655 100644 --- a/util/autoport/bd82x6x.go +++ b/util/autoport/bd82x6x.go @@ -430,6 +430,7 @@ /* PCIe bridge */ for _, id := range []uint16{ + 0x0101, 0x0105, 0x0109, 0x010d, 0x0151, 0x0155, 0x1c10, 0x1c12, 0x1c14, 0x1c16, 0x1c18, 0x1c1a, 0x1c1c, 0x1c1e, 0x1e10, 0x1e12, -- To view, visit https://review.coreboot.org/c/coreboot/+/30962 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04b5220c460f1930accd64b63c11f512581f2c6c Gerrit-Change-Number: 30962 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

4 9

Change in ...coreboot[master]: lib/hardwaremain: Remove unused acpi_is_wakeup() function
by Subrata Banik (Code Review) 13 Mar '19

13 Mar '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31140 Change subject: lib/hardwaremain: Remove unused acpi_is_wakeup() function ...................................................................... lib/hardwaremain: Remove unused acpi_is_wakeup() function Looks like acpi_is_wakeup() return value is not getting honoured, hence this function is not doing anything rather reading from romstage buffer. Change-Id: Icc57804074a58315e72e276fcae799febc10612d Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/lib/hardwaremain.c 1 file changed, 1 insertion(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/31140/1 diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 98b8841..3ec7e8e 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google, Inc. + * Copyright (C) 2019 Intel Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -469,11 +470,6 @@ timestamp_add_now(TS_START_RAMSTAGE); post_code(POST_ENTRY_RAMSTAGE); - /* Handoff sleep type from romstage. */ -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) - acpi_is_wakeup(); -#endif - exception_init(); threads_initialize(); -- To view, visit https://review.coreboot.org/c/coreboot/+/31140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc57804074a58315e72e276fcae799febc10612d Gerrit-Change-Number: 31140 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

3 17

Change in ...coreboot[master]: mb/mainboard/amd/serengeti_cheetah_fam10: Use PCI_DEVFN()
by HAOUAS Elyes (Code Review) 13 Mar '19

13 Mar '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30787 Change subject: mb/mainboard/amd/serengeti_cheetah_fam10: Use PCI_DEVFN() ...................................................................... mb/mainboard/amd/serengeti_cheetah_fam10: Use PCI_DEVFN() Change-Id: Ica2ea269152c30ded7c865adc2454bccc4f986ec Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/30787/1 diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c b/src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c index 4ce5285..8fc7153 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c @@ -101,7 +101,7 @@ u32 busn = (sysconf.pci1234[i] >> 12) & 0xff; u32 devn = sysconf.hcdn[i] & 0xff; - write_pirq_info(pirq_info, busn, (devn << 3) | 0, 0x1, 0xdef8, + write_pirq_info(pirq_info, busn, PCI_DEVFN(devn, 0), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; @@ -110,12 +110,12 @@ } #if CONFIG_CBB - write_pirq_info(pirq_info, CONFIG_CBB, (0 << 3) | 0, 0x1, 0xdef8, 0x2, + write_pirq_info(pirq_info, CONFIG_CBB, PCI_DEVFN(0, 0), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; if (sysconf.nodes > 32) { - write_pirq_info(pirq_info, CONFIG_CBB - 1, (0 << 3) | 0, 0x1, + write_pirq_info(pirq_info, CONFIG_CBB - 1, PCI_DEVFN(0, 0), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; -- To view, visit https://review.coreboot.org/c/coreboot/+/30787 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica2ea269152c30ded7c865adc2454bccc4f986ec Gerrit-Change-Number: 30787 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [WIP] nb/intel/sandybridge: Reserve CAR region with !NATIVE_RAMINIT
by Kyösti Mälkki (Code Review) 06 Mar '19

06 Mar '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31150 Change subject: [WIP] nb/intel/sandybridge: Reserve CAR region with !NATIVE_RAMINIT ...................................................................... [WIP] nb/intel/sandybridge: Reserve CAR region with !NATIVE_RAMINIT Fail builds if MRC blobs pool heap would get corrupted by CAR relocatable data from coreboot proper. Patch the blob instead: https://review.coreboot.org/c/blobs/+/31149 Change-Id: Ibc771b592b35d77be81fce87769314fe6bb84c87 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/car.ld 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/31150/1 diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 7b10f43..fe55071 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -89,6 +89,13 @@ _car_global_end = .; _car_relocatable_data_end = .; +#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) && !IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT) + . = ABSOLUTE(0xff7e1000); + _mrc_var_heap_start = .; + . += 0x3000; + _mrc_var_heap_end = .; +#endif + #if !IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) _car_stack_start = .; _car_stack_end = _car_region_end; -- To view, visit https://review.coreboot.org/c/coreboot/+/31150 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc771b592b35d77be81fce87769314fe6bb84c87 Gerrit-Change-Number: 31150 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit January 2019