Shaleen Jain has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30604
Change subject: util/inteltool: fix PCR init of Sunrise Point-LP devices
......................................................................
util/inteltool: fix PCR init of Sunrise Point-LP devices
Fixes getting a dump of GPIO registers for these devices.
Change-Id: I80f05a170152969ba45d6aee33ab7ed5296ee496
Signed-off-by: Shaleen Jain <shaleen(a)jain.sh>
---
M util/inteltool/pcr.c
1 file changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/30604/1
diff --git a/util/inteltool/pcr.c b/util/inteltool/pcr.c
index 4e75905..555411a 100644
--- a/util/inteltool/pcr.c
+++ b/util/inteltool/pcr.c
@@ -77,6 +77,13 @@
switch (sb->device_id) {
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_PRE:
+ case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SATA:
+ case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE:
+ case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM:
+ case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM:
+ case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE:
+ case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM:
+ case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM:
case PCI_DEVICE_ID_INTEL_H110:
case PCI_DEVICE_ID_INTEL_H170:
case PCI_DEVICE_ID_INTEL_Z170:
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I80f05a170152969ba45d6aee33ab7ed5296ee496
Gerrit-Change-Number: 30604
Gerrit-PatchSet: 1
Gerrit-Owner: Shaleen Jain <shaleen.jain95(a)gmail.com>
Gerrit-MessageType: newchange
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30561
Change subject: soc/intel/cannonlake: Add support to enable/disable USB charging in s3/S5
......................................................................
soc/intel/cannonlake: Add support to enable/disable USB charging in s3/S5
BUG=b:120914069
BRANCH=none
TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot.
Change-Id: I555bb8d763bbc0b693536e34e0a5bf9375e3259a
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
M src/soc/intel/cannonlake/acpi/globalnvs.asl
1 file changed, 27 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/30561/1
diff --git a/src/soc/intel/cannonlake/acpi/globalnvs.asl b/src/soc/intel/cannonlake/acpi/globalnvs.asl
index ac60b36..1bd3038 100644
--- a/src/soc/intel/cannonlake/acpi/globalnvs.asl
+++ b/src/soc/intel/cannonlake/acpi/globalnvs.asl
@@ -3,7 +3,7 @@
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
+ * Copyright (C) 2015-2019 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -50,8 +50,34 @@
U2WE, 16, // 0x2b - 0x2c USB2 Wake Enable Bitmap
U3WE, 16, // 0x2d - 0x2e USB3 Wake Enable Bitmap
UIOR, 8, // 0x2f - UART debug controller init on S3 resume
+ S5U0, 8, // 0x30 - Enable USB in S5
+ S3U0, 8, // 0x31 - Enable USB in S3
/* ChromeOS specific */
Offset (0x100),
#include <vendorcode/google/chromeos/acpi/gnvs.asl>
}
+
+/* Set flag to enable USB charging in S3 */
+Method (S3UE)
+{
+ Store (One, \S3U0)
+}
+
+/* Set flag to disable USB charging in S3 */
+Method (S3UD)
+{
+ Store (Zero, \S3U0)
+}
+
+/* Set flag to enable USB charging in S5 */
+Method (S5UE)
+{
+ Store (One, \S5U0)
+}
+
+/* Set flag to disable USB charging in S5 */
+Method (S5UD)
+{
+ Store (Zero, \S5U0)
+}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I555bb8d763bbc0b693536e34e0a5bf9375e3259a
Gerrit-Change-Number: 30561
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-MessageType: newchange