coreboot-gerrit January 2019

coreboot-gerrit@coreboot.org

1 participants
1296 discussions

Change in ...coreboot[master]: crossgcc: Update GCC to 8.2.0 (test no nds32)
by HAOUAS Elyes (Code Review) 05 Jan '19

05 Jan '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30676 Change subject: crossgcc: Update GCC to 8.2.0 (test no nds32) ...................................................................... crossgcc: Update GCC to 8.2.0 (test no nds32) Change-Id: Ifdf165e7a34bb76eb8ce806091268fd28797ffb7 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/patches/gcc-8.1.0_armv6s-m.patch D util/crossgcc/patches/gcc-8.1.0_bsd.patch D util/crossgcc/patches/gcc-8.1.0_gnat.patch D util/crossgcc/patches/gcc-8.1.0_nds32_ite.patch R util/crossgcc/patches/gcc-8.2.0_ada-musl_workaround.patch A util/crossgcc/patches/gcc-8.2.0_gnat.patch R util/crossgcc/patches/gcc-8.2.0_libgcc.patch 8 files changed, 21 insertions(+), 21,262 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/30676/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/30676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifdf165e7a34bb76eb8ce806091268fd28797ffb7 Gerrit-Change-Number: 30676 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: sb/intel/fsp_rangeley: Fix typo in GPIO Level
by HAOUAS Elyes (Code Review) 05 Jan '19

05 Jan '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30675 Change subject: sb/intel/fsp_rangeley: Fix typo in GPIO Level ...................................................................... sb/intel/fsp_rangeley: Fix typo in GPIO Level Change-Id: I83886820b8c1acceb2007b694361fe8c30c34f7f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/fsp_rangeley/acpi/soc.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/30675/1 diff --git a/src/southbridge/intel/fsp_rangeley/acpi/soc.asl b/src/southbridge/intel/fsp_rangeley/acpi/soc.asl index b55bd92..dde6796 100644 --- a/src/southbridge/intel/fsp_rangeley/acpi/soc.asl +++ b/src/southbridge/intel/fsp_rangeley/acpi/soc.asl @@ -93,7 +93,7 @@ GIO2, 8, GIO3, 8, Offset(0x0c), // GPIO Level - GL00, 1, + GP00, 1, GP01, 1, GP02, 1, GP0e, 1, -- To view, visit https://review.coreboot.org/c/coreboot/+/30675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I83886820b8c1acceb2007b694361fe8c30c34f7f Gerrit-Change-Number: 30675 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: mb/google/fizz: enable eist (enhanced speedstep)
by Matt DeVillier (Code Review) 05 Jan '19

05 Jan '19

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30674 Change subject: mb/google/fizz: enable eist (enhanced speedstep) ...................................................................... mb/google/fizz: enable eist (enhanced speedstep) Without eist enabled, fizz's CPU clocks are locked at the base frequency, and don't scale up or down. This prevents fizz from idling properly and turbo boost from functioning, so enable it (as is done for all other KBL boards) Test: build/boot google/fizz, ensure CPU clocks scale as expected Change-Id: I77dd0e1df1bf88f5bae18e9f832ca8d60fb777b4 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/fizz/variants/baseboard/devicetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/30674/1 diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index cc48498..c7c35c0 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -7,6 +7,8 @@ register "deep_s5_enable_dc" = "1" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN" + register "eist_enable" = "1" + # Mapping of USB port # to device #+----------------+-------+-----------------------------------+ #| Device | Port# | Rev | -- To view, visit https://review.coreboot.org/c/coreboot/+/30674 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77dd0e1df1bf88f5bae18e9f832ca8d60fb777b4 Gerrit-Change-Number: 30674 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: util/ifdtool: Fix regions_collide() check
by Nico Huber (Code Review) 05 Jan '19

05 Jan '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30673 Change subject: util/ifdtool: Fix regions_collide() check ...................................................................... util/ifdtool: Fix regions_collide() check The old version was unnecessarily complex and allowed one region to include the other. Change-Id: Ibf7faf8103c8945b82c3962b5a7b82c3288b871f Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M util/ifdtool/ifdtool.c 1 file changed, 2 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/30673/1 diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index ccd27d0..69cd2a9 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -1153,11 +1153,8 @@ if ((r1->size == 0) || (r2->size == 0)) return 0; - if ( ((r1->base >= r2->base) && (r1->base <= r2->limit)) || - ((r1->limit >= r2->base) && (r1->limit <= r2->limit)) ) - return 1; - - return 0; + /* r1 should be either completely below or completely above r2 */ + return !(r1->limit < r2->base || r1->base > r2->limit); } void new_layout(const char *filename, char *image, int size, -- To view, visit https://review.coreboot.org/c/coreboot/+/30673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf7faf8103c8945b82c3962b5a7b82c3288b871f Gerrit-Change-Number: 30673 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: superio/*: Link early initialization into bootblock
by Arthur Heymans (Code Review) 04 Jan '19

04 Jan '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30672 Change subject: superio/*: Link early initialization into bootblock ...................................................................... superio/*: Link early initialization into bootblock This allows to set up the SuperIO in the C_ENVIRONMENT_BOOTBLOCK bootblocks. I ran the following command in the superio source directory: for file in $(find -name Makefile.inc -exec grep -L bootblock {} \;) do sed -i 's/$romstage$$.*$/bootblock\2\n&/' $file done Change-Id: I3d999611baa1e79c79fe6b1f01822ebaa5f85daf Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/superio/fintek/Makefile.inc M src/superio/fintek/f81216h/Makefile.inc M src/superio/intel/i8900/Makefile.inc M src/superio/ite/Makefile.inc M src/superio/ite/it8671f/Makefile.inc M src/superio/ite/it8718f/Makefile.inc M src/superio/ite/it8772f/Makefile.inc M src/superio/nsc/pc87309/Makefile.inc M src/superio/nsc/pc87360/Makefile.inc M src/superio/nsc/pc87366/Makefile.inc M src/superio/nsc/pc87417/Makefile.inc M src/superio/nsc/pc97317/Makefile.inc M src/superio/nuvoton/nct5104d/Makefile.inc M src/superio/nuvoton/wpcm450/Makefile.inc M src/superio/serverengines/pilot/Makefile.inc M src/superio/smsc/dme1737/Makefile.inc M src/superio/smsc/kbc1100/Makefile.inc M src/superio/smsc/lpc47b272/Makefile.inc M src/superio/smsc/lpc47b397/Makefile.inc M src/superio/smsc/lpc47m10x/Makefile.inc M src/superio/smsc/lpc47m15x/Makefile.inc M src/superio/smsc/lpc47n207/Makefile.inc M src/superio/smsc/lpc47n217/Makefile.inc M src/superio/smsc/lpc47n227/Makefile.inc M src/superio/smsc/sch4037/Makefile.inc M src/superio/smsc/sio1007/Makefile.inc M src/superio/smsc/sio1036/Makefile.inc M src/superio/smsc/smscsuperio/Makefile.inc M src/superio/winbond/Makefile.inc M src/superio/winbond/w83627dhg/Makefile.inc M src/superio/winbond/wpcd376i/Makefile.inc 31 files changed, 32 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/30672/1 diff --git a/src/superio/fintek/Makefile.inc b/src/superio/fintek/Makefile.inc index 2222644..c346324 100644 --- a/src/superio/fintek/Makefile.inc +++ b/src/superio/fintek/Makefile.inc @@ -14,6 +14,7 @@ ## ## include generic fintek pre-ram stage driver +bootblock-$(CONFIG_SUPERIO_FINTEK_COMMON_ROMSTAGE) += common/early_serial.c romstage-$(CONFIG_SUPERIO_FINTEK_COMMON_ROMSTAGE) += common/early_serial.c subdirs-y += f71805f diff --git a/src/superio/fintek/f81216h/Makefile.inc b/src/superio/fintek/f81216h/Makefile.inc index 51e5123..7dbf20e 100644 --- a/src/superio/fintek/f81216h/Makefile.inc +++ b/src/superio/fintek/f81216h/Makefile.inc @@ -14,5 +14,6 @@ ## GNU General Public License for more details. ## +bootblock-$(CONFIG_SUPERIO_FINTEK_F81216H) += early_serial.c romstage-$(CONFIG_SUPERIO_FINTEK_F81216H) += early_serial.c ramstage-$(CONFIG_SUPERIO_FINTEK_F81216H) += superio.c diff --git a/src/superio/intel/i8900/Makefile.inc b/src/superio/intel/i8900/Makefile.inc index fd1db21..562d5d1 100644 --- a/src/superio/intel/i8900/Makefile.inc +++ b/src/superio/intel/i8900/Makefile.inc @@ -14,5 +14,6 @@ ## GNU General Public License for more details. ## +bootblock-$(CONFIG_SUPERIO_INTEL_I8900) += early_serial.c romstage-$(CONFIG_SUPERIO_INTEL_I8900) += early_serial.c ramstage-$(CONFIG_SUPERIO_INTEL_I8900) += superio.c diff --git a/src/superio/ite/Makefile.inc b/src/superio/ite/Makefile.inc index 382dbd7..e2127c2 100644 --- a/src/superio/ite/Makefile.inc +++ b/src/superio/ite/Makefile.inc @@ -14,6 +14,7 @@ ## ## include generic ite pre-ram stage driver +bootblock-$(CONFIG_SUPERIO_ITE_COMMON_ROMSTAGE) += common/early_serial.c romstage-$(CONFIG_SUPERIO_ITE_COMMON_ROMSTAGE) += common/early_serial.c ## include generic ite environment controller driver diff --git a/src/superio/ite/it8671f/Makefile.inc b/src/superio/ite/it8671f/Makefile.inc index 339f962..f625bc1 100644 --- a/src/superio/ite/it8671f/Makefile.inc +++ b/src/superio/ite/it8671f/Makefile.inc @@ -14,5 +14,6 @@ ## GNU General Public License for more details. ## +bootblock-$(CONFIG_SUPERIO_ITE_IT8671F) += early_serial.c romstage-$(CONFIG_SUPERIO_ITE_IT8671F) += early_serial.c ramstage-$(CONFIG_SUPERIO_ITE_IT8671F) += superio.c diff --git a/src/superio/ite/it8718f/Makefile.inc b/src/superio/ite/it8718f/Makefile.inc index 7627d1c..89382ca 100644 --- a/src/superio/ite/it8718f/Makefile.inc +++ b/src/superio/ite/it8718f/Makefile.inc @@ -14,5 +14,6 @@ ## GNU General Public License for more details. ## +bootblock-$(CONFIG_SUPERIO_ITE_IT8718F) += early_serial.c romstage-$(CONFIG_SUPERIO_ITE_IT8718F) += early_serial.c ramstage-$(CONFIG_SUPERIO_ITE_IT8718F) += superio.c diff --git a/src/superio/ite/it8772f/Makefile.inc b/src/superio/ite/it8772f/Makefile.inc index a0bf94d..6c06c36 100644 --- a/src/superio/ite/it8772f/Makefile.inc +++ b/src/superio/ite/it8772f/Makefile.inc @@ -14,6 +14,7 @@ ## GNU General Public License for more details. ## +bootblock-$(CONFIG_SUPERIO_ITE_IT8772F) += early_init.c romstage-$(CONFIG_SUPERIO_ITE_IT8772F) += early_init.c ramstage-$(CONFIG_SUPERIO_ITE_IT8772F) += superio.c smm-$(CONFIG_SUPERIO_ITE_IT8772F) += early_init.c diff --git a/src/superio/nsc/pc87309/Makefile.inc b/src/superio/nsc/pc87309/Makefile.inc index e04c4f8..0f0b367 100644 --- a/src/superio/nsc/pc87309/Makefile.inc +++ b/src/superio/nsc/pc87309/Makefile.inc @@ -14,5 +14,6 @@ ## GNU General Public License for more details. ## +bootblock-$(CONFIG_SUPERIO_NSC_PC87309) += early_serial.c romstage-$(CONFIG_SUPERIO_NSC_PC87309) += early_serial.c ramstage-$(CONFIG_SUPERIO_NSC_PC87309) += superio.c diff --git a/src/superio/nsc/pc87360/Makefile.inc b/src/superio/nsc/pc87360/Makefile.inc index 5c3ed24..e0ee98a 100644 --- a/src/superio/nsc/pc87360/Makefile.inc +++ b/src/superio/nsc/pc87360/Makefile.inc @@ -15,5 +15,6 @@ ## GNU General Public License for more details. ## +bootblock-$(CONFIG_SUPERIO_NSC_PC87360) += early_serial.c romstage-$(CONFIG_SUPERIO_NSC_PC87360) += early_serial.c ramstage-$(CONFIG_SUPERIO_NSC_PC87360) += superio.c diff --git a/src/superio/nsc/pc87366/Makefile.inc b/src/superio/nsc/pc87366/Makefile.inc index a7b5536..6e558ac 100644 --- a/src/superio/nsc/pc87366/Makefile.inc +++ b/src/superio/nsc/pc87366/Makefile.inc @@ -15,5 +15,6 @@ ## GNU General Public License for more details. ## +bootblock-$(CONFIG_SUPERIO_NSC_PC87366) += early_serial.c romstage-$(CONFIG_SUPERIO_NSC_PC87366) += early_serial.c ramstage-$(CONFIG_SUPERIO_NSC_PC87366) += superio.c diff --git a/src/superio/nsc/pc87417/Makefile.inc b/src/superio/nsc/pc87417/Makefile.inc index a4a0ed5..4294561 100644 --- a/src/superio/nsc/pc87417/Makefile.inc +++ b/src/superio/nsc/pc87417/Makefile.inc @@ -16,6 +16,8 @@ ## GNU General Public License for more details. ## +bootblock-$(CONFIG_SUPERIO_NSC_PC87417) += early_init.c romstage-$(CONFIG_SUPERIO_NSC_PC87417) += early_init.c +bootblock-$(CONFIG_SUPERIO_NSC_PC87417) += early_serial.c romstage-$(CONFIG_SUPERIO_NSC_PC87417) += early_serial.c ramstage-$(CONFIG_SUPERIO_NSC_PC87417) += superio.c diff --git a/src/superio/nsc/pc97317/Makefile.inc b/src/superio/nsc/pc97317/Makefile.inc index f5f1300..2f8ee76 100644 --- a/src/superio/nsc/pc97317/Makefile.inc +++ b/src/superio/nsc/pc97317/Makefile.inc @@ -14,5 +14,6 @@ ## GNU General Public License for more details. ## +bootblock-$(CONFIG_SUPERIO_NSC_PC97317) += early_serial.c romstage-$(CONFIG_SUPERIO_NSC_PC97317) += early_serial.c ramstage-$(CONFIG_SUPERIO_NSC_PC97317) += superio.c diff --git a/src/superio/nuvoton/nct5104d/Makefile.inc b/src/superio/nuvoton/nct5104d/Makefile.inc index 5067a93..1c67660 100644 --- a/src/superio/nuvoton/nct5104d/Makefile.inc +++ b/src/superio/nuvoton/nct5104d/Makefile.inc @@ -15,4 +15,5 @@ ## ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT5104D) += superio.c +bootblock-$(CONFIG_SUPERIO_NUVOTON_NCT5104D) += early_init.c romstage-$(CONFIG_SUPERIO_NUVOTON_NCT5104D) += early_init.c diff --git a/src/superio/nuvoton/wpcm450/Makefile.inc b/src/superio/nuvoton/wpcm450/Makefile.inc index e5aa66b..27dc253 100644 --- a/src/superio/nuvoton/wpcm450/Makefile.inc +++ b/src/superio/nuvoton/wpcm450/Makefile.inc @@ -14,5 +14,6 @@ ## GNU General Public License for more details. ## +bootblock-$(CONFIG_SUPERIO_NUVOTON_WPCM450) += early_init.c romstage-$(CONFIG_SUPERIO_NUVOTON_WPCM450) += early_init.c ramstage-$(CONFIG_SUPERIO_NUVOTON_WPCM450) += superio.c diff --git a/src/superio/serverengines/pilot/Makefile.inc b/src/superio/serverengines/pilot/Makefile.inc index e342b5f..26ff103 100644 --- a/src/superio/serverengines/pilot/Makefile.inc +++ b/src/superio/serverengines/pilot/Makefile.inc @@ -14,5 +14,5 @@ ## GNU General Public License for more details. ## +bootblock-$(CONFIG_SUPERIO_SERVERENGINES_PILOT) += early_init.c romstage-$(CONFIG_SUPERIO_SERVERENGINES_PILOT) += early_init.c -romstage-$(CONFIG_SUPERIO_SERVERENGINES_PILOT) += early_serial.c diff --git a/src/superio/smsc/dme1737/Makefile.inc b/src/superio/smsc/dme1737/Makefile.inc index 17f10b1..e106a02 100644 --- a/src/superio/smsc/dme1737/Makefile.inc +++ b/src/superio/smsc/dme1737/Makefile.inc @@ -16,5 +16,6 @@ ## GNU General Public License for more details. ## +bootblock-$(CONFIG_SUPERIO_SMSC_DME1737) += early_serial.c romstage-$(CONFIG_SUPERIO_SMSC_DME1737) += early_serial.c ramstage-$(CONFIG_SUPERIO_SMSC_DME1737) += superio.c diff --git a/src/superio/smsc/kbc1100/Makefile.inc b/src/superio/smsc/kbc1100/Makefile.inc index 3a22a2e..5da9494 100644 --- a/src/superio/smsc/kbc1100/Makefile.inc +++ b/src/superio/smsc/kbc1100/Makefile.inc @@ -13,5 +13,6 @@ # GNU General Public License for more details. # +bootblock-$(CONFIG_SUPERIO_SMSC_KBC1100) += early_init.c romstage-$(CONFIG_SUPERIO_SMSC_KBC1100) += early_init.c ramstage-$(CONFIG_SUPERIO_SMSC_KBC1100) += superio.c diff --git a/src/superio/smsc/lpc47b272/Makefile.inc b/src/superio/smsc/lpc47b272/Makefile.inc index 904a70a..51d77d4 100644 --- a/src/superio/smsc/lpc47b272/Makefile.inc +++ b/src/superio/smsc/lpc47b272/Makefile.inc @@ -14,5 +14,6 @@ ## GNU General Public License for more details. ## +bootblock-$(CONFIG_SUPERIO_SMSC_LPC47B272) += early_serial.c romstage-$(CONFIG_SUPERIO_SMSC_LPC47B272) += early_serial.c ramstage-$(CONFIG_SUPERIO_SMSC_LPC47B272) += superio.c diff --git a/src/superio/smsc/lpc47b397/Makefile.inc b/src/superio/smsc/lpc47b397/Makefile.inc index 8609ee0..ddb251d 100644 --- a/src/superio/smsc/lpc47b397/Makefile.inc +++ b/src/superio/smsc/lpc47b397/Makefile.inc @@ -16,5 +16,6 @@ ## GNU General Public License for more details. ## +bootblock-$(CONFIG_SUPERIO_SMSC_LPC47B397) += early_serial.c romstage-$(CONFIG_SUPERIO_SMSC_LPC47B397) += early_serial.c ramstage-$(CONFIG_SUPERIO_SMSC_LPC47B397) += superio.c diff --git a/src/superio/smsc/lpc47m10x/Makefile.inc b/src/superio/smsc/lpc47m10x/Makefile.inc index 0dd272c..278aa1e 100644 --- a/src/superio/smsc/lpc47m10x/Makefile.inc +++ b/src/superio/smsc/lpc47m10x/Makefile.inc @@ -18,5 +18,6 @@ ## GNU General Public License for more details. ## +bootblock-$(CONFIG_SUPERIO_SMSC_LPC47M10X) += early_serial.c romstage-$(CONFIG_SUPERIO_SMSC_LPC47M10X) += early_serial.c ramstage-$(CONFIG_SUPERIO_SMSC_LPC47M10X) += superio.c diff --git a/src/superio/smsc/lpc47m15x/Makefile.inc b/src/superio/smsc/lpc47m15x/Makefile.inc index f465669..dc6b9ab 100644 --- a/src/superio/smsc/lpc47m15x/Makefile.inc +++ b/src/superio/smsc/lpc47m15x/Makefile.inc @@ -13,5 +13,6 @@ ## GNU General Public License for more details. ## +bootblock-$(CONFIG_SUPERIO_SMSC_LPC47M15X) += early_serial.c romstage-$(CONFIG_SUPERIO_SMSC_LPC47M15X) += early_serial.c ramstage-$(CONFIG_SUPERIO_SMSC_LPC47M15X) += superio.c diff --git a/src/superio/smsc/lpc47n207/Makefile.inc b/src/superio/smsc/lpc47n207/Makefile.inc index 599e19a..65a0939 100644 --- a/src/superio/smsc/lpc47n207/Makefile.inc +++ b/src/superio/smsc/lpc47n207/Makefile.inc @@ -14,4 +14,5 @@ ## GNU General Public License for more details. ## +bootblock-$(CONFIG_SUPERIO_SMSC_LPC47N207) += early_serial.c romstage-$(CONFIG_SUPERIO_SMSC_LPC47N207) += early_serial.c diff --git a/src/superio/smsc/lpc47n217/Makefile.inc b/src/superio/smsc/lpc47n217/Makefile.inc index 0bff637..a643407 100644 --- a/src/superio/smsc/lpc47n217/Makefile.inc +++ b/src/superio/smsc/lpc47n217/Makefile.inc @@ -14,5 +14,6 @@ ## GNU General Public License for more details. ## +bootblock-$(CONFIG_SUPERIO_SMSC_LPC47N217) += early_serial.c romstage-$(CONFIG_SUPERIO_SMSC_LPC47N217) += early_serial.c ramstage-$(CONFIG_SUPERIO_SMSC_LPC47N217) += superio.c diff --git a/src/superio/smsc/lpc47n227/Makefile.inc b/src/superio/smsc/lpc47n227/Makefile.inc index 71abe9e..4bb0dac 100644 --- a/src/superio/smsc/lpc47n227/Makefile.inc +++ b/src/superio/smsc/lpc47n227/Makefile.inc @@ -13,5 +13,6 @@ ## GNU General Public License for more details. ## +bootblock-$(CONFIG_SUPERIO_SMSC_LPC47N227) += early_serial.c romstage-$(CONFIG_SUPERIO_SMSC_LPC47N227) += early_serial.c ramstage-$(CONFIG_SUPERIO_SMSC_LPC47N227) += superio.c diff --git a/src/superio/smsc/sch4037/Makefile.inc b/src/superio/smsc/sch4037/Makefile.inc index 6b3bf19..ac7d7de 100644 --- a/src/superio/smsc/sch4037/Makefile.inc +++ b/src/superio/smsc/sch4037/Makefile.inc @@ -13,5 +13,6 @@ # GNU General Public License for more details. # +bootblock-$(CONFIG_SUPERIO_SMSC_SCH4037) += sch4037_early_init.c romstage-$(CONFIG_SUPERIO_SMSC_SCH4037) += sch4037_early_init.c ramstage-$(CONFIG_SUPERIO_SMSC_SCH4037) += superio.c diff --git a/src/superio/smsc/sio1007/Makefile.inc b/src/superio/smsc/sio1007/Makefile.inc index bc458bf..20a0b2a 100644 --- a/src/superio/smsc/sio1007/Makefile.inc +++ b/src/superio/smsc/sio1007/Makefile.inc @@ -13,4 +13,5 @@ ## GNU General Public License for more details. ## +bootblock-$(CONFIG_SUPERIO_SMSC_SIO1007) += early_serial.c romstage-$(CONFIG_SUPERIO_SMSC_SIO1007) += early_serial.c diff --git a/src/superio/smsc/sio1036/Makefile.inc b/src/superio/smsc/sio1036/Makefile.inc index 7d09b69..e9fdae2 100644 --- a/src/superio/smsc/sio1036/Makefile.inc +++ b/src/superio/smsc/sio1036/Makefile.inc @@ -13,5 +13,6 @@ # GNU General Public License for more details. # +bootblock-$(CONFIG_SUPERIO_SMSC_SIO1036) += sio1036_early_init.c romstage-$(CONFIG_SUPERIO_SMSC_SIO1036) += sio1036_early_init.c ramstage-$(CONFIG_SUPERIO_SMSC_SIO1036) += superio.c diff --git a/src/superio/smsc/smscsuperio/Makefile.inc b/src/superio/smsc/smscsuperio/Makefile.inc index aae5f22..b9bf35c 100644 --- a/src/superio/smsc/smscsuperio/Makefile.inc +++ b/src/superio/smsc/smscsuperio/Makefile.inc @@ -14,5 +14,6 @@ ## GNU General Public License for more details. ## +bootblock-$(CONFIG_SUPERIO_SMSC_SMSCSUPERIO) += early_serial.c romstage-$(CONFIG_SUPERIO_SMSC_SMSCSUPERIO) += early_serial.c ramstage-$(CONFIG_SUPERIO_SMSC_SMSCSUPERIO) += superio.c diff --git a/src/superio/winbond/Makefile.inc b/src/superio/winbond/Makefile.inc index b0b7b8c..a98c366 100644 --- a/src/superio/winbond/Makefile.inc +++ b/src/superio/winbond/Makefile.inc @@ -14,6 +14,7 @@ ## ## include generic winbond pre-ram stage driver +bootblock-$(CONFIG_SUPERIO_WINBOND_COMMON_ROMSTAGE) += common/early_init.c romstage-$(CONFIG_SUPERIO_WINBOND_COMMON_ROMSTAGE) += common/early_init.c subdirs-y += w83627dhg diff --git a/src/superio/winbond/w83627dhg/Makefile.inc b/src/superio/winbond/w83627dhg/Makefile.inc index 7d9dc97..4075a41 100644 --- a/src/superio/winbond/w83627dhg/Makefile.inc +++ b/src/superio/winbond/w83627dhg/Makefile.inc @@ -15,5 +15,6 @@ ## GNU General Public License for more details. ## +bootblock-$(CONFIG_SUPERIO_WINBOND_W83627DHG) += early_serial.c romstage-$(CONFIG_SUPERIO_WINBOND_W83627DHG) += early_serial.c ramstage-$(CONFIG_SUPERIO_WINBOND_W83627DHG) += superio.c diff --git a/src/superio/winbond/wpcd376i/Makefile.inc b/src/superio/winbond/wpcd376i/Makefile.inc index 402aa32..cebd175 100644 --- a/src/superio/winbond/wpcd376i/Makefile.inc +++ b/src/superio/winbond/wpcd376i/Makefile.inc @@ -15,5 +15,6 @@ ## GNU General Public License for more details. ## +bootblock-$(CONFIG_SUPERIO_WINBOND_WPCD376I) += early_serial.c romstage-$(CONFIG_SUPERIO_WINBOND_WPCD376I) += early_serial.c ramstage-$(CONFIG_SUPERIO_WINBOND_WPCD376I) += superio.c -- To view, visit https://review.coreboot.org/c/coreboot/+/30672 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d999611baa1e79c79fe6b1f01822ebaa5f85daf Gerrit-Change-Number: 30672 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: cpu/intel: Use the common code to initialize the romstage timestamps
by Arthur Heymans (Code Review) 04 Jan '19

04 Jan '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30670 Change subject: cpu/intel: Use the common code to initialize the romstage timestamps ...................................................................... cpu/intel: Use the common code to initialize the romstage timestamps In the bootblock timestamps are pushed to mm1 and mm2 registers which the romstage can now use to set up the initial timestamp. Change-Id: I88e972caafff5c53d8e68e85415f920c7341b92d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/car/romstage.c M src/cpu/intel/haswell/romstage.c M src/mainboard/apple/macbook21/romstage.c M src/mainboard/asrock/g41c-gs/romstage.c M src/mainboard/asus/p5gc-mx/romstage.c M src/mainboard/asus/p5qc/romstage.c M src/mainboard/asus/p5qpl-am/romstage.c M src/mainboard/foxconn/d41s/romstage.c M src/mainboard/foxconn/g41s-k/romstage.c M src/mainboard/getac/p470/romstage.c M src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c M src/mainboard/gigabyte/ga-g41m-es2l/romstage.c M src/mainboard/ibase/mb899/romstage.c M src/mainboard/intel/d510mo/romstage.c M src/mainboard/intel/d945gclf/romstage.c M src/mainboard/intel/dg41wv/romstage.c M src/mainboard/intel/dg43gt/romstage.c M src/mainboard/kontron/986lcd-m/romstage.c M src/mainboard/lenovo/t400/romstage.c M src/mainboard/lenovo/t60/romstage.c M src/mainboard/lenovo/thinkcentre_a58/romstage.c M src/mainboard/lenovo/x200/romstage.c M src/mainboard/lenovo/x60/romstage.c M src/mainboard/lenovo/z61t/romstage.c M src/mainboard/roda/rk886ex/romstage.c M src/mainboard/roda/rk9/romstage.c M src/northbridge/intel/sandybridge/romstage.c M src/southbridge/intel/bd82x6x/bootblock.c M src/southbridge/intel/bd82x6x/early_pch_common.c M src/southbridge/intel/i82801gx/bootblock.c M src/southbridge/intel/i82801gx/early_lpc.c M src/southbridge/intel/i82801ix/bootblock.c M src/southbridge/intel/i82801ix/early_init.c M src/southbridge/intel/i82801jx/bootblock.c M src/southbridge/intel/i82801jx/early_lpc.c M src/southbridge/intel/lynxpoint/bootblock.c M src/southbridge/intel/lynxpoint/early_pch.c 37 files changed, 3 insertions(+), 214 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/30670/1 diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index 5eba043..9d3144d 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -17,6 +17,7 @@ #include <cpu/x86/mtrr.h> #include <arch/symbols.h> #include <program_loading.h> +#include <timestamp.h> #define DCACHE_RAM_ROMSTAGE_STACK_SIZE 0x2000 @@ -59,6 +60,8 @@ */ asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) { + timestamp_init(base_timestamp); + timestamp_add_now(TS_START_ROMSTAGE); romstage_main(bist); } #endif diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index a25f883..c6020e1 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -77,9 +77,6 @@ int boot_mode; int wake_from_s3; - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - if (params->bist == 0) enable_lapic(); diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index a538e0f..de60fbb 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -237,9 +237,6 @@ int s3resume = 0; const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x51, 0x52, 0x53 }; - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - if (bist == 0) enable_lapic(); diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c index e0246a8..0151919 100644 --- a/src/mainboard/asrock/g41c-gs/romstage.c +++ b/src/mainboard/asrock/g41c-gs/romstage.c @@ -90,9 +90,6 @@ u8 boot_path = 0; u8 s3_resume; - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - /* Set southbridge and Super I/O GPIOs. */ ich7_enable_lpc(); mb_lpc_setup(); diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c index 6f41b4c..31de960 100644 --- a/src/mainboard/asus/p5gc-mx/romstage.c +++ b/src/mainboard/asus/p5gc-mx/romstage.c @@ -188,9 +188,6 @@ u8 c_bsel = msr_get_fsb(); - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - if (bist == 0) enable_lapic(); diff --git a/src/mainboard/asus/p5qc/romstage.c b/src/mainboard/asus/p5qc/romstage.c index eb534ca..527f31b 100644 --- a/src/mainboard/asus/p5qc/romstage.c +++ b/src/mainboard/asus/p5qc/romstage.c @@ -73,9 +73,6 @@ u8 boot_path = 0; u8 s3_resume; - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - /* Set southbridge and Super I/O GPIOs. */ ich10_enable_lpc(); mb_gpio_init(); diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c index bc04261..09629d5 100644 --- a/src/mainboard/asus/p5qpl-am/romstage.c +++ b/src/mainboard/asus/p5qpl-am/romstage.c @@ -148,9 +148,6 @@ u8 boot_path = 0; u8 s3_resume; - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - /* Set southbridge and Super I/O GPIOs. */ ich7_enable_lpc(); mb_lpc_setup(); diff --git a/src/mainboard/foxconn/d41s/romstage.c b/src/mainboard/foxconn/d41s/romstage.c index 2d64bef..da23d55 100644 --- a/src/mainboard/foxconn/d41s/romstage.c +++ b/src/mainboard/foxconn/d41s/romstage.c @@ -88,9 +88,6 @@ int s3resume = 0; int boot_path; - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - if (bist == 0) enable_lapic(); diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/romstage.c index 5ea41ea..cf5337f 100644 --- a/src/mainboard/foxconn/g41s-k/romstage.c +++ b/src/mainboard/foxconn/g41s-k/romstage.c @@ -88,9 +88,6 @@ u8 boot_path = 0; u8 s3_resume; - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - /* Set up southbridge and Super I/O GPIOs. */ ich7_enable_lpc(); mb_lpc_setup(); diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index 18d856b..664a683 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -171,7 +171,6 @@ /* Enable PCIe Root Port Clock Gate */ // RCBA32(0x341c) = 0x00000001; - /* This should probably go into the ACPI enable trap */ /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ RCBA32(0x1e84) = 0x00020001; @@ -240,9 +239,6 @@ { int s3resume = 0; - timestamp_init(timestamp_get()); - timestamp_add_now(TS_START_ROMSTAGE); - if (bist == 0) enable_lapic(); diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c index 6c1da82..34d056e 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c @@ -149,10 +149,6 @@ { int s3resume = 0, boot_mode = 0; - - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - if (bist == 0) enable_lapic(); diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index 4613c14..0121f18 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -134,9 +134,6 @@ u8 boot_path = 0; u8 s3_resume; - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - /* Set southbridge and Super I/O GPIOs. */ ich7_enable_lpc(); mb_gpio_init(); diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 24bd8a2..09a28a4 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -204,9 +204,6 @@ { int s3resume = 0; - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - if (bist == 0) enable_lapic(); diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c index 459fb19..f613d40 100644 --- a/src/mainboard/intel/d510mo/romstage.c +++ b/src/mainboard/intel/d510mo/romstage.c @@ -37,7 +37,6 @@ #define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1) #define SUPERIO_DEV PNP_DEV(0x4e, 0) - /* Early mainboard specific GPIO setup */ static void mb_gpio_init(void) { @@ -95,9 +94,6 @@ int s3resume = 0; int boot_path; - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - if (bist == 0) enable_lapic(); diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index 6f0e419..2e629ca 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -129,10 +129,6 @@ { int s3resume = 0, boot_mode = 0; - - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - if (bist == 0) enable_lapic(); diff --git a/src/mainboard/intel/dg41wv/romstage.c b/src/mainboard/intel/dg41wv/romstage.c index 6e9d034..a6a65b6 100644 --- a/src/mainboard/intel/dg41wv/romstage.c +++ b/src/mainboard/intel/dg41wv/romstage.c @@ -84,9 +84,6 @@ u8 boot_path = 0; u8 s3_resume; - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - /* Set southbridge and Super I/O GPIOs. */ ich7_enable_lpc(); mb_lpc_setup(); diff --git a/src/mainboard/intel/dg43gt/romstage.c b/src/mainboard/intel/dg43gt/romstage.c index 36aa149..aa8c50e 100644 --- a/src/mainboard/intel/dg43gt/romstage.c +++ b/src/mainboard/intel/dg43gt/romstage.c @@ -75,9 +75,6 @@ u8 boot_path = 0; u8 s3_resume; - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - /* Set southbridge and Super I/O GPIOs. */ ich10_enable_lpc(); mb_gpio_init(); diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 144872d..2b5af3d 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -294,10 +294,6 @@ { int s3resume = 0; - - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - if (bist == 0) enable_lapic(); diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index 6d93112..1a392fa 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -68,9 +68,6 @@ int err; u16 reg16; - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - /* basic northbridge setup, including MMCONF BAR */ gm45_early_init(); diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index 3b806f9..7807bb6 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -170,10 +170,6 @@ int dock_err; const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0, 0x51, 0 }; - - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - if (bist == 0) enable_lapic(); diff --git a/src/mainboard/lenovo/thinkcentre_a58/romstage.c b/src/mainboard/lenovo/thinkcentre_a58/romstage.c index 149a45d..f264e35 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/romstage.c +++ b/src/mainboard/lenovo/thinkcentre_a58/romstage.c @@ -70,9 +70,6 @@ u8 boot_path = 0; u8 s3_resume; - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - /* Set southbridge and Super I/O GPIOs. */ ich7_enable_lpc(); mb_lpc_setup(); diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c index 8176fad..0669568 100644 --- a/src/mainboard/lenovo/x200/romstage.c +++ b/src/mainboard/lenovo/x200/romstage.c @@ -34,7 +34,6 @@ #define LPC_DEV PCI_DEV(0, 0x1f, 0) #define MCH_DEV PCI_DEV(0, 0, 0) - static void early_lpc_setup(void) { /* Set up SuperIO LPC forwards */ @@ -56,9 +55,6 @@ int cbmem_initted; u16 reg16; - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - /* basic northbridge setup, including MMCONF BAR */ gm45_early_init(); diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index d6674fe..a30601f 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -168,10 +168,6 @@ int s3resume = 0; const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0, 0x51, 0 }; - - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - if (bist == 0) enable_lapic(); diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c index 20dbaba..130dcda 100644 --- a/src/mainboard/lenovo/z61t/romstage.c +++ b/src/mainboard/lenovo/z61t/romstage.c @@ -170,10 +170,6 @@ int dock_err; const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0, 0x51, 0 }; - - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - if (bist == 0) enable_lapic(); diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index 6e9cc83..ea8bf2d 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -213,10 +213,6 @@ { int s3resume = 0; - - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - if (bist == 0) enable_lapic(); diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c index 1bcfd62..3080130 100644 --- a/src/mainboard/roda/rk9/romstage.c +++ b/src/mainboard/roda/rk9/romstage.c @@ -107,7 +107,6 @@ /* Exit configuration state. */ pnp_exit_conf_state(sio); - /* Enable decoding of 0x600-0x60f through lpc. */ pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0x000c0601); @@ -123,9 +122,6 @@ int cbmem_initted; u16 reg16; - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - /* basic northbridge setup, including MMCONF BAR */ gm45_early_init(); diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 7345443..26f4977 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -53,9 +53,6 @@ halt (); } - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - if (bist == 0) enable_lapic(); diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c index 8541903..673f0c7 100644 --- a/src/southbridge/intel/bd82x6x/bootblock.c +++ b/src/southbridge/intel/bd82x6x/bootblock.c @@ -14,20 +14,8 @@ */ #include <arch/io.h> -#include <cpu/x86/tsc.h> #include "pch.h" -static void store_initial_timestamp(void) -{ - /* On Cougar Point we have two 32bit scratchpad registers available: - * D0:F0 0xdc (SKPAD) - * D31:F2 0xd0 (SATA SP) - */ - tsc_t tsc = rdtsc(); - pci_write_config32(PCI_DEV(0, 0x00, 0), 0xdc, tsc.lo); - pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.hi); -} - /* * Enable Prefetching and Caching. */ @@ -80,8 +68,6 @@ static void bootblock_southbridge_init(void) { - store_initial_timestamp(); - enable_spi_prefetch(); enable_port80_on_lpc(); set_spi_speed(); diff --git a/src/southbridge/intel/bd82x6x/early_pch_common.c b/src/southbridge/intel/bd82x6x/early_pch_common.c index 3e151fc..a9ec9b1 100644 --- a/src/southbridge/intel/bd82x6x/early_pch_common.c +++ b/src/southbridge/intel/bd82x6x/early_pch_common.c @@ -15,8 +15,6 @@ */ #include <arch/io.h> -#include <timestamp.h> -#include <cpu/x86/tsc.h> #include <device/pci_def.h> #include <device/pci_ops.h> #include "pch.h" @@ -25,15 +23,6 @@ #include <rules.h> #if ENV_ROMSTAGE -uint64_t get_initial_timestamp(void) -{ - tsc_t base_time = { - .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), - .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) - }; - return tsc_to_uint64(base_time); -} - int southbridge_detect_s3_resume(void) { u32 pm1_cnt; diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c index c9c19a3..6d65df3 100644 --- a/src/southbridge/intel/i82801gx/bootblock.c +++ b/src/southbridge/intel/i82801gx/bootblock.c @@ -14,20 +14,8 @@ */ #include <arch/io.h> -#include <cpu/x86/tsc.h> #include "i82801gx.h" -static void store_initial_timestamp(void) -{ - /* On i945/ICH7 we have two 32bit scratchpad registers available: - * D0:F0 0xdc (SKPAD) - * D31:F2 0xd0 (SATA SP) - */ - tsc_t tsc = rdtsc(); - pci_write_config32(PCI_DEV(0, 0x00, 0), 0xdc, tsc.lo); - pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.hi); -} - static void enable_spi_prefetch(void) { u8 reg8; @@ -43,8 +31,6 @@ static void bootblock_southbridge_init(void) { - store_initial_timestamp(); - enable_spi_prefetch(); /* Enable RCBA */ diff --git a/src/southbridge/intel/i82801gx/early_lpc.c b/src/southbridge/intel/i82801gx/early_lpc.c index 11da3ec..a52fb85 100644 --- a/src/southbridge/intel/i82801gx/early_lpc.c +++ b/src/southbridge/intel/i82801gx/early_lpc.c @@ -15,21 +15,10 @@ */ #include <arch/io.h> -#include <timestamp.h> -#include <cpu/x86/tsc.h> #include <console/console.h> #include <arch/acpi.h> #include "i82801gx.h" -uint64_t get_initial_timestamp(void) -{ - tsc_t base_time = { - .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), - .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) - }; - return tsc_to_uint64(base_time); -} - int southbridge_detect_s3_resume(void) { u32 reg32; diff --git a/src/southbridge/intel/i82801ix/bootblock.c b/src/southbridge/intel/i82801ix/bootblock.c index bb025b0..6252712 100644 --- a/src/southbridge/intel/i82801ix/bootblock.c +++ b/src/southbridge/intel/i82801ix/bootblock.c @@ -14,19 +14,6 @@ */ #include <arch/io.h> -#include <cpu/x86/tsc.h> - -static void store_initial_timestamp(void) -{ - /* - * We have two 32bit scratchpad registers available: - * D0:F0 0xdc (SKPAD) - * D31:F2 0xd0 (SATA SP) - */ - tsc_t tsc = rdtsc(); - pci_write_config32(PCI_DEV(0, 0x00, 0), 0xdc, tsc.lo); - pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.hi); -} static void enable_spi_prefetch(void) { @@ -43,6 +30,5 @@ static void bootblock_southbridge_init(void) { - store_initial_timestamp(); enable_spi_prefetch(); } diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c index 7c4dafa..c40f9b7 100644 --- a/src/southbridge/intel/i82801ix/early_init.c +++ b/src/southbridge/intel/i82801ix/early_init.c @@ -15,19 +15,8 @@ */ #include <arch/io.h> -#include <timestamp.h> -#include <cpu/x86/tsc.h> #include "i82801ix.h" -uint64_t get_initial_timestamp(void) -{ - tsc_t base_time = { - .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), - .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) - }; - return tsc_to_uint64(base_time); -} - void i82801ix_early_init(void) { const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); diff --git a/src/southbridge/intel/i82801jx/bootblock.c b/src/southbridge/intel/i82801jx/bootblock.c index 115555c..cc685c4 100644 --- a/src/southbridge/intel/i82801jx/bootblock.c +++ b/src/southbridge/intel/i82801jx/bootblock.c @@ -14,21 +14,8 @@ */ #include <arch/io.h> -#include <cpu/x86/tsc.h> #include "i82801jx.h" -static void store_initial_timestamp(void) -{ - /* - * We have two 32bit scratchpad registers available: - * D0:F0 0xdc (SKPAD) - * D31:F2 0xd0 (SATA SP) - */ - tsc_t tsc = rdtsc(); - pci_write_config32(PCI_DEV(0, 0x00, 0), 0xdc, tsc.lo); - pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.hi); -} - static void enable_spi_prefetch(void) { u8 reg8; @@ -44,7 +31,6 @@ static void bootblock_southbridge_init(void) { - store_initial_timestamp(); enable_spi_prefetch(); /* Enable RCBA */ diff --git a/src/southbridge/intel/i82801jx/early_lpc.c b/src/southbridge/intel/i82801jx/early_lpc.c index 74f0ee2..a59fdcc 100644 --- a/src/southbridge/intel/i82801jx/early_lpc.c +++ b/src/southbridge/intel/i82801jx/early_lpc.c @@ -15,21 +15,10 @@ */ #include <arch/io.h> -#include <timestamp.h> -#include <cpu/x86/tsc.h> #include <console/console.h> #include <arch/acpi.h> #include "i82801jx.h" -uint64_t get_initial_timestamp(void) -{ - tsc_t base_time = { - .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), - .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) - }; - return tsc_to_uint64(base_time); -} - int southbridge_detect_s3_resume(void) { u32 reg32; diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index 20d0ee3..f87ebe3 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c @@ -14,20 +14,8 @@ */ #include <arch/io.h> -#include <cpu/x86/tsc.h> #include "pch.h" -static void store_initial_timestamp(void) -{ - /* On Cougar Point we have two 32bit scratchpad registers available: - * D0:F0 0xdc (SKPAD) - * D31:F2 0xd0 (SATA SP) - */ - tsc_t tsc = rdtsc(); - pci_write_config32(PCI_DEV(0, 0x00, 0), 0xdc, tsc.lo); - pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.hi); -} - /* * Enable Prefetching and Caching. */ @@ -83,8 +71,6 @@ static void bootblock_southbridge_init(void) { - store_initial_timestamp(); - map_rcba(); enable_spi_prefetch(); enable_port80_on_lpc(); diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 27a3b29..aae761c 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -18,8 +18,6 @@ #include <arch/io.h> #include <device/device.h> #include <device/pci_def.h> -#include <timestamp.h> -#include <cpu/x86/tsc.h> #include <elog.h> #include "pch.h" #include "chip.h" @@ -68,15 +66,6 @@ printk(BIOS_DEBUG, " done.\n"); } -uint64_t get_initial_timestamp(void) -{ - tsc_t base_time = { - .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), - .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) - }; - return tsc_to_uint64(base_time); -} - static int sleep_type_s3(void) { u32 pm1_cnt; -- To view, visit https://review.coreboot.org/c/coreboot/+/30670 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88e972caafff5c53d8e68e85415f920c7341b92d Gerrit-Change-Number: 30670 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: Documentation/releases: Note the disappearance of device_t
by Patrick Georgi (Code Review) 04 Jan '19

04 Jan '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30669 Change subject: Documentation/releases: Note the disappearance of device_t ...................................................................... Documentation/releases: Note the disappearance of device_t That was truly a huge task. Change-Id: Ifd79aaf005bf39744bd4fd930ba2441f966ec0b3 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M Documentation/releases/coreboot-4.10-relnotes.md 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/30669/1 diff --git a/Documentation/releases/coreboot-4.10-relnotes.md b/Documentation/releases/coreboot-4.10-relnotes.md index 95adc56..9a6d63c 100644 --- a/Documentation/releases/coreboot-4.10-relnotes.md +++ b/Documentation/releases/coreboot-4.10-relnotes.md @@ -11,4 +11,14 @@ * The chip and board additions and removals will be updated right before the release, so those do not need to be added. +Significant changes +------------------- +### `device_t` is no more +coreboot used to have a data type, `device_t` that changed shape depending on +whether it is compiled for romstage (with limited memory) or ramstage (with +unlimited memory as far as coreboot is concerned). It's an old relic from the +time when romstage wasn't operated in Cache-As-RAM mode, but compiled with +our romcc compiler. + +That data type is now gone. -- To view, visit https://review.coreboot.org/c/coreboot/+/30669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd79aaf005bf39744bd4fd930ba2441f966ec0b3 Gerrit-Change-Number: 30669 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: crossgcc: Update CMake to version 3.13.2
by HAOUAS Elyes (Code Review) 04 Jan '19

04 Jan '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30668 Change subject: crossgcc: Update CMake to version 3.13.2 ...................................................................... crossgcc: Update CMake to version 3.13.2 Change-Id: Ifd9e82d564e4e49194ac48786fd233cbf97a55c5 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/sum/cmake-3.11.3.tar.gz.cksum A util/crossgcc/sum/cmake-3.13.2.tar.gz.cksum 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/30668/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 3a6baa9..b748c37 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -60,7 +60,7 @@ # CLANG version number CLANG_VERSION=7.0.1 MAKE_VERSION=4.2.1 -CMAKE_VERSION=3.11.3 +CMAKE_VERSION=3.13.2 # GCC toolchain archive locations # These are sanitized by the jenkins toolchain test builder, so if @@ -81,7 +81,7 @@ CRT_ARCHIVE="https://releases.llvm.org/${CLANG_VERSION}/compiler-rt-${CLANG_VERSION}.src…" CTE_ARCHIVE="https://releases.llvm.org/${CLANG_VERSION}/clang-tools-extra-${CLANG_VERSIO…" MAKE_ARCHIVE="https://ftpmirror.gnu.org/make/make-${MAKE_VERSION}.tar.bz2" -CMAKE_ARCHIVE="https://cmake.org/files/v3.11/cmake-${CMAKE_VERSION}.tar.gz" +CMAKE_ARCHIVE="https://cmake.org/files/v3.13/cmake-${CMAKE_VERSION}.tar.gz" ALL_ARCHIVES="$GMP_ARCHIVE $MPFR_ARCHIVE $MPC_ARCHIVE \ $GCC_ARCHIVE $BINUTILS_ARCHIVE $GDB_ARCHIVE $IASL_ARCHIVE \ diff --git a/util/crossgcc/sum/cmake-3.11.3.tar.gz.cksum b/util/crossgcc/sum/cmake-3.11.3.tar.gz.cksum deleted file mode 100644 index 14a4b22..0000000 --- a/util/crossgcc/sum/cmake-3.11.3.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -73261a5b7f71abf7277c1d2a418ca3c4cf170c89 tarballs/cmake-3.11.3.tar.gz diff --git a/util/crossgcc/sum/cmake-3.13.2.tar.gz.cksum b/util/crossgcc/sum/cmake-3.13.2.tar.gz.cksum new file mode 100644 index 0000000..5523b70 --- /dev/null +++ b/util/crossgcc/sum/cmake-3.13.2.tar.gz.cksum @@ -0,0 +1 @@ +101b8599b5ddd4df9127e227c3fe13ed3d8e266a tarballs/cmake-3.13.2.tar.gz -- To view, visit https://review.coreboot.org/c/coreboot/+/30668 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd9e82d564e4e49194ac48786fd233cbf97a55c5 Gerrit-Change-Number: 30668 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: crossgcc: Update GDB to version 8.2.1
by HAOUAS Elyes (Code Review) 04 Jan '19

04 Jan '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30667 Change subject: crossgcc: Update GDB to version 8.2.1 ...................................................................... crossgcc: Update GDB to version 8.2.1 Change-Id: I454843dcabe7e3fa4b13dd58ce81ba9f25b5a432 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/sum/gdb-8.0.tar.xz.cksum A util/crossgcc/sum/gdb-8.2.1.tar.xz.cksum 3 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/30667/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index a55fcf5..3a6baa9 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -53,7 +53,7 @@ GCC_VERSION=8.1.0 GCC_AUTOCONF_VERSION=2.69 BINUTILS_VERSION=2.31.1 -GDB_VERSION=8.0 +GDB_VERSION=8.2.1 IASL_VERSION=20181213 PYTHON_VERSION=3.7.0 EXPAT_VERSION=2.2.6 diff --git a/util/crossgcc/sum/gdb-8.0.tar.xz.cksum b/util/crossgcc/sum/gdb-8.0.tar.xz.cksum deleted file mode 100644 index fb42fe2..0000000 --- a/util/crossgcc/sum/gdb-8.0.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -148c8e783ebf9b281241d0566db59961191ec64d tarballs/gdb-8.0.tar.xz diff --git a/util/crossgcc/sum/gdb-8.2.1.tar.xz.cksum b/util/crossgcc/sum/gdb-8.2.1.tar.xz.cksum new file mode 100644 index 0000000..a976106 --- /dev/null +++ b/util/crossgcc/sum/gdb-8.2.1.tar.xz.cksum @@ -0,0 +1 @@ +023556a6d6effa1ffaadf0007cc4458cbe8dde3d tarballs/gdb-8.2.1.tar.xz -- To view, visit https://review.coreboot.org/c/coreboot/+/30667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I454843dcabe7e3fa4b13dd58ce81ba9f25b5a432 Gerrit-Change-Number: 30667 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: crossgcc: Update LLVM to 7.0.1
by HAOUAS Elyes (Code Review) 04 Jan '19

04 Jan '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30666 Change subject: crossgcc: Update LLVM to 7.0.1 ...................................................................... crossgcc: Update LLVM to 7.0.1 Change-Id: I7d88f0c36a254d8b2e3e76f632f46f0d2a4ad6f8 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/sum/cfe-7.0.0.src.tar.xz.cksum A util/crossgcc/sum/cfe-7.0.1.src.tar.xz.cksum D util/crossgcc/sum/llvm-7.0.0.src.tar.xz.cksum A util/crossgcc/sum/llvm-7.0.1.src.tar.xz.cksum 5 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/30666/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index f95884e..a55fcf5 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -58,7 +58,7 @@ PYTHON_VERSION=3.7.0 EXPAT_VERSION=2.2.6 # CLANG version number -CLANG_VERSION=7.0.0 +CLANG_VERSION=7.0.1 MAKE_VERSION=4.2.1 CMAKE_VERSION=3.11.3 diff --git a/util/crossgcc/sum/cfe-7.0.0.src.tar.xz.cksum b/util/crossgcc/sum/cfe-7.0.0.src.tar.xz.cksum deleted file mode 100644 index 422bb80..0000000 --- a/util/crossgcc/sum/cfe-7.0.0.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -a4eb0b33f6a201e97ac62eb1b519e2476e56c794 tarballs/cfe-7.0.0.src.tar.xz diff --git a/util/crossgcc/sum/cfe-7.0.1.src.tar.xz.cksum b/util/crossgcc/sum/cfe-7.0.1.src.tar.xz.cksum new file mode 100644 index 0000000..13a5251 --- /dev/null +++ b/util/crossgcc/sum/cfe-7.0.1.src.tar.xz.cksum @@ -0,0 +1 @@ +427e12762836d808583fb4149c033d02de0a8db2 tarballs/cfe-7.0.1.src.tar.xz diff --git a/util/crossgcc/sum/llvm-7.0.0.src.tar.xz.cksum b/util/crossgcc/sum/llvm-7.0.0.src.tar.xz.cksum deleted file mode 100644 index ddccf26..0000000 --- a/util/crossgcc/sum/llvm-7.0.0.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -27503a22614626e935a05b609ab4211be72cd78b tarballs/llvm-7.0.0.src.tar.xz diff --git a/util/crossgcc/sum/llvm-7.0.1.src.tar.xz.cksum b/util/crossgcc/sum/llvm-7.0.1.src.tar.xz.cksum new file mode 100644 index 0000000..e0c1f5c --- /dev/null +++ b/util/crossgcc/sum/llvm-7.0.1.src.tar.xz.cksum @@ -0,0 +1 @@ +f97632fcc3186eb0d396492ef8acfc807648580f tarballs/llvm-7.0.1.src.tar.xz -- To view, visit https://review.coreboot.org/c/coreboot/+/30666 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d88f0c36a254d8b2e3e76f632f46f0d2a4ad6f8 Gerrit-Change-Number: 30666 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2019