coreboot-gerrit January 2019

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Change in ...coreboot[master]: crossgcc: Update binutils to 2.31.1
by HAOUAS Elyes (Code Review) 04 Jan '19

04 Jan '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30665 Change subject: crossgcc: Update binutils to 2.31.1 ...................................................................... crossgcc: Update binutils to 2.31.1 Change-Id: I71e5646fe27a2a55eafb9bc4cd00ae3b735e56a3 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/sum/binutils-2.30.tar.xz.cksum A util/crossgcc/sum/binutils-2.31.1.tar.xz.cksum 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/30665/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index a9287e1..f95884e 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -30,7 +30,7 @@ cd "$(dirname "$0")" || exit 1 -CROSSGCC_DATE="January 1st, 2019" +CROSSGCC_DATE="January 4st, 2019" CROSSGCC_VERSION="1.55" CROSSGCC_COMMIT=$( git describe ) @@ -52,7 +52,7 @@ MPC_VERSION=1.1.0 GCC_VERSION=8.1.0 GCC_AUTOCONF_VERSION=2.69 -BINUTILS_VERSION=2.30 +BINUTILS_VERSION=2.31.1 GDB_VERSION=8.0 IASL_VERSION=20181213 PYTHON_VERSION=3.7.0 diff --git a/util/crossgcc/sum/binutils-2.30.tar.xz.cksum b/util/crossgcc/sum/binutils-2.30.tar.xz.cksum deleted file mode 100644 index 3493413..0000000 --- a/util/crossgcc/sum/binutils-2.30.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -574d3b5650413d6ee65195a4f5ecbddc3a38f718 tarballs/binutils-2.30.tar.xz diff --git a/util/crossgcc/sum/binutils-2.31.1.tar.xz.cksum b/util/crossgcc/sum/binutils-2.31.1.tar.xz.cksum new file mode 100644 index 0000000..6a26c8f --- /dev/null +++ b/util/crossgcc/sum/binutils-2.31.1.tar.xz.cksum @@ -0,0 +1 @@ +3b031410897fe224412f3a6a1b052402d2fbcc6a tarballs/binutils-2.31.1.tar.xz -- To view, visit https://review.coreboot.org/c/coreboot/+/30665 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71e5646fe27a2a55eafb9bc4cd00ae3b735e56a3 Gerrit-Change-Number: 30665 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/autoport/readme.md: Correct minor inconsistency
by Angel Pons (Code Review) 04 Jan '19

04 Jan '19

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30655 Change subject: util/autoport/readme.md: Correct minor inconsistency ...................................................................... util/autoport/readme.md: Correct minor inconsistency CB:28851 changed where the SPD map is. Reflect that. Change-Id: Id0bd1778617371bac5921c4eae63d0beb088216c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/autoport/readme.md 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/30655/1 diff --git a/util/autoport/readme.md b/util/autoport/readme.md index 67a2c56..226fcda 100644 --- a/util/autoport/readme.md +++ b/util/autoport/readme.md @@ -80,7 +80,7 @@ most likely correct. In order to initialize the memory coreboot needs to know RAM timings. For socketed RAM it's stored in a small EEPROM chip which can be accessed through SPD. Unfortunately mapping between SPD addresses and RAM slots differs and cannot always be detected automatically. -Resulting SPD map is encoded in function `mainboard_get_spd` in `early_southbridge.c`. +Resulting SPD map is encoded in function `mainboard_get_spd` in `romstage.c`. autoport uses the most common map `0x50, 0x51, 0x52, 0x53` except for lenovos which are known to use `0x50, 0x52, 0x51, 0x53`. To detect the correct memory map the easiest way is with vendor BIOS to boot with just one module in channel 0 slot 0 and then see where does it show -- To view, visit https://review.coreboot.org/c/coreboot/+/30655 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0bd1778617371bac5921c4eae63d0beb088216c Gerrit-Change-Number: 30655 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/mb/apple/macbookair4_2: move early_southbridge.c to romstage.c
by Angel Pons (Code Review) 04 Jan '19

04 Jan '19

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30654 Change subject: src/mb/apple/macbookair4_2: move early_southbridge.c to romstage.c ...................................................................... src/mb/apple/macbookair4_2: move early_southbridge.c to romstage.c This is done for consistency purposes. Also fix a small formatting issue in a function. Change-Id: I5dc170dbca59b7abbc912f9a26f76886b25ad82f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/apple/macbookair4_2/Makefile.inc D src/mainboard/apple/macbookair4_2/early_southbridge.c M src/mainboard/apple/macbookair4_2/romstage.c 3 files changed, 77 insertions(+), 79 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/30654/1 diff --git a/src/mainboard/apple/macbookair4_2/Makefile.inc b/src/mainboard/apple/macbookair4_2/Makefile.inc index 555581c..dd5eea3 100644 --- a/src/mainboard/apple/macbookair4_2/Makefile.inc +++ b/src/mainboard/apple/macbookair4_2/Makefile.inc @@ -1,4 +1,3 @@ -romstage-y += early_southbridge.c romstage-y += gpio.c ramstage-y += gnvs.c diff --git a/src/mainboard/apple/macbookair4_2/early_southbridge.c b/src/mainboard/apple/macbookair4_2/early_southbridge.c deleted file mode 100644 index 3ec6187..0000000 --- a/src/mainboard/apple/macbookair4_2/early_southbridge.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <string.h> -#include <arch/byteorder.h> -#include <arch/io.h> -#include <device/pci_def.h> -#include <device/pnp_def.h> -#include <northbridge/intel/sandybridge/sandybridge.h> -#include <northbridge/intel/sandybridge/raminit_native.h> -#include <southbridge/intel/bd82x6x/pch.h> -#include <cbfs.h> - -void pch_enable_lpc(void) -{ - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0681); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c1641); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x001c0301); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00fc0701); - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0070); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x80000000); -} - -void mainboard_rcba_config(void) -{ - /* Disable devices. */ - RCBA32(0x3414) = 0x00000020; -} -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, -}; - -void mainboard_early_init(int s3resume) { -} - -void mainboard_config_superio(void) -{ -} - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - void *spd_file; - size_t spd_file_len = 0; - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); - if (spd_file && spd_file_len >= 1024) { - int i; - for (i = 0; i < 4; i++) - memcpy(&spd[i], spd_file + 256 * i, 128); - } -} diff --git a/src/mainboard/apple/macbookair4_2/romstage.c b/src/mainboard/apple/macbookair4_2/romstage.c index 78049bb..914ee05 100644 --- a/src/mainboard/apple/macbookair4_2/romstage.c +++ b/src/mainboard/apple/macbookair4_2/romstage.c @@ -1,2 +1,77 @@ -/* No license required */ -/* dummy file */ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <arch/byteorder.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <cbfs.h> + +void pch_enable_lpc(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0681); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c1641); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x001c0301); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00fc0701); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0070); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x80000000); +} + +void mainboard_rcba_config(void) +{ + /* Disable devices. */ + RCBA32(0x3414) = 0x00000020; +} +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + void *spd_file; + size_t spd_file_len = 0; + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_file_len); + if (spd_file && spd_file_len >= 1024) { + int i; + for (i = 0; i < 4; i++) + memcpy(&spd[i], spd_file + 256 * i, 128); + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/30654 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5dc170dbca59b7abbc912f9a26f76886b25ad82f Gerrit-Change-Number: 30654 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/sarien: Correct I2C bus clock for touchpad
by Lijian Zhao (Code Review) 03 Jan '19

03 Jan '19

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30653 Change subject: mb/google/sarien: Correct I2C bus clock for touchpad ...................................................................... mb/google/sarien: Correct I2C bus clock for touchpad Elan touchpad require connected i2c clock to be running at 400Khz, with the modification can get 404Khz speed from Arcada EVT platform. BUG=b:119628524 TEST=Build and boot up on Arcada platform, measure the i2c clock is around 400Khz. Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: If717cdd6b73394125df54d90f729ffb4ef37b087 --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/30653/1 diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 52840de..5fdf8fd 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -65,8 +65,8 @@ }, .i2c[1] = { .speed = I2C_SPEED_FAST, - .rise_time_ns = 216, - .fall_time_ns = 28, + .rise_time_ns = 176, + .fall_time_ns = 15, }, .i2c[4] = { .early_init = 1, -- To view, visit https://review.coreboot.org/c/coreboot/+/30653 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If717cdd6b73394125df54d90f729ffb4ef37b087 Gerrit-Change-Number: 30653 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src: Use "foo **bar" instead of "foo ** bar"
by HAOUAS Elyes (Code Review) 03 Jan '19

03 Jan '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30624 Change subject: src: Use "foo **bar" instead of "foo ** bar" ...................................................................... src: Use "foo **bar" instead of "foo ** bar" Change-Id: I8260424ee243c06827f2b5939e1568e52539b282 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/device/azalia_device.c M src/mainboard/lenovo/x201/mainboard.c M src/southbridge/intel/bd82x6x/azalia.c M src/southbridge/intel/i82801ix/hdaudio.c M src/southbridge/intel/i82801jx/hdaudio.c M src/southbridge/intel/ibexpeak/azalia.c M src/southbridge/intel/lynxpoint/hda_verb.c 7 files changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/30624/1 diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c index 364eec1..6ca80a8 100644 --- a/src/device/azalia_device.c +++ b/src/device/azalia_device.c @@ -105,7 +105,7 @@ return 0; } -static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb) +static u32 find_verb(struct device *dev, u32 viddid, const u32 **verb) { printk(BIOS_DEBUG, "azalia_audio: dev=%s\n", dev_path(dev)); printk(BIOS_DEBUG, "azalia_audio: Reading viddid=%x\n", viddid); diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index 419f817..b707366 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -36,7 +36,7 @@ {2, 17, 250, {0x01, 8, 0, {0}, DEFAULT_PMBASE + LV3, 0}}, }; -int get_cst_entries(acpi_cstate_t ** entries) +int get_cst_entries(acpi_cstate_t **entries) { *entries = cst_entries; return ARRAY_SIZE(cst_entries); diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index d5721e6..e960b06 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -88,7 +88,7 @@ return 0; } -static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb) +static u32 find_verb(struct device *dev, u32 viddid, const u32 **verb) { int idx=0; diff --git a/src/southbridge/intel/i82801ix/hdaudio.c b/src/southbridge/intel/i82801ix/hdaudio.c index b4cee46..d6d72e1 100644 --- a/src/southbridge/intel/i82801ix/hdaudio.c +++ b/src/southbridge/intel/i82801ix/hdaudio.c @@ -88,7 +88,7 @@ return 0; } -static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb) +static u32 find_verb(struct device *dev, u32 viddid, const u32 **verb) { int idx=0; diff --git a/src/southbridge/intel/i82801jx/hdaudio.c b/src/southbridge/intel/i82801jx/hdaudio.c index 0c9d39c..afde2cf 100644 --- a/src/southbridge/intel/i82801jx/hdaudio.c +++ b/src/southbridge/intel/i82801jx/hdaudio.c @@ -88,7 +88,7 @@ return 0; } -static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb) +static u32 find_verb(struct device *dev, u32 viddid, const u32 **verb) { int idx=0; diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c index 9e3ed43..7f3e6cd 100644 --- a/src/southbridge/intel/ibexpeak/azalia.c +++ b/src/southbridge/intel/ibexpeak/azalia.c @@ -86,7 +86,7 @@ return 0; } -static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb) +static u32 find_verb(struct device *dev, u32 viddid, const u32 **verb) { int idx=0; diff --git a/src/southbridge/intel/lynxpoint/hda_verb.c b/src/southbridge/intel/lynxpoint/hda_verb.c index a8a139c..93a004e 100644 --- a/src/southbridge/intel/lynxpoint/hda_verb.c +++ b/src/southbridge/intel/lynxpoint/hda_verb.c @@ -160,7 +160,7 @@ */ static u32 hda_find_verb(u32 verb_table_bytes, const u32 *verb_table_data, - u32 viddid, const u32 ** verb) + u32 viddid, const u32 **verb) { int idx=0; -- To view, visit https://review.coreboot.org/c/coreboot/+/30624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8260424ee243c06827f2b5939e1568e52539b282 Gerrit-Change-Number: 30624 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/cavium: Remove white spaces before tabs
by HAOUAS Elyes (Code Review) 03 Jan '19

03 Jan '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30620 Change subject: soc/cavium: Remove white spaces before tabs ...................................................................... soc/cavium: Remove white spaces before tabs Change-Id: I8213835ac18a31f1c10d80ba07b50d33f8abcbd9 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/cavium/cn81xx/gpio.c M src/soc/cavium/cn81xx/include/soc/addressmap.h M src/soc/cavium/cn81xx/spi.c M src/soc/cavium/cn81xx/uart.c M src/soc/cavium/common/bdk-coreboot.c 5 files changed, 15 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/30620/1 diff --git a/src/soc/cavium/cn81xx/gpio.c b/src/soc/cavium/cn81xx/gpio.c index 84e36d1..9de1839 100644 --- a/src/soc/cavium/cn81xx/gpio.c +++ b/src/soc/cavium/cn81xx/gpio.c @@ -37,9 +37,9 @@ u64 filt_cnt : 4; /* Glitch filter counter */ u64 filt_sel : 4; /* Glitch filter select */ u64 tx_od : 1; /* Set Output to Open Drain */ - u64 : 3; + u64 : 3; u64 pin_sel : 10; /* Select type of pin */ - u64 : 38; + u64 : 38; } s; }; diff --git a/src/soc/cavium/cn81xx/include/soc/addressmap.h b/src/soc/cavium/cn81xx/include/soc/addressmap.h index f698306..3fb4c9c 100644 --- a/src/soc/cavium/cn81xx/include/soc/addressmap.h +++ b/src/soc/cavium/cn81xx/include/soc/addressmap.h @@ -36,7 +36,7 @@ /* LMC */ #define LMC0_PF_BAR0 0x87E088000000ULL -#define LMC0_DDR_PLL_CTL0 0x258 +#define LMC0_DDR_PLL_CTL0 0x258 /* OCLA */ diff --git a/src/soc/cavium/cn81xx/spi.c b/src/soc/cavium/cn81xx/spi.c index 6527f22..2391f4a 100644 --- a/src/soc/cavium/cn81xx/spi.c +++ b/src/soc/cavium/cn81xx/spi.c @@ -44,7 +44,7 @@ u64 cslate : 1; u64 csena : 4; /* Must be one */ u64 clkdiv : 13; - u64 : 35; + u64 : 35; } s; }; @@ -69,7 +69,7 @@ u64 leavecs : 1; u64 : 3; u64 csid : 2; - u64 : 42; + u64 : 42; } s; }; diff --git a/src/soc/cavium/cn81xx/uart.c b/src/soc/cavium/cn81xx/uart.c index 7a9ea3a..baa9206 100644 --- a/src/soc/cavium/cn81xx/uart.c +++ b/src/soc/cavium/cn81xx/uart.c @@ -34,13 +34,13 @@ u64 uaa_rst : 1; u64 : 2; u64 csclk_en : 1; - u64 : 19; + u64 : 19; u64 h_clkdiv_sel : 3; - u64 : 1; + u64 : 1; u64 h_clkdiv_rst : 1; u64 h_clk_byp_sel : 1; u64 h_clk_en : 1; - u64 : 33; + u64 : 33; } s; }; diff --git a/src/soc/cavium/common/bdk-coreboot.c b/src/soc/cavium/common/bdk-coreboot.c index ff30edf..b6686e8 100644 --- a/src/soc/cavium/common/bdk-coreboot.c +++ b/src/soc/cavium/common/bdk-coreboot.c @@ -39,10 +39,10 @@ * @param twsi_id which TWSI bus to use * @param dev_addr Device address (7 bit) * @param internal_addr - * Internal address. Can be 0, 1 or 2 bytes in width + * Internal address. Can be 0, 1 or 2 bytes in width * @param num_bytes Number of data bytes to read (1-4) * @param ia_width_bytes - * Internal address size in bytes (0, 1, or 2) + * Internal address size in bytes (0, 1, or 2) * * @return Read data, or -1 on failure */ @@ -77,14 +77,14 @@ * @param twsi_id which TWSI interface to use * @param dev_addr TWSI device address (7 bit only) * @param internal_addr - * TWSI internal address (0, 8, or 16 bits) + * TWSI internal address (0, 8, or 16 bits) * @param num_bytes Number of bytes to write (1-8) * @param ia_width_bytes - * internal address width, in bytes (0, 1, 2) + * internal address width, in bytes (0, 1, 2) * @param data Data to write. Data is written MSB first on the twsi bus, and - * only the lower num_bytes bytes of the argument are valid. (If - * a 2 byte write is done, only the low 2 bytes of the argument is - * used. + * only the lower num_bytes bytes of the argument are valid. (If + * a 2 byte write is done, only the low 2 bytes of the argument is + * used. * * @return Zero on success, -1 on error */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30620 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8213835ac18a31f1c10d80ba07b50d33f8abcbd9 Gerrit-Change-Number: 30620 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/pineview/raminit.c: Remove unused variable
by HAOUAS Elyes (Code Review) 02 Jan '19

02 Jan '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30612 Change subject: nb/intel/pineview/raminit.c: Remove unused variable ...................................................................... nb/intel/pineview/raminit.c: Remove unused variable Change-Id: I1e0009677fda44faab2021e1c44827fdba803061 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/pineview/raminit.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/30612/1 diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index 512403f..3413cc1 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -1062,7 +1062,7 @@ static void sdram_dlltiming(struct sysinfo *s) { - u8 reg8, i, pipost; + u8 reg8, i; u16 reg16; u32 reg32; @@ -1119,7 +1119,6 @@ MCHBAR8(0x18e) = (MCHBAR8(0x18e) & ~0x7f) | 0x55; sdram_calibratehwpll(s); } - pipost = 0x34; MCHBAR32(0x248) = MCHBAR32(0x248) & ~(1 << 22); MCHBAR8(0x5d9) = MCHBAR8(0x5d9) & ~0x2; -- To view, visit https://review.coreboot.org/c/coreboot/+/30612 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e0009677fda44faab2021e1c44827fdba803061 Gerrit-Change-Number: 30612 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: mb/google/poppy/variant/rammus: enable USB acpi
by Marx Wang (Code Review) 02 Jan '19

02 Jan '19

Marx Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30607 Change subject: mb/google/poppy/variant/rammus: enable USB acpi ...................................................................... mb/google/poppy/variant/rammus: enable USB acpi Main objective for this change is to export the bluetooth reset gpio to the kernel for use in an rf-kill operation. To do so, we enable USB acpi and define all of the USB2 devices, which includes bluetooth's reset gpio information. BUG=b:119899987 TEST=build and flash to rammus, log into rammus and 'cat /sys/firmware/acpi/tables/SSDT > /tmp/ssdt.dml', copy that ssdt.dsml to /tmp/ssdt.dml on host machine, 'iasl -d /tmp/ssdt.dml', then verify that "reset gpio" shows up in the HS03 node's _DSD package in the table. Signed-off-by: marxwang <marx.wang(a)intel.com> Change-Id: Ieadb3609c7634a20e96c7c4dfb96f5e3f23e468b --- M src/mainboard/google/poppy/Kconfig M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/rammus/gpio.c 3 files changed, 42 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/30607/1 diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index 789578f..59abe72 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -198,6 +198,7 @@ select DRIVERS_I2C_MAX98927 select DRIVERS_I2C_DA7219 select DRIVERS_SPI_ACPI + select DRIVERS_USB_ACPI select MAINBOARD_HAS_SPI_TPM_CR50 config VARIANT_SPECIFIC_OPTIONS_SORAKA diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 7159c02..80fc1d5 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -254,7 +254,45 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 14.0 on end # USB xHCI + device pci 14.0 on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""USB Type C Port 1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB Type A Port 1"" + register "type" = "UPC_TYPE_A" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C8)" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB Type C Port 2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device usb 2.4 on end + end + chip drivers/usb/acpi + register "desc" = ""H1 Secure Micro Controller"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.6 on end + end + chip drivers/usb/acpi + register "desc" = ""Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.8 on end + end + end + end + end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem device pci 15.0 on diff --git a/src/mainboard/google/poppy/variants/rammus/gpio.c b/src/mainboard/google/poppy/variants/rammus/gpio.c index 8b8dd12..d82eeaf 100644 --- a/src/mainboard/google/poppy/variants/rammus/gpio.c +++ b/src/mainboard/google/poppy/variants/rammus/gpio.c @@ -127,8 +127,8 @@ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP), /* C7 : SM1DATA ==> NC */ PAD_CFG_NC(GPP_C7), - /* C8 : UART0_RXD ==> NC(BT_OFF#) */ - PAD_CFG_NC(GPP_C8), + /* C8 : UART0_RXD ==> BT_OFF# */ + PAD_CFG_GPO(GPP_C8, 1, DEEP), /* C9 : UART0_TXD ==> NC(WLAN_OFF#) */ PAD_CFG_NC(GPP_C9), /* C10 : UART0_RTS# ==> NC(T0817) */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30607 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieadb3609c7634a20e96c7c4dfb96f5e3f23e468b Gerrit-Change-Number: 30607 Gerrit-PatchSet: 1 Gerrit-Owner: Marx Wang <marx.wang(a)intel.com> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: mb: Remove duplicated USE_NATIVE_RAMINIT
by HAOUAS Elyes (Code Review) 02 Jan '19

02 Jan '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30606 Change subject: mb: Remove duplicated USE_NATIVE_RAMINIT ...................................................................... mb: Remove duplicated USE_NATIVE_RAMINIT USE_NATIVE_RAMINIT is enabled here: intel/sandybridge/Kconfig Change-Id: Id823e3dc3459ee575f4d37b5679a6a36affe2962 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/apple/macbookair4_2/Kconfig M src/mainboard/asrock/b75pro3-m/Kconfig M src/mainboard/asus/maximus_iv_gene-z/Kconfig M src/mainboard/asus/p8h61-m_lx/Kconfig M src/mainboard/asus/p8h61-m_pro/Kconfig M src/mainboard/compulab/intense_pc/Kconfig M src/mainboard/gigabyte/ga-b75m-d3h/Kconfig M src/mainboard/gigabyte/ga-b75m-d3v/Kconfig M src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig M src/mainboard/hp/2570p/Kconfig M src/mainboard/hp/2760p/Kconfig M src/mainboard/hp/8460p/Kconfig M src/mainboard/hp/8470p/Kconfig M src/mainboard/hp/8770w/Kconfig M src/mainboard/hp/compaq_8200_elite_sff/Kconfig M src/mainboard/hp/folio_9470m/Kconfig M src/mainboard/hp/revolve_810_g1/Kconfig M src/mainboard/lenovo/l520/Kconfig M src/mainboard/lenovo/s230u/Kconfig M src/mainboard/lenovo/t420/Kconfig M src/mainboard/lenovo/t420s/Kconfig M src/mainboard/lenovo/t430/Kconfig M src/mainboard/lenovo/t430s/Kconfig M src/mainboard/lenovo/t520/Kconfig M src/mainboard/lenovo/t530/Kconfig M src/mainboard/lenovo/x131e/Kconfig M src/mainboard/lenovo/x1_carbon_gen1/Kconfig M src/mainboard/lenovo/x230/Kconfig M src/mainboard/sapphire/pureplatinumh61/Kconfig 29 files changed, 0 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/30606/1 diff --git a/src/mainboard/apple/macbookair4_2/Kconfig b/src/mainboard/apple/macbookair4_2/Kconfig index d233d00..7b72389 100644 --- a/src/mainboard/apple/macbookair4_2/Kconfig +++ b/src/mainboard/apple/macbookair4_2/Kconfig @@ -9,7 +9,6 @@ select HAVE_ACPI_TABLES select INTEL_INT15 select NORTHBRIDGE_INTEL_SANDYBRIDGE - select USE_NATIVE_RAMINIT select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_BD82X6X select SYSTEM_TYPE_LAPTOP diff --git a/src/mainboard/asrock/b75pro3-m/Kconfig b/src/mainboard/asrock/b75pro3-m/Kconfig index c0f907f..0c75fb0 100644 --- a/src/mainboard/asrock/b75pro3-m/Kconfig +++ b/src/mainboard/asrock/b75pro3-m/Kconfig @@ -26,7 +26,6 @@ select NORTHBRIDGE_INTEL_IVYBRIDGE select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_C216 - select USE_NATIVE_RAMINIT select MAINBOARD_HAS_LIBGFXINIT select DRIVERS_ASMEDIA_ASPM_BLACKLIST diff --git a/src/mainboard/asus/maximus_iv_gene-z/Kconfig b/src/mainboard/asus/maximus_iv_gene-z/Kconfig index c6e0dce..ef2a0ae 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/Kconfig +++ b/src/mainboard/asus/maximus_iv_gene-z/Kconfig @@ -32,7 +32,6 @@ select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_BD82X6X select SUPERIO_NUVOTON_NCT6776 - select USE_NATIVE_RAMINIT config MAINBOARD_DIR string diff --git a/src/mainboard/asus/p8h61-m_lx/Kconfig b/src/mainboard/asus/p8h61-m_lx/Kconfig index 0960803..568b0e8 100644 --- a/src/mainboard/asus/p8h61-m_lx/Kconfig +++ b/src/mainboard/asus/p8h61-m_lx/Kconfig @@ -34,7 +34,6 @@ select SOUTHBRIDGE_INTEL_BD82X6X select SUPERIO_NUVOTON_NCT6776 select SUPERIO_NUVOTON_NCT6776_COM_A - select USE_NATIVE_RAMINIT config MAINBOARD_DIR string diff --git a/src/mainboard/asus/p8h61-m_pro/Kconfig b/src/mainboard/asus/p8h61-m_pro/Kconfig index 8fcc650..d372280 100644 --- a/src/mainboard/asus/p8h61-m_pro/Kconfig +++ b/src/mainboard/asus/p8h61-m_pro/Kconfig @@ -25,7 +25,6 @@ select NORTHBRIDGE_INTEL_IVYBRIDGE select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_BD82X6X - select USE_NATIVE_RAMINIT select SUPERIO_NUVOTON_NCT6776 select MAINBOARD_HAS_LIBGFXINIT select HAVE_OPTION_TABLE diff --git a/src/mainboard/compulab/intense_pc/Kconfig b/src/mainboard/compulab/intense_pc/Kconfig index fccfb86..f4854d3 100644 --- a/src/mainboard/compulab/intense_pc/Kconfig +++ b/src/mainboard/compulab/intense_pc/Kconfig @@ -13,7 +13,6 @@ select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_C216 select SYSTEM_TYPE_LAPTOP - select USE_NATIVE_RAMINIT select SUPERIO_SMSC_SIO1007 config MAINBOARD_DIR diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig index 7aefcfb..1c104f2 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig @@ -5,7 +5,6 @@ select ARCH_X86 select CPU_INTEL_SOCKET_LGA1155 select NORTHBRIDGE_INTEL_IVYBRIDGE - select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_C216 select SUPERIO_ITE_IT8728F select BOARD_ROMSIZE_KB_8192 diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig index a2a89b9..7fc6694 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig +++ b/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig @@ -5,7 +5,6 @@ select ARCH_X86 select CPU_INTEL_SOCKET_LGA1155 select NORTHBRIDGE_INTEL_IVYBRIDGE - select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_C216 select SUPERIO_ITE_IT8728F select BOARD_ROMSIZE_KB_8192 diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig b/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig index a4595f5..7153d04 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig @@ -26,7 +26,6 @@ select NORTHBRIDGE_INTEL_SANDYBRIDGE select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_BD82X6X - select USE_NATIVE_RAMINIT select SUPERIO_ITE_IT8728F select MAINBOARD_HAS_LIBGFXINIT select INTEL_GMA_HAVE_VBT diff --git a/src/mainboard/hp/2570p/Kconfig b/src/mainboard/hp/2570p/Kconfig index 8cda10c..12aa762 100644 --- a/src/mainboard/hp/2570p/Kconfig +++ b/src/mainboard/hp/2570p/Kconfig @@ -27,7 +27,6 @@ select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_C216 select SYSTEM_TYPE_LAPTOP - select USE_NATIVE_RAMINIT select EC_HP_KBC1126 select MAINBOARD_HAS_LIBGFXINIT select GFX_GMA_INTERNAL_IS_LVDS diff --git a/src/mainboard/hp/2760p/Kconfig b/src/mainboard/hp/2760p/Kconfig index 529862e..b7eb070 100644 --- a/src/mainboard/hp/2760p/Kconfig +++ b/src/mainboard/hp/2760p/Kconfig @@ -27,7 +27,6 @@ select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_BD82X6X select SYSTEM_TYPE_LAPTOP - select USE_NATIVE_RAMINIT select EC_HP_KBC1126 select MAINBOARD_HAS_LIBGFXINIT select GFX_GMA_INTERNAL_IS_LVDS diff --git a/src/mainboard/hp/8460p/Kconfig b/src/mainboard/hp/8460p/Kconfig index 57e6268..0c01772 100644 --- a/src/mainboard/hp/8460p/Kconfig +++ b/src/mainboard/hp/8460p/Kconfig @@ -27,7 +27,6 @@ select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_BD82X6X select SYSTEM_TYPE_LAPTOP - select USE_NATIVE_RAMINIT select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 diff --git a/src/mainboard/hp/8470p/Kconfig b/src/mainboard/hp/8470p/Kconfig index fafa686..19749d5 100644 --- a/src/mainboard/hp/8470p/Kconfig +++ b/src/mainboard/hp/8470p/Kconfig @@ -27,7 +27,6 @@ select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_C216 select SYSTEM_TYPE_LAPTOP - select USE_NATIVE_RAMINIT select MAINBOARD_HAS_LIBGFXINIT select GFX_GMA_INTERNAL_IS_LVDS select EC_HP_KBC1126 diff --git a/src/mainboard/hp/8770w/Kconfig b/src/mainboard/hp/8770w/Kconfig index 1ab9c60..ecf324d 100644 --- a/src/mainboard/hp/8770w/Kconfig +++ b/src/mainboard/hp/8770w/Kconfig @@ -27,7 +27,6 @@ select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_C216 select SYSTEM_TYPE_LAPTOP - select USE_NATIVE_RAMINIT select EC_HP_KBC1126 select SUPERIO_SMSC_LPC47N217 select HAVE_OPTION_TABLE diff --git a/src/mainboard/hp/compaq_8200_elite_sff/Kconfig b/src/mainboard/hp/compaq_8200_elite_sff/Kconfig index 48132a8..29f3ba9 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/Kconfig +++ b/src/mainboard/hp/compaq_8200_elite_sff/Kconfig @@ -10,7 +10,6 @@ select NORTHBRIDGE_INTEL_SANDYBRIDGE select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_BD82X6X - select USE_NATIVE_RAMINIT select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 select HAVE_OPTION_TABLE diff --git a/src/mainboard/hp/folio_9470m/Kconfig b/src/mainboard/hp/folio_9470m/Kconfig index eaeebdb..ade3196 100644 --- a/src/mainboard/hp/folio_9470m/Kconfig +++ b/src/mainboard/hp/folio_9470m/Kconfig @@ -13,7 +13,6 @@ select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_C216 select SYSTEM_TYPE_LAPTOP - select USE_NATIVE_RAMINIT select MAINBOARD_HAS_LPC_TPM select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT diff --git a/src/mainboard/hp/revolve_810_g1/Kconfig b/src/mainboard/hp/revolve_810_g1/Kconfig index 81f5d39..f654f0f 100644 --- a/src/mainboard/hp/revolve_810_g1/Kconfig +++ b/src/mainboard/hp/revolve_810_g1/Kconfig @@ -13,7 +13,6 @@ select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_C216 select SYSTEM_TYPE_LAPTOP - select USE_NATIVE_RAMINIT select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 select GENERIC_SPD_BIN diff --git a/src/mainboard/lenovo/l520/Kconfig b/src/mainboard/lenovo/l520/Kconfig index 902a1ce..a91c233 100644 --- a/src/mainboard/lenovo/l520/Kconfig +++ b/src/mainboard/lenovo/l520/Kconfig @@ -16,7 +16,6 @@ select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_BD82X6X select SYSTEM_TYPE_LAPTOP - select USE_NATIVE_RAMINIT config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/s230u/Kconfig b/src/mainboard/lenovo/s230u/Kconfig index e57ffe0..3ad1488 100644 --- a/src/mainboard/lenovo/s230u/Kconfig +++ b/src/mainboard/lenovo/s230u/Kconfig @@ -5,7 +5,6 @@ select SYSTEM_TYPE_LAPTOP select CPU_INTEL_SOCKET_RPGA989 select NORTHBRIDGE_INTEL_IVYBRIDGE - select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_C216 select EC_COMPAL_ENE932 select EC_ACPI diff --git a/src/mainboard/lenovo/t420/Kconfig b/src/mainboard/lenovo/t420/Kconfig index 696558c..e0535c6 100644 --- a/src/mainboard/lenovo/t420/Kconfig +++ b/src/mainboard/lenovo/t420/Kconfig @@ -5,7 +5,6 @@ select SYSTEM_TYPE_LAPTOP select CPU_INTEL_SOCKET_RPGA988B select NORTHBRIDGE_INTEL_SANDYBRIDGE - select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_BD82X6X select EC_LENOVO_PMH7 select EC_LENOVO_H8 diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig index 0f9a957..3a6e960 100644 --- a/src/mainboard/lenovo/t420s/Kconfig +++ b/src/mainboard/lenovo/t420s/Kconfig @@ -5,7 +5,6 @@ select SYSTEM_TYPE_LAPTOP select CPU_INTEL_SOCKET_RPGA988B select NORTHBRIDGE_INTEL_SANDYBRIDGE - select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_BD82X6X select EC_LENOVO_PMH7 select EC_LENOVO_H8 diff --git a/src/mainboard/lenovo/t430/Kconfig b/src/mainboard/lenovo/t430/Kconfig index 7272d53..3971a0f 100644 --- a/src/mainboard/lenovo/t430/Kconfig +++ b/src/mainboard/lenovo/t430/Kconfig @@ -20,7 +20,6 @@ select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_C216 select SYSTEM_TYPE_LAPTOP - select USE_NATIVE_RAMINIT select DRIVERS_LENOVO_HYBRID_GRAPHICS select MAINBOARD_HAS_LIBGFXINIT select GFX_GMA_INTERNAL_IS_LVDS diff --git a/src/mainboard/lenovo/t430s/Kconfig b/src/mainboard/lenovo/t430s/Kconfig index 22af597..2ea64bc 100644 --- a/src/mainboard/lenovo/t430s/Kconfig +++ b/src/mainboard/lenovo/t430s/Kconfig @@ -5,7 +5,6 @@ select SYSTEM_TYPE_LAPTOP select CPU_INTEL_SOCKET_RPGA989 select NORTHBRIDGE_INTEL_IVYBRIDGE - select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_C216 select EC_LENOVO_PMH7 select EC_LENOVO_H8 diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index 6bc5884..7cab6e1 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -3,7 +3,6 @@ select SYSTEM_TYPE_LAPTOP select CPU_INTEL_SOCKET_RPGA988B select NORTHBRIDGE_INTEL_SANDYBRIDGE - select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_BD82X6X select EC_LENOVO_PMH7 select EC_LENOVO_H8 diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index b5c4048..6190d88 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -3,7 +3,6 @@ select SYSTEM_TYPE_LAPTOP select CPU_INTEL_SOCKET_RPGA989 select NORTHBRIDGE_INTEL_IVYBRIDGE - select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_C216 select EC_LENOVO_PMH7 select EC_LENOVO_H8 diff --git a/src/mainboard/lenovo/x131e/Kconfig b/src/mainboard/lenovo/x131e/Kconfig index fbff083..521281a 100644 --- a/src/mainboard/lenovo/x131e/Kconfig +++ b/src/mainboard/lenovo/x131e/Kconfig @@ -5,7 +5,6 @@ select SYSTEM_TYPE_LAPTOP select CPU_INTEL_SOCKET_RPGA989 select NORTHBRIDGE_INTEL_SANDYBRIDGE - select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_C216 select EC_LENOVO_PMH7 select EC_LENOVO_H8 diff --git a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig index 3c4dba3..eed3ccc 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig +++ b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig @@ -5,7 +5,6 @@ select SYSTEM_TYPE_LAPTOP select CPU_INTEL_SOCKET_RPGA989 select NORTHBRIDGE_INTEL_IVYBRIDGE - select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_C216 select EC_LENOVO_PMH7 select EC_LENOVO_H8 diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig index 524d4d3..74035cb 100644 --- a/src/mainboard/lenovo/x230/Kconfig +++ b/src/mainboard/lenovo/x230/Kconfig @@ -5,7 +5,6 @@ select SYSTEM_TYPE_LAPTOP select CPU_INTEL_SOCKET_RPGA989 select NORTHBRIDGE_INTEL_IVYBRIDGE - select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_C216 select EC_LENOVO_PMH7 select EC_LENOVO_H8 diff --git a/src/mainboard/sapphire/pureplatinumh61/Kconfig b/src/mainboard/sapphire/pureplatinumh61/Kconfig index a07617e..71cb6b2 100644 --- a/src/mainboard/sapphire/pureplatinumh61/Kconfig +++ b/src/mainboard/sapphire/pureplatinumh61/Kconfig @@ -5,7 +5,6 @@ select ARCH_X86 select CPU_INTEL_SOCKET_LGA1155 select NORTHBRIDGE_INTEL_IVYBRIDGE - select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_BD82X6X select SUPERIO_FINTEK_F71808A select BOARD_ROMSIZE_KB_4096 -- To view, visit https://review.coreboot.org/c/coreboot/+/30606 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id823e3dc3459ee575f4d37b5679a6a36affe2962 Gerrit-Change-Number: 30606 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: mb: Remove duplicated ENABLE_VMX
by HAOUAS Elyes (Code Review) 02 Jan '19

02 Jan '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30605 Change subject: mb: Remove duplicated ENABLE_VMX ...................................................................... mb: Remove duplicated ENABLE_VMX ENABLE_VMX is CPU specific and it is already enabled here: src/cpu/intel/common/Kconfig Change-Id: I130738aa3758a9212bab10f90edb7b2ab6830597 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/hp/folio_9470m/Kconfig M src/mainboard/hp/revolve_810_g1/Kconfig M src/mainboard/kontron/ktqm77/Kconfig M src/mainboard/lenovo/t420/Kconfig M src/mainboard/lenovo/t430/Kconfig M src/mainboard/lenovo/t430s/Kconfig M src/mainboard/lenovo/t530/Kconfig M src/mainboard/roda/rv11/Kconfig 8 files changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/30605/1 diff --git a/src/mainboard/hp/folio_9470m/Kconfig b/src/mainboard/hp/folio_9470m/Kconfig index 23d0eb5..eaeebdb 100644 --- a/src/mainboard/hp/folio_9470m/Kconfig +++ b/src/mainboard/hp/folio_9470m/Kconfig @@ -17,7 +17,6 @@ select MAINBOARD_HAS_LPC_TPM select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT - select ENABLE_VMX select MAINBOARD_HAS_LIBGFXINIT select GFX_GMA_INTERNAL_IS_LVDS diff --git a/src/mainboard/hp/revolve_810_g1/Kconfig b/src/mainboard/hp/revolve_810_g1/Kconfig index d2389a1..81f5d39 100644 --- a/src/mainboard/hp/revolve_810_g1/Kconfig +++ b/src/mainboard/hp/revolve_810_g1/Kconfig @@ -19,7 +19,6 @@ select GENERIC_SPD_BIN select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT - select ENABLE_VMX select MAINBOARD_HAS_LIBGFXINIT select GFX_GMA_INTERNAL_IS_LVDS diff --git a/src/mainboard/kontron/ktqm77/Kconfig b/src/mainboard/kontron/ktqm77/Kconfig index e137540..eddca02 100644 --- a/src/mainboard/kontron/ktqm77/Kconfig +++ b/src/mainboard/kontron/ktqm77/Kconfig @@ -11,7 +11,6 @@ select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME - select ENABLE_VMX select MAINBOARD_HAS_LIBGFXINIT select GFX_GMA_ANALOG_I2C_HDMI_B select GFX_GMA_INTERNAL_IS_LVDS diff --git a/src/mainboard/lenovo/t420/Kconfig b/src/mainboard/lenovo/t420/Kconfig index b7f01b0..696558c 100644 --- a/src/mainboard/lenovo/t420/Kconfig +++ b/src/mainboard/lenovo/t420/Kconfig @@ -17,7 +17,6 @@ select HAVE_ACPI_RESUME select INTEL_INT15 select SANDYBRIDGE_IVYBRIDGE_LVDS - select ENABLE_VMX select DRIVERS_RICOH_RCE822 select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 diff --git a/src/mainboard/lenovo/t430/Kconfig b/src/mainboard/lenovo/t430/Kconfig index 44f511d..7272d53 100644 --- a/src/mainboard/lenovo/t430/Kconfig +++ b/src/mainboard/lenovo/t430/Kconfig @@ -21,7 +21,6 @@ select SOUTHBRIDGE_INTEL_C216 select SYSTEM_TYPE_LAPTOP select USE_NATIVE_RAMINIT - select ENABLE_VMX select DRIVERS_LENOVO_HYBRID_GRAPHICS select MAINBOARD_HAS_LIBGFXINIT select GFX_GMA_INTERNAL_IS_LVDS diff --git a/src/mainboard/lenovo/t430s/Kconfig b/src/mainboard/lenovo/t430s/Kconfig index e507ec8..22af597 100644 --- a/src/mainboard/lenovo/t430s/Kconfig +++ b/src/mainboard/lenovo/t430s/Kconfig @@ -17,7 +17,6 @@ select HAVE_ACPI_RESUME select INTEL_INT15 select SANDYBRIDGE_IVYBRIDGE_LVDS if BOARD_LENOVO_T430S - select ENABLE_VMX select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 select MAINBOARD_HAS_LIBGFXINIT diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index 61752d8..b5c4048 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -15,7 +15,6 @@ select HAVE_ACPI_RESUME select INTEL_INT15 select SANDYBRIDGE_IVYBRIDGE_LVDS - select ENABLE_VMX select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 select DRIVERS_LENOVO_HYBRID_GRAPHICS diff --git a/src/mainboard/roda/rv11/Kconfig b/src/mainboard/roda/rv11/Kconfig index 5f99f66..33994c3 100644 --- a/src/mainboard/roda/rv11/Kconfig +++ b/src/mainboard/roda/rv11/Kconfig @@ -10,7 +10,6 @@ select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME - select ENABLE_VMX select EC_RODA_IT8518 select SERIRQ_CONTINUOUS_MODE select MAINBOARD_HAS_LIBGFXINIT -- To view, visit https://review.coreboot.org/c/coreboot/+/30605 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I130738aa3758a9212bab10f90edb7b2ab6830597 Gerrit-Change-Number: 30605 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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coreboot-gerrit January 2019