coreboot-gerrit January 2019

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Change in ...coreboot[master]: cpu/amd: Use `get_option()`
by Paul Menzel (Code Review) 07 Jan '19

07 Jan '19

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30715 Change subject: cpu/amd: Use `get_option()` ...................................................................... cpu/amd: Use `get_option()` Fix warnings on the console. coreboot-4.9-214-g0dd2014390 Mon Jan 7 15:17:13 UTC 2019 romstage starting... NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead. NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead. NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead. Change-Id: I8501ff256676cd0ec4b59b28f4f1e0f2a9f74cac Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/cpu/amd/family_10h-family_15h/init_cpus.c 1 file changed, 16 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/30715/1 diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index 2ddbc43..b8e11e4 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -147,6 +147,9 @@ // here assume the OS don't change our apicid u32 ap_apicid; + u8 nvram; + bool multicore; + u32 nodes; u32 disable_siblings; u32 cores_found; @@ -155,12 +158,13 @@ /* get_nodes define in ht_wrapper.c */ nodes = get_nodes(); - if (!IS_ENABLED(CONFIG_LOGICAL_CPUS) || - read_option(multi_core, 0) != 0) { // 0 means multi core + multicore = true; + if (get_option(&nvram, "multi_core") == CB_SUCCESS) + multicore = !!nvram; + + disable_siblings = 0; + if (!IS_ENABLED(CONFIG_LOGICAL_CPUS) || !multicore) disable_siblings = 1; - } else { - disable_siblings = 0; - } for (i = 0; i < nodes; i++) { if ((node >= 0) && (i != node)) @@ -635,11 +639,17 @@ //it is running on core0 of node0 void start_other_cores(uint32_t bsp_apicid) { + u8 nvram; u32 nodes; u32 nodeid; + bool multicore; // disable multi_core - if (read_option(multi_core, 0) != 0) { + multicore = true; + if (get_option(&nvram, "multi_core") == CB_SUCCESS) + multicore = !!nvram; + + if (!multicore) { printk(BIOS_DEBUG, "Skip additional core init\n"); return; } -- To view, visit https://review.coreboot.org/c/coreboot/+/30715 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8501ff256676cd0ec4b59b28f4f1e0f2a9f74cac Gerrit-Change-Number: 30715 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: cpu/intel/common: Fix generated exception if VMX is not supported
by HAOUAS Elyes (Code Review) 07 Jan '19

07 Jan '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30713 Change subject: cpu/intel/common: Fix generated exception if VMX is not supported ...................................................................... cpu/intel/common: Fix generated exception if VMX is not supported Reading rdmsr(IA32_FEATURE_CONTROL) in function et_feature_ctrl_lock() will generate an exception if the CPU do not support this MSR. Tested on pentium4 (CPUID F65). Change-Id: I72e138e3bcffe1dcd4e20739a8d07c9abfab4f80 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/intel/common/common_init.c 1 file changed, 9 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/30713/1 diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c index 4f3bcac..882db3e 100644 --- a/src/cpu/intel/common/common_init.c +++ b/src/cpu/intel/common/common_init.c @@ -23,6 +23,14 @@ void set_vmx_and_lock(void) { + uint32_t feature_flag = cpu_get_feature_flags_ecx(); + + /* Check that the VMX is supported before reading or writing the MSR. */ + if (!((feature_flag & CPUID_VMX) || (feature_flag & CPUID_SMX))) { + printk(BIOS_DEBUG, "CPU doesn't support VMX; exiting\n"); + return; + } + set_feature_ctrl_vmx(); set_feature_ctrl_lock(); } @@ -30,16 +38,9 @@ void set_feature_ctrl_vmx(void) { msr_t msr; - uint32_t feature_flag; + uint32_t feature_flag = cpu_get_feature_flags_ecx(); int enable = IS_ENABLED(CONFIG_ENABLE_VMX); - feature_flag = cpu_get_feature_flags_ecx(); - /* Check that the VMX is supported before reading or writing the MSR. */ - if (!((feature_flag & CPUID_VMX) || (feature_flag & CPUID_SMX))) { - printk(BIOS_DEBUG, "CPU doesn't support VMX; exiting\n"); - return; - } - msr = rdmsr(IA32_FEATURE_CONTROL); if (msr.lo & (1 << 0)) { -- To view, visit https://review.coreboot.org/c/coreboot/+/30713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72e138e3bcffe1dcd4e20739a8d07c9abfab4f80 Gerrit-Change-Number: 30713 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/{d41s,d510mo}: Remove references to PCIe port 5 and 6
by Arthur Heymans (Code Review) 07 Jan '19

07 Jan '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30712 Change subject: mb/{d41s,d510mo}: Remove references to PCIe port 5 and 6 ...................................................................... mb/{d41s,d510mo}: Remove references to PCIe port 5 and 6 The southbridge has the function disable bits for port 5 and 6 strapped RO to 1 (disable). Change-Id: I2948935d42b9031d61f9e5b3f06b769e68f5a042 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/foxconn/d41s/devicetree.cb M src/mainboard/intel/d510mo/devicetree.cb 2 files changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/30712/1 diff --git a/src/mainboard/foxconn/d41s/devicetree.cb b/src/mainboard/foxconn/d41s/devicetree.cb index 21e8762..75df88e 100644 --- a/src/mainboard/foxconn/d41s/devicetree.cb +++ b/src/mainboard/foxconn/d41s/devicetree.cb @@ -51,7 +51,6 @@ end device pci 1c.2 off end # PCIe 3 device pci 1c.3 off end # PCIe 4 - # (PCIe 5 and 6 not on nm10?) device pci 1d.0 on end # USB device pci 1d.1 on end # USB device pci 1d.2 on end # USB diff --git a/src/mainboard/intel/d510mo/devicetree.cb b/src/mainboard/intel/d510mo/devicetree.cb index a80180a..a008610 100644 --- a/src/mainboard/intel/d510mo/devicetree.cb +++ b/src/mainboard/intel/d510mo/devicetree.cb @@ -49,7 +49,6 @@ device pci 1c.1 on end # PCIe 2 device pci 1c.2 on end # PCIe 3 device pci 1c.3 on end # PCIe 4 - # (PCIe 5 and 6 not on nm10?) device pci 1d.0 on end # USB device pci 1d.1 on end # USB device pci 1d.2 on end # USB -- To view, visit https://review.coreboot.org/c/coreboot/+/30712 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2948935d42b9031d61f9e5b3f06b769e68f5a042 Gerrit-Change-Number: 30712 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/{ga-g41m-es2l,d954gclf,rk886ex}: Fix devicetree
by Arthur Heymans (Code Review) 07 Jan '19

07 Jan '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30711 Change subject: mb/{ga-g41m-es2l,d954gclf,rk886ex}: Fix devicetree ...................................................................... mb/{ga-g41m-es2l,d954gclf,rk886ex}: Fix devicetree The devicetree was synced incorrectly with respect to the function disable register set in romstage. Change-Id: I189c5fdc433b5577ae008abf42878cdc6e3f2d52 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb M src/mainboard/intel/d945gclf/devicetree.cb M src/mainboard/roda/rk886ex/devicetree.cb 3 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/30711/1 diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb index 9f92d2a..05edb27 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb @@ -61,7 +61,7 @@ subsystemid 0x1458 0xe000 end end - device pci 1c.2 on end # PCIe 3 + device pci 1c.2 off end # PCIe 3 device pci 1c.3 off end # PCIe 4 device pci 1c.4 off end # PCIe 5 device pci 1c.5 off end # PCIe 6 diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb index eaa26ef..90c517f 100644 --- a/src/mainboard/intel/d945gclf/devicetree.cb +++ b/src/mainboard/intel/d945gclf/devicetree.cb @@ -64,7 +64,7 @@ device pci 1d.0 on end # USB UHCI device pci 1d.1 on end # USB UHCI device pci 1d.2 on end # USB UHCI - device pci 1d.3 on end # USB UHCI + device pci 1d.3 off end # USB UHCI device pci 1d.7 on end # USB2 EHCI device pci 1e.0 on end # PCI bridge device pci 1e.2 off end # AC'97 Audio diff --git a/src/mainboard/roda/rk886ex/devicetree.cb b/src/mainboard/roda/rk886ex/devicetree.cb index e3bcc5b..ec42766 100644 --- a/src/mainboard/roda/rk886ex/devicetree.cb +++ b/src/mainboard/roda/rk886ex/devicetree.cb @@ -63,7 +63,7 @@ register "ide_enable_secondary" = "0x0" register "sata_ahci" = "0x0" - device pci 1b.0 on end # High Definition Audio + device pci 1b.0 off end # High Definition Audio device pci 1c.0 on end # PCIe port 1 device pci 1c.1 off end # PCIe port 2 device pci 1c.2 off end # PCIe port 3 @@ -84,7 +84,7 @@ device pci 3.3 off end # smartcard end end # PCI bridge - device pci 1e.2 off end # AC'97 Audio + device pci 1e.2 on end # AC'97 Audio device pci 1e.3 off end # AC'97 Modem device pci 1f.0 on # LPC bridge chip superio/smsc/lpc47n227 -- To view, visit https://review.coreboot.org/c/coreboot/+/30711 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I189c5fdc433b5577ae008abf42878cdc6e3f2d52 Gerrit-Change-Number: 30711 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/mb/asus/p5qpl-am/romstage.c: Fix comment
by Angel Pons (Code Review) 07 Jan '19

07 Jan '19

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30705 Change subject: src/mb/asus/p5qpl-am/romstage.c: Fix comment ...................................................................... src/mb/asus/p5qpl-am/romstage.c: Fix comment Change-Id: I2b3ad53766bc9cef5ae00392814a03a3e177ad35 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asus/p5qpl-am/romstage.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/30705/1 diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c index bc04261..96473bb 100644 --- a/src/mainboard/asus/p5qpl-am/romstage.c +++ b/src/mainboard/asus/p5qpl-am/romstage.c @@ -54,7 +54,7 @@ } /* - * BSEL mch straps are not hooked up to the CPU as usual but the the SIO + * BSEL MCH straps are not hooked up to the CPU as usual but to the SIO * BSEL0 -> not hooked up (such configs are not supported anyways) * BSEL1 -> GPIO33 * BSEL2 -> GPIO40 -- To view, visit https://review.coreboot.org/c/coreboot/+/30705 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b3ad53766bc9cef5ae00392814a03a3e177ad35 Gerrit-Change-Number: 30705 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/icelake: Increase bootblock size
by Subrata Banik (Code Review) 07 Jan '19

07 Jan '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30702 Change subject: soc/intel/icelake: Increase bootblock size ...................................................................... soc/intel/icelake: Increase bootblock size This patch fixes icelake build brokenness due to bootblock size issue. Change-Id: I66706e66ac1bce677fe11022d0eef44b9efc2e76 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/icelake/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/30702/1 diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 727fccee..6343ca5 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -176,7 +176,7 @@ config C_ENV_BOOTBLOCK_SIZE hex - default 0x8000 + default 0xC000 config CBFS_SIZE hex -- To view, visit https://review.coreboot.org/c/coreboot/+/30702 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66706e66ac1bce677fe11022d0eef44b9efc2e76 Gerrit-Change-Number: 30702 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: google/kukui: Enable VBOOT_VBNV_FLASH to store VBNV in flash
by Tristan Hsieh (Code Review) 07 Jan '19

07 Jan '19

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30701 Change subject: google/kukui: Enable VBOOT_VBNV_FLASH to store VBNV in flash ...................................................................... google/kukui: Enable VBOOT_VBNV_FLASH to store VBNV in flash Reading nvdata from non-volatile flash storage. With this patch, it will pass the firmware test that corrupts FW_MAIN_A and boots up with FW_MAIN_B. BUG=b:80501386 BRANCH=none Test=test_that --board=kukui 172.23.213.147 firmware_CorruptFwSigA Change-Id: I9ef6bff019ee986ff018202bfd4d4a875526ec6c Signed-off-by: Tristan Shieh <tristan.shieh(a)mediatek.com> --- M src/mainboard/google/kukui/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/30701/1 diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index 5be904c..287fd0d 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -2,6 +2,7 @@ config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES + select VBOOT_VBNV_FLASH config BOARD_SPECIFIC_OPTIONS def_bool y -- To view, visit https://review.coreboot.org/c/coreboot/+/30701 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ef6bff019ee986ff018202bfd4d4a875526ec6c Gerrit-Change-Number: 30701 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch: Disable the SA IPU for hatch
by V Sowmya (Code Review) 07 Jan '19

07 Jan '19

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30699 Change subject: mb/google/hatch: Disable the SA IPU for hatch ...................................................................... mb/google/hatch: Disable the SA IPU for hatch This patch disables the SA IPU for hatch since it is not using the IPU. Change-Id: Ib2afc4cc4fd7ef98365b0b98130b0e8bc757ac2a Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/30699/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index a3d0bc6..c61c5e5 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -74,6 +74,7 @@ device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device device pci 04.0 off end # SA Thermal device + device pci 05.0 off end # SA IPU device pci 12.0 off end # Thermal Subsystem device pci 12.5 off end # UFS SCS device pci 12.6 off end # GSPI #2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30699 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2afc4cc4fd7ef98365b0b98130b0e8bc757ac2a Gerrit-Change-Number: 30699 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: Add an option to enable or disable IPU
by V Sowmya (Code Review) 07 Jan '19

07 Jan '19

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30698 Change subject: soc/intel/cannonlake: Add an option to enable or disable IPU ...................................................................... soc/intel/cannonlake: Add an option to enable or disable IPU This patch provides an option to enable or disable IPU (image processing unit), * Expose SaIpuEnable FSP UPD param in chip.h. * Add an entry for SA IPU in the pci_devs.h. * Enable/Disable the IPU based on device status. Change-Id: Ia155bc242dd33e816d056bbea1e3d4c1cbbe23da Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/include/soc/pci_devs.h M src/soc/intel/cannonlake/romstage/fsp_params.c 3 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/30698/1 diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 3a723d2..5ef516c 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -110,6 +110,8 @@ SaGv_Enabled, } SaGv; + /* SA IPU (Image Processing Unit) */ + uint8_t SaIpuEnabled; /* Rank Margin Tool. 1:Enable, 0:Disable */ uint8_t RMT; diff --git a/src/soc/intel/cannonlake/include/soc/pci_devs.h b/src/soc/intel/cannonlake/include/soc/pci_devs.h index 77ae746..005cda3 100644 --- a/src/soc/intel/cannonlake/include/soc/pci_devs.h +++ b/src/soc/intel/cannonlake/include/soc/pci_devs.h @@ -47,6 +47,10 @@ #define SA_DEVFN_DSP _SA_DEVFN(DSP) #define SA_DEV_DSP _SA_DEV(DSP) +#define SA_DEV_SLOT_IPU 0x05 +#define SA_DEVFN_IPU _SA_DEVFN(IPU) +#define SA_DEV_IPU _SA_DEV(IPU) + /* PCH Devices */ #define PCH_DEV_SLOT_THERMAL 0x12 #define PCH_DEVFN_THERMAL _PCH_DEVFN(THERMAL, 0) diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index c3a2509..ab1bfc0 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -67,6 +67,12 @@ else m_cfg->PchHdaEnable = dev->enabled; + /* Enable IPU only if the device is enabled */ + dev = dev_find_slot(0, SA_DEVFN_IPU); + if (!dev) + m_cfg->SaIpuEnable = 0; + else + m_cfg->SaIpuEnable = dev->enabled; } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) -- To view, visit https://review.coreboot.org/c/coreboot/+/30698 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia155bc242dd33e816d056bbea1e3d4c1cbbe23da Gerrit-Change-Number: 30698 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: TESTONLY:mb/asus/m4a785-m: Try making HT enumerate properly
by Arthur Heymans (Code Review) 06 Jan '19

06 Jan '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30696 Change subject: TESTONLY:mb/asus/m4a785-m: Try making HT enumerate properly ...................................................................... TESTONLY:mb/asus/m4a785-m: Try making HT enumerate properly Change-Id: If445ea2f1672916db3b8cca4f2e81b1567f10da1 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/asus/m4a785-m/Kconfig M src/mainboard/asus/m4a785-m/romstage.c 2 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/30696/1 diff --git a/src/mainboard/asus/m4a785-m/Kconfig b/src/mainboard/asus/m4a785-m/Kconfig index 22665ef..8dfba3d 100644 --- a/src/mainboard/asus/m4a785-m/Kconfig +++ b/src/mainboard/asus/m4a785-m/Kconfig @@ -39,14 +39,14 @@ int default 2 -config HT_CHAIN_END_UNITID_BASE - hex - default 0x1 - config HT_CHAIN_UNITID_BASE hex default 0x0 +config HT_CHAIN_END_UNITID_BASE + hex + default 0x20 + config IRQ_SLOT_COUNT int default 19 diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index 02c396f..a106832 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -251,7 +251,7 @@ } } #else - static const u8 swaplist[] = {0, 1, 0xFF, 0, 0xFF}; + static const u8 swaplist[] = {0, 0, 0xFF, 0, 0xFF}; /* If the BUID was adjusted in early_ht we need to do the manual override */ if ((node == 0) && (link == 0)) { /* BSP SB link */ *List = swaplist; -- To view, visit https://review.coreboot.org/c/coreboot/+/30696 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If445ea2f1672916db3b8cca4f2e81b1567f10da1 Gerrit-Change-Number: 30696 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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coreboot-gerrit January 2019