coreboot-gerrit January 2019

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Change in ...coreboot[master]: mb/google/sarien: Add PDR and RW_LEGACY_NVRAM to FMAP
by Duncan Laurie (Code Review) 08 Jan '19

08 Jan '19

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30755 Change subject: mb/google/sarien: Add PDR and RW_LEGACY_NVRAM to FMAP ...................................................................... mb/google/sarien: Add PDR and RW_LEGACY_NVRAM to FMAP 1) Add a Platform Data Region called SI_PDR which is allocated in the flash descriptor for this platform 2) Add a DIAG_NVRAM region for use by the diagnostic payload for non-volatile storage. 3) Encapsulate both RW_LEGACY and DIAG_NVRAM in a region called RW_DIAG so it is clear they are associated. 4) Move the RW_DIAG region to the start of the RW region so that once we can re-enable a larger BIOS region this sub-region will be in the uncached area since it is not accessed on a normal boot. BUG=b:119435206 TEST=tested on Arcada board to ensure expected regions are present Change-Id: Ieb8bc4cf70d0a931e4944210112cfaf5c543f9f3 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/mainboard/google/sarien/chromeos.fmd 1 file changed, 9 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/30755/1 diff --git a/src/mainboard/google/sarien/chromeos.fmd b/src/mainboard/google/sarien/chromeos.fmd index 6631769..ba42a6f 100644 --- a/src/mainboard/google/sarien/chromeos.fmd +++ b/src/mainboard/google/sarien/chromeos.fmd @@ -3,20 +3,25 @@ SI_DESC@0x0 0x1000 SI_EC@0x1000 0x100000 SI_GBE@0x101000 0x2000 - SI_ME@0x103000 0xefd000 + SI_ME@0x103000 0xef9000 + SI_PDR@0xffc000 0x4000 } SI_BIOS@0x1000000 0x1000000 { - RW_SECTION_A@0x0 0x280000 { + RW_DIAG@0x0 0x6d0000 { + DIAG_NVRAM@0x0 0x10000 + RW_LEGACY(CBFS)@0x10000 0x6c0000 + } + RW_SECTION_A@0x6d0000 0x280000 { VBLOCK_A@0x0 0x10000 FW_MAIN_A(CBFS)@0x10000 0x26ffc0 RW_FWID_A@0x27ffc0 0x40 } - RW_SECTION_B@0x280000 0x280000 { + RW_SECTION_B@0x950000 0x280000 { VBLOCK_B@0x0 0x10000 FW_MAIN_B(CBFS)@0x10000 0x26ffc0 RW_FWID_B@0x27ffc0 0x40 } - RW_MISC@0x500000 0x30000 { + RW_MISC@0xbd0000 0x30000 { UNIFIED_MRC_CACHE@0x0 0x20000 { RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 @@ -29,8 +34,6 @@ RW_VPD@0x28000 0x2000 RW_NVRAM@0x2a000 0x6000 } - CONSOLE@0x530000 0x20000 - RW_LEGACY(CBFS)@0x550000 0x6b0000 WP_RO@0xc00000 0x400000 { RO_VPD@0x0 0x4000 RO_UNUSED@0x4000 0xc000 -- To view, visit https://review.coreboot.org/c/coreboot/+/30755 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb8bc4cf70d0a931e4944210112cfaf5c543f9f3 Gerrit-Change-Number: 30755 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: drivers/intel/fsp1_1: Add stack guards
by Arthur Heymans (Code Review) 08 Jan '19

08 Jan '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30751 Change subject: drivers/intel/fsp1_1: Add stack guards ...................................................................... drivers/intel/fsp1_1: Add stack guards This allows to check if stack overflows the car globals. Change-Id: I369b2d846f35914facb3e69cc762f7e555271bec Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/intel/fsp1_1/car.c 1 file changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/30751/1 diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index 13161d6..63c5042 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -35,6 +35,21 @@ asmlinkage void *cache_as_ram_main(struct cache_as_ram_params *car_params) { + int i; + const int num_guards = 4; + const u32 stack_guard = 0xdeadbeef; + u32 *stack_base; + u32 size; + + /* Size of unallocated CAR. */ + size = _car_region_end - _car_relocatable_data_end; + size = ALIGN_DOWN(size, 16); + + stack_base = (u32 *) (_car_region_end - size); + + for (i = 0; i < num_guards; i++) + stack_base[i] = stack_guard; + /* Initialize timestamp book keeping only once. */ timestamp_init(car_params->tsc); @@ -63,6 +78,13 @@ set_fih_car(car_params->fih); + /* Check the stack. */ + for (i = 0; i < num_guards; i++) { + if (stack_base[i] == stack_guard) + continue; + printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n"); + } + /* Return new stack value in RAM back to assembly stub. */ return cache_as_ram_stage_main(car_params->fih); } -- To view, visit https://review.coreboot.org/c/coreboot/+/30751 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I369b2d846f35914facb3e69cc762f7e555271bec Gerrit-Change-Number: 30751 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb: Move timestamp_add_now to northbridge x4x
by HAOUAS Elyes (Code Review) 08 Jan '19

08 Jan '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30750 Change subject: mb: Move timestamp_add_now to northbridge x4x ...................................................................... mb: Move timestamp_add_now to northbridge x4x Change-Id: Iacbee658a4049e1c13a120dbc21425ffb6a1cabb Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/asrock/g41c-gs/romstage.c M src/mainboard/asus/p5qc/romstage.c M src/mainboard/asus/p5qpl-am/romstage.c M src/mainboard/foxconn/g41s-k/romstage.c M src/mainboard/gigabyte/ga-g41m-es2l/romstage.c M src/mainboard/intel/dg41wv/romstage.c M src/mainboard/intel/dg43gt/romstage.c M src/mainboard/lenovo/thinkcentre_a58/romstage.c M src/northbridge/intel/x4x/raminit.c 9 files changed, 4 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/30750/1 diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c index e5e1110..49bec34 100644 --- a/src/mainboard/asrock/g41c-gs/romstage.c +++ b/src/mainboard/asrock/g41c-gs/romstage.c @@ -109,12 +109,8 @@ if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) boot_path = BOOT_PATH_WARM_RESET; - printk(BIOS_DEBUG, "Initializing memory\n"); - timestamp_add_now(TS_BEFORE_INITRAM); sdram_initialize(boot_path, spd_addrmap); - timestamp_add_now(TS_AFTER_INITRAM); quick_ram_check(); - printk(BIOS_DEBUG, "Memory initialized\n"); x4x_late_init(s3_resume); diff --git a/src/mainboard/asus/p5qc/romstage.c b/src/mainboard/asus/p5qc/romstage.c index eb534ca..4f12187 100644 --- a/src/mainboard/asus/p5qc/romstage.c +++ b/src/mainboard/asus/p5qc/romstage.c @@ -94,12 +94,8 @@ if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) boot_path = BOOT_PATH_WARM_RESET; - printk(BIOS_DEBUG, "Initializing memory\n"); - timestamp_add_now(TS_BEFORE_INITRAM); sdram_initialize(boot_path, spd_addrmap); - timestamp_add_now(TS_AFTER_INITRAM); quick_ram_check(); - printk(BIOS_DEBUG, "Memory initialized\n"); x4x_late_init(s3_resume); diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c index 2c1b586..0078995 100644 --- a/src/mainboard/asus/p5qpl-am/romstage.c +++ b/src/mainboard/asus/p5qpl-am/romstage.c @@ -174,12 +174,8 @@ halt(); } - printk(BIOS_DEBUG, "Initializing memory\n"); - timestamp_add_now(TS_BEFORE_INITRAM); sdram_initialize(boot_path, spd_addrmap); - timestamp_add_now(TS_AFTER_INITRAM); quick_ram_check(); - printk(BIOS_DEBUG, "Memory initialized\n"); x4x_late_init(s3_resume); diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/romstage.c index a695c53..a866090 100644 --- a/src/mainboard/foxconn/g41s-k/romstage.c +++ b/src/mainboard/foxconn/g41s-k/romstage.c @@ -108,12 +108,8 @@ if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) boot_path = BOOT_PATH_WARM_RESET; - printk(BIOS_DEBUG, "Initializing memory\n"); - timestamp_add_now(TS_BEFORE_INITRAM); sdram_initialize(boot_path, spd_addrmap); - timestamp_add_now(TS_AFTER_INITRAM); quick_ram_check(); - printk(BIOS_DEBUG, "Memory initialized\n"); x4x_late_init(s3_resume); diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index 78be08b..e9ee4b5 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -156,12 +156,8 @@ if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) boot_path = BOOT_PATH_WARM_RESET; - printk(BIOS_DEBUG, "Initializing memory\n"); - timestamp_add_now(TS_BEFORE_INITRAM); sdram_initialize(boot_path, spd_addrmap); - timestamp_add_now(TS_AFTER_INITRAM); quick_ram_check(); - printk(BIOS_DEBUG, "Memory initialized\n"); x4x_late_init(s3_resume); diff --git a/src/mainboard/intel/dg41wv/romstage.c b/src/mainboard/intel/dg41wv/romstage.c index 830bc73..13b8dcb 100644 --- a/src/mainboard/intel/dg41wv/romstage.c +++ b/src/mainboard/intel/dg41wv/romstage.c @@ -103,12 +103,8 @@ if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) boot_path = BOOT_PATH_WARM_RESET; - printk(BIOS_DEBUG, "Initializing memory\n"); - timestamp_add_now(TS_BEFORE_INITRAM); sdram_initialize(boot_path, spd_addrmap); - timestamp_add_now(TS_AFTER_INITRAM); quick_ram_check(); - printk(BIOS_DEBUG, "Memory initialized\n"); x4x_late_init(s3_resume); diff --git a/src/mainboard/intel/dg43gt/romstage.c b/src/mainboard/intel/dg43gt/romstage.c index 36aa149..649fceb 100644 --- a/src/mainboard/intel/dg43gt/romstage.c +++ b/src/mainboard/intel/dg43gt/romstage.c @@ -96,12 +96,8 @@ if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) boot_path = BOOT_PATH_WARM_RESET; - printk(BIOS_DEBUG, "Initializing memory\n"); - timestamp_add_now(TS_BEFORE_INITRAM); sdram_initialize(boot_path, spd_addrmap); - timestamp_add_now(TS_AFTER_INITRAM); quick_ram_check(); - printk(BIOS_DEBUG, "Memory initialized\n"); x4x_late_init(s3_resume); diff --git a/src/mainboard/lenovo/thinkcentre_a58/romstage.c b/src/mainboard/lenovo/thinkcentre_a58/romstage.c index 6d0bc97..4ba4514 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/romstage.c +++ b/src/mainboard/lenovo/thinkcentre_a58/romstage.c @@ -89,12 +89,8 @@ if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) boot_path = BOOT_PATH_WARM_RESET; - printk(BIOS_DEBUG, "Initializing memory\n"); - timestamp_add_now(TS_BEFORE_INITRAM); sdram_initialize(boot_path, spd_addrmap); - timestamp_add_now(TS_AFTER_INITRAM); quick_ram_check(); - printk(BIOS_DEBUG, "Memory initialized\n"); x4x_late_init(s3_resume); diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index b3b84d8..7c1603a 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -34,6 +34,7 @@ #include <device/dram/ddr2.h> #include <device/dram/ddr3.h> #include <mrc_cache.h> +#include <timestamp.h> #define MRC_CACHE_VERSION 0 @@ -639,6 +640,7 @@ int fast_boot, cbmem_was_inited, cache_not_found; struct region_device rdev; + timestamp_add_now(TS_BEFORE_INITRAM); printk(BIOS_DEBUG, "Setting up RAM controller.\n"); pci_write_config8(PCI_DEV(0, 0, 0), 0xdf, 0xff); @@ -728,4 +730,6 @@ outb(0x6, 0xcf9); halt(); } + + timestamp_add_now(TS_AFTER_INITRAM); } -- To view, visit https://review.coreboot.org/c/coreboot/+/30750 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iacbee658a4049e1c13a120dbc21425ffb6a1cabb Gerrit-Change-Number: 30750 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: cpu/Kconfig: hide CPU_MICROCODE_CBFS_GENERATE if no SUPPORT_CPU_UCODE...
by mikeb mikeb (Code Review) 08 Jan '19

08 Jan '19

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30748 to review the following change. Change subject: cpu/Kconfig: hide CPU_MICROCODE_CBFS_GENERATE if no SUPPORT_CPU_UCODE_IN_CBFS ...................................................................... cpu/Kconfig: hide CPU_MICROCODE_CBFS_GENERATE if no SUPPORT_CPU_UCODE_IN_CBFS Trying to use CPU_MICROCODE_CBFS_GENERATE microcode update option for a board which does not support it - could lead to not-obvious problems. For example: if someone tries to use this option e.g. for Lenovo G505S which does not belong to CPU_AMD_MODEL_10XXX (f10h-f15h) group of the only AMD boards supporting it, then CB will be built successfully but the microcode blob will occupy 0 size at CBFS, which would result in worse outcome than if CPU_MICROCODE_CBFS_NONE is selected. So CPU_MICROCODE_CBFS_GENERATE should be hidden for the not-supporting boards. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I5e4654b14a0c14a25bd6aa62c71ed1d51a7aec03 --- M src/cpu/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/30748/1 diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index a7cb99e..59c8e23 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -92,6 +92,7 @@ config CPU_MICROCODE_CBFS_GENERATE bool "Generate from tree" + depends on SUPPORT_CPU_UCODE_IN_CBFS help Select this option if you want microcode updates to be assembled when building coreboot and included in the final image as a separate CBFS -- To view, visit https://review.coreboot.org/c/coreboot/+/30748 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e4654b14a0c14a25bd6aa62c71ed1d51a7aec03 Gerrit-Change-Number: 30748 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: arch/x86/Kconfig: Fix spelling of *successful*
by Paul Menzel (Code Review) 08 Jan '19

08 Jan '19

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30745 Change subject: arch/x86/Kconfig: Fix spelling of *successful* ...................................................................... arch/x86/Kconfig: Fix spelling of *successful* Change-Id: If0da91cf94aa12fe7b8670f6b181e443e3446aa1 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/arch/x86/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/30745/1 diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 794ea11..242a7cf 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -263,7 +263,7 @@ Do not clear the reboot count immediately after successful boot. Set to allow the payload to control normal/fallback image recovery. Note that it is the responsibility of the payload to reset the - normal boot bit to 1 after each successsful boot. + normal boot bit to 1 after each successful boot. config ACPI_CPU_STRING string -- To view, visit https://review.coreboot.org/c/coreboot/+/30745 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0da91cf94aa12fe7b8670f6b181e443e3446aa1 Gerrit-Change-Number: 30745 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: driver/spi/eon.c: Add the rest of >=1MB EON EN25 chips
by mikeb mikeb (Code Review) 08 Jan '19

08 Jan '19

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30744 to review the following change. Change subject: driver/spi/eon.c: Add the rest of >=1MB EON EN25 chips ...................................................................... driver/spi/eon.c: Add the rest of >=1MB EON EN25 chips Required for hybernation support at some motherboards, e.g. EN25QH32 chip entry for AMD Lenovo G505S laptop. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I8343a1741be5ea294de0773962c021428815934c --- M src/drivers/spi/eon.c 1 file changed, 167 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/30744/1 diff --git a/src/drivers/spi/eon.c b/src/drivers/spi/eon.c index 4cb5697..9c3a0db 100644 --- a/src/drivers/spi/eon.c +++ b/src/drivers/spi/eon.c @@ -27,10 +27,27 @@ #define CMD_EN25_DP 0xb9 /* Deep Power-down */ #define CMD_EN25_RES 0xab /* Release from DP, and Read Signature */ -#define EON_ID_EN25Q128 0x3018 -#define EON_ID_EN25Q64 0x3017 -#define EON_ID_EN25S64 0x3817 +#define EON_ID_EN25B80 0x2014 +#define EON_ID_EN25B16 0x2015 +#define EON_ID_EN25B32 0x2016 +#define EON_ID_EN25B64 0x2017 #define EON_ID_EN25F80 0x3114 +#define EON_ID_EN25F16 0x3115 +#define EON_ID_EN25F32 0x3116 +#define EON_ID_EN25F64 0x3117 +#define EON_ID_EN25Q80 0x3014 +#define EON_ID_EN25Q16 0x3015 /* Same as EN25D16 */ +#define EON_ID_EN25Q32 0x3016 /* Same as EN25Q32A and EN25Q32B */ +#define EON_ID_EN25Q64 0x3017 +#define EON_ID_EN25Q128 0x3018 +#define EON_ID_EN25QH16 0x7015 +#define EON_ID_EN25QH32 0x7016 +#define EON_ID_EN25QH64 0x7017 +#define EON_ID_EN25QH128 0x7018 +#define EON_ID_EN25S80 0x3814 +#define EON_ID_EN25S16 0x3815 +#define EON_ID_EN25S32 0x3816 +#define EON_ID_EN25S64 0x3817 struct eon_spi_flash_params { u16 id; @@ -43,12 +60,92 @@ static const struct eon_spi_flash_params eon_spi_flash_table[] = { { - .id = EON_ID_EN25Q128, + .id = EON_ID_EN25B80, .page_size = 256, .pages_per_sector = 16, .sectors_per_block = 16, - .nr_sectors = 4096, - .name = "EN25Q128", + .nr_sectors = 256, + .name = "EN25B80", + }, + { + .id = EON_ID_EN25B16, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_sectors = 512, + .name = "EN25B16", + }, + { + .id = EON_ID_EN25B32, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_sectors = 1024, + .name = "EN25B32", + }, + { + .id = EON_ID_EN25B64, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_sectors = 2048, + .name = "EN25B64", + }, + { + .id = EON_ID_EN25F80, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_sectors = 256, + .name = "EN25F80", + }, + { + .id = EON_ID_EN25F16, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_sectors = 512, + .name = "EN25F16", + }, + { + .id = EON_ID_EN25F32, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_sectors = 1024, + .name = "EN25F32", + }, + { + .id = EON_ID_EN25F64, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_sectors = 2048, + .name = "EN25F64", + }, + { + .id = EON_ID_EN25Q80, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_sectors = 256, + .name = "EN25Q80(A)", + }, + { + .id = EON_ID_EN25Q16, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_sectors = 512, + .name = "EN25Q16", + }, + { + .id = EON_ID_EN25Q32, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_sectors = 1024, + .name = "EN25Q32(A/B)", }, { .id = EON_ID_EN25Q64, @@ -59,6 +156,70 @@ .name = "EN25Q64", }, { + .id = EON_ID_EN25Q128, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_sectors = 4096, + .name = "EN25Q128", + }, + { + .id = EON_ID_EN25QH16, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_sectors = 512, + .name = "EN25QH16", + }, + { + .id = EON_ID_EN25QH32, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_sectors = 1024, + .name = "EN25QH32", + }, + { + .id = EON_ID_EN25QH64, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_sectors = 2048, + .name = "EN25QH64", + }, + { + .id = EON_ID_EN25QH128, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_sectors = 4096, + .name = "EN25QH128", + }, + { + .id = EON_ID_EN25S80, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_sectors = 256, + .name = "EN25S80", + }, + { + .id = EON_ID_EN25S16, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_sectors = 512, + .name = "EN25S16", + }, + { + .id = EON_ID_EN25S32, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_sectors = 1024, + .name = "EN25S32", + }, + { .id = EON_ID_EN25S64, .page_size = 256, .pages_per_sector = 16, @@ -66,14 +227,6 @@ .nr_sectors = 2048, .name = "EN25S64", }, - { - .id = EON_ID_EN25F80, - .page_size = 256, - .pages_per_sector = 16, - .sectors_per_block = 16, - .nr_sectors = 256, - .name = "EN25F80", - }, }; static int eon_write(const struct spi_flash *flash, -- To view, visit https://review.coreboot.org/c/coreboot/+/30744 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8343a1741be5ea294de0773962c021428815934c Gerrit-Change-Number: 30744 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: soc/intel/fsp_broadwell_de/vtd: Silence warning
by Patrick Rudolph (Code Review) 08 Jan '19

08 Jan '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30743 Change subject: soc/intel/fsp_broadwell_de/vtd: Silence warning ...................................................................... soc/intel/fsp_broadwell_de/vtd: Silence warning Silence PCI resource warning due to missing set_resources. Change-Id: I8253e9ca137bda1cdd1c06273679693c4b7803ec Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/fsp_broadwell_de/vtd.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/30743/1 diff --git a/src/soc/intel/fsp_broadwell_de/vtd.c b/src/soc/intel/fsp_broadwell_de/vtd.c index e584cfa..8f6b278 100644 --- a/src/soc/intel/fsp_broadwell_de/vtd.c +++ b/src/soc/intel/fsp_broadwell_de/vtd.c @@ -34,6 +34,7 @@ static struct device_operations vtd_ops = { .read_resources = vtd_read_resources, + .set_resources = DEVICE_NOOP, .write_acpi_tables = vtd_write_acpi_tables, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/30743 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8253e9ca137bda1cdd1c06273679693c4b7803ec Gerrit-Change-Number: 30743 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: amdfam10 boards: Use smp_write_pci_intsrc()
by Kyösti Mälkki (Code Review) 08 Jan '19

08 Jan '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30739 Change subject: amdfam10 boards: Use smp_write_pci_intsrc() ...................................................................... amdfam10 boards: Use smp_write_pci_intsrc() Radically reduces line lengths and splits '(bus<<2) | INT' to separate parameters. Change-Id: I6c924a70d00a9139719f8078bbf1e4d04b576324 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/amd/serengeti_cheetah_fam10/mptable.c M src/mainboard/asus/kfsn4-dre/mptable.c M src/mainboard/hp/dl165_g6_fam10/mptable.c M src/mainboard/msi/ms9652_fam10/mptable.c M src/mainboard/supermicro/h8dmr_fam10/mptable.c M src/mainboard/supermicro/h8qme_fam10/mptable.c M src/mainboard/supermicro/h8scm_fam10/mptable.c M src/mainboard/tyan/s2912_fam10/mptable.c 8 files changed, 83 insertions(+), 83 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/30739/1 diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c index 1ab3ad2..bf3dc9d 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c @@ -98,32 +98,32 @@ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ /* ??? What */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13); + smp_write_pci_intsrc(mc, mp_INT, m->bus_8111_0, sysconf.sbdn+1, 3, m->apicid_8111, 0x13); /* Onboard AMD USB */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0 << 2)|3, m->apicid_8111, 0x13); + smp_write_pci_intsrc(mc, mp_INT, m->bus_8111_1, 0, 3, m->apicid_8111, 0x13); /* Slot 3 PCI 32 */ for (i = 0; i < 4; i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5 << 2)|i, m->apicid_8111, 0x10 + (1+i)%4); /* 16 */ + smp_write_pci_intsrc(mc, mp_INT, m->bus_8111_1, 5, i, m->apicid_8111, 0x10 + (1+i)%4); /* 16 */ } /* Slot 4 PCI 32 */ for (i = 0; i < 4; i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4 << 2)|i, m->apicid_8111, 0x10 + (0+i)%4); /* 16 */ + smp_write_pci_intsrc(mc, mp_INT, m->bus_8111_1, 4, i, m->apicid_8111, 0x10 + (0+i)%4); /* 16 */ } /* Slot 1 PCI-X 133/100/66 */ for (i = 0; i < 4; i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1 << 2)|i, m->apicid_8132_2, (0+i)%4); + smp_write_pci_intsrc(mc, mp_INT, m->bus_8132_2, 1, i, m->apicid_8132_2, (0+i)%4); } /* Slot 2 PCI-X 133/100/66 */ for (i = 0; i < 4; i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1 << 2)|i, m->apicid_8132_1, (1+i)%4); /* 25 */ + smp_write_pci_intsrc(mc, mp_INT, m->bus_8132_1, 1, i, m->apicid_8132_1, (1+i)%4); /* 25 */ } j = 0; @@ -145,7 +145,7 @@ for (jj = 0; jj < 4; jj++) { /* Slot 1 PCI-X 133/100/66 */ for (ii = 0; ii < 4; ii++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (jj << 2)|ii, m->apicid_8132a[j][0], (jj+ii)%4); + smp_write_pci_intsrc(mc, mp_INT, m->bus_8132a[j][1], jj, ii, m->apicid_8132a[j][0], (jj+ii)%4); } } } @@ -158,7 +158,7 @@ for (jj = 0; jj < 4; jj++) { /* Slot 2 PCI-X 133/100/66 */ for (ii = 0; ii < 4; ii++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (jj << 2)|ii, m->apicid_8132a[j][1], (jj+ii)%4); /* 25 */ + smp_write_pci_intsrc(mc, mp_INT, m->bus_8132a[j][2], jj, ii, m->apicid_8132a[j][1], (jj+ii)%4); /* 25 */ } } } @@ -168,7 +168,7 @@ case 2: /* Slot AGP */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151[j][1], 0x0, m->apicid_8111, 0x11); + smp_write_pci_intsrc(mc, mp_INT, m->bus_8151[j][1], 0x0, m->apicid_8111, 0x11); break; } diff --git a/src/mainboard/asus/kfsn4-dre/mptable.c b/src/mainboard/asus/kfsn4-dre/mptable.c index 387baa4..69ea301 100644 --- a/src/mainboard/asus/kfsn4-dre/mptable.c +++ b/src/mainboard/asus/kfsn4-dre/mptable.c @@ -111,28 +111,28 @@ mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 0); // Onboard ck804 smbus - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - bus_ck804[0], ((sbdn + 1) << 2) | 1, apicid_ck804, + smp_write_pci_intsrc(mc, mp_INT, + bus_ck804[0], sbdn + 1, 1, apicid_ck804, 0xa); // Onboard ck804 USB 1.1 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - bus_ck804[0], ((sbdn + 2) << 2) | 0, apicid_ck804, + smp_write_pci_intsrc(mc, mp_INT, + bus_ck804[0], sbdn + 2, 0, apicid_ck804, 0x15); // Onboard ck804 USB 2 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - bus_ck804[0], ((sbdn + 2) << 2) | 1, apicid_ck804, + smp_write_pci_intsrc(mc, mp_INT, + bus_ck804[0], sbdn + 2, 1, apicid_ck804, 0x14); // Onboard ck804 SATA 0 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - bus_ck804[0], ((sbdn + 7) << 2) | 0, apicid_ck804, + smp_write_pci_intsrc(mc, mp_INT, + bus_ck804[0], sbdn + 7, 0, apicid_ck804, 0x17); // Onboard ck804 SATA 1 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - bus_ck804[0], ((sbdn + 8) << 2) | 0, apicid_ck804, + smp_write_pci_intsrc(mc, mp_INT, + bus_ck804[0], sbdn + 8, 0, apicid_ck804, 0x16); /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ diff --git a/src/mainboard/hp/dl165_g6_fam10/mptable.c b/src/mainboard/hp/dl165_g6_fam10/mptable.c index 9e5976f..6c9a001 100644 --- a/src/mainboard/hp/dl165_g6_fam10/mptable.c +++ b/src/mainboard/hp/dl165_g6_fam10/mptable.c @@ -112,16 +112,16 @@ mptable_add_isa_interrupts(mc, isa_bus, m->apicid_bcm5785[0], 0); /* I/O Ints: Type Polarity/Trigger Bus ID IRQ APIC ID PIN# */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0xe << 2)|0, m->apicid_bcm5785[0], 0x5); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x3 << 2)|0, m->apicid_bcm5785[0], 0xa); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x6 << 2)|0, m->apicid_bcm5785[2], 0x4); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x7 << 2)|0, m->apicid_bcm5785[2], 0x3); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x8 << 2)|0, m->apicid_bcm5785[2], 0x2); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x9 << 2)|0, m->apicid_bcm5785[2], 0x1); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0xa << 2)|0, m->apicid_bcm5785[2], 0x0); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (0x2 << 2)|0, m->apicid_bcm5785[2], 0x8); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (0x2 << 2)|1, m->apicid_bcm5785[2], 0x7); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[5], (0x0 << 2)|0, m->apicid_bcm5785[2], 0xa); + smp_write_pci_intsrc(mc, mp_INT, m->bus_bcm5785_1, 0xe, 0, m->apicid_bcm5785[0], 0x5); + smp_write_pci_intsrc(mc, mp_INT, m->bus_bcm5785_0, 0x3, 0, m->apicid_bcm5785[0], 0xa); + smp_write_pci_intsrc(mc, mp_INT, m->bus_bcm5785_0, 0x6, 0, m->apicid_bcm5785[2], 0x4); + smp_write_pci_intsrc(mc, mp_INT, m->bus_bcm5785_0, 0x7, 0, m->apicid_bcm5785[2], 0x3); + smp_write_pci_intsrc(mc, mp_INT, m->bus_bcm5785_0, 0x8, 0, m->apicid_bcm5785[2], 0x2); + smp_write_pci_intsrc(mc, mp_INT, m->bus_bcm5785_0, 0x9, 0, m->apicid_bcm5785[2], 0x1); + smp_write_pci_intsrc(mc, mp_INT, m->bus_bcm5785_0, 0xa, 0, m->apicid_bcm5785[2], 0x0); + smp_write_pci_intsrc(mc, mp_INT, m->bus_bcm5785_1_1, 0x2, 0, m->apicid_bcm5785[2], 0x8); + smp_write_pci_intsrc(mc, mp_INT, m->bus_bcm5785_1_1, 0x2, 1, m->apicid_bcm5785[2], 0x7); + smp_write_pci_intsrc(mc, mp_INT, m->bus_bcm5780[5], 0x0, 0, m->apicid_bcm5785[2], 0xa); /* enable int */ /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/ diff --git a/src/mainboard/msi/ms9652_fam10/mptable.c b/src/mainboard/msi/ms9652_fam10/mptable.c index 8cf5b3d..63816dc 100644 --- a/src/mainboard/msi/ms9652_fam10/mptable.c +++ b/src/mainboard/msi/ms9652_fam10/mptable.c @@ -71,31 +71,31 @@ mptable_add_isa_interrupts(mc, bus_isa, m->apicid_mcp55, 0); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa); + smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 1, 1, m->apicid_mcp55, 0xa); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|0, m->apicid_mcp55, 0x16); // 22 + smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 2, 0, m->apicid_mcp55, 0x16); // 22) - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|1, m->apicid_mcp55, 0x17); // 23 + smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 2, 1, m->apicid_mcp55, 0x17); // 23) - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+6)<<2)|1, m->apicid_mcp55, 0x17); // 23 + smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 6, 1, m->apicid_mcp55, 0x17); // 23) - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x14); // 20 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|1, m->apicid_mcp55, 0x17); // 23 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|2, m->apicid_mcp55, 0x15); // 21 + smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 5, 0, m->apicid_mcp55, 0x14); // 20) + smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 5, 1, m->apicid_mcp55, 0x17); // 23) + smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 5, 2, m->apicid_mcp55, 0x15); // 21) - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21 + smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 8, 0, m->apicid_mcp55, 0x16); // 22) + smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 9, 0, m->apicid_mcp55, 0x15); // 21) for (j = 7; j >= 2; j--) { if (!m->bus_mcp55[j]) continue; for (i = 0; i < 4; i++) - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00 << 2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); + smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[j], 0x00, i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); } for (j = 0; j < 1; j++) for (i = 0; i < 4; i++) - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x04+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4); + smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[1], 0x04+j, i, m->apicid_mcp55, 0x10 + (2+i+j)%4); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ mptable_lintsrc(mc, bus_isa); diff --git a/src/mainboard/supermicro/h8dmr_fam10/mptable.c b/src/mainboard/supermicro/h8dmr_fam10/mptable.c index 16a3420..9065965 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/mptable.c +++ b/src/mainboard/supermicro/h8dmr_fam10/mptable.c @@ -71,31 +71,31 @@ mptable_add_isa_interrupts(mc, bus_isa, m->apicid_mcp55, 0); /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa); + smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 1, 1, m->apicid_mcp55, 0xa); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|0, m->apicid_mcp55, 0x16); // 22 + smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 2, 0, m->apicid_mcp55, 0x16); // 22) - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|1, m->apicid_mcp55, 0x17); // 23 + smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 2, 1, m->apicid_mcp55, 0x17); // 23) - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+6)<<2)|1, m->apicid_mcp55, 0x17); // 23 + smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 6, 1, m->apicid_mcp55, 0x17); // 23) - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x14); // 20 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|1, m->apicid_mcp55, 0x17); // 23 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|2, m->apicid_mcp55, 0x15); // 21 + smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 5, 0, m->apicid_mcp55, 0x14); // 20) + smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 5, 1, m->apicid_mcp55, 0x17); // 23) + smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 5, 2, m->apicid_mcp55, 0x15); // 21) - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21 + smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 8, 0, m->apicid_mcp55, 0x16); // 22) + smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 9, 0, m->apicid_mcp55, 0x15); // 21) for(j = 7; j >= 2; j--) { if(!m->bus_mcp55[j]) continue; for(i = 0; i < 4; i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00 << 2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); + smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[j], 0x00, i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); } } for(j = 0; j < 1; j++) for(i = 0; i < 4; i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x04+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4); + smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[1], 0x04+j, i, m->apicid_mcp55, 0x10 + (2+i+j)%4); } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ diff --git a/src/mainboard/supermicro/h8qme_fam10/mptable.c b/src/mainboard/supermicro/h8qme_fam10/mptable.c index 616e6a8..81c0c1a 100644 --- a/src/mainboard/supermicro/h8qme_fam10/mptable.c +++ b/src/mainboard/supermicro/h8qme_fam10/mptable.c @@ -73,27 +73,27 @@ mptable_add_isa_interrupts(mc, bus_isa, m->apicid_mcp55, 0); /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0x5); /* 5 SMBus, OK */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|0, m->apicid_mcp55, 0xb); /* 11 USB, OK */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|1, m->apicid_mcp55, 0xa); /* 10 USB, OK */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x5); /* 5 IDE, OK*/ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|1, m->apicid_mcp55, 0xa); /* 10 IDE, OK*/ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|2, m->apicid_mcp55, 0xa); /* 10 IDE, OK*/ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+6)<<2)|1, m->apicid_mcp55, 0xa); /* 10 VGA, OK*/ + smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 1, 1, m->apicid_mcp55, 0x5); /* 5 SMBus, OK */ + smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 2, 0, m->apicid_mcp55, 0xb); /* 11 USB, OK */ + smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 2, 1, m->apicid_mcp55, 0xa); /* 10 USB, OK */ + smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 5, 0, m->apicid_mcp55, 0x5); /* 5 IDE, OK*/ + smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 5, 1, m->apicid_mcp55, 0xa); /* 10 IDE, OK*/ + smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 5, 2, m->apicid_mcp55, 0xa); /* 10 IDE, OK*/ + smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 6, 1, m->apicid_mcp55, 0xa); /* 10 VGA, OK*/ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, ((3)<<2)|0, m->apicid_mcp55, 0x5); /* 5 eth0, OK*/ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, ((3)<<2)|1, m->apicid_mcp55, 0xb); /* 11 eth1, OK*/ + smp_write_pci_intsrc(mc, mp_INT, m->bus_8132_2, 3, 0, m->apicid_mcp55, 0x5); /* 5 eth0, OK*/ + smp_write_pci_intsrc(mc, mp_INT, m->bus_8132_2, 3, 1, m->apicid_mcp55, 0xb); /* 11 eth1, OK*/ for(j = 7;j >= 2; j--) { if(!m->bus_mcp55[j]) continue; for(i = 0; i < 4; i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00 << 2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); + smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[j], 0x00, i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); } } for(j = 0; j < 1; j++) for(i = 0; i < 4; i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x04+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4); + smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[1], 0x04+j, i, m->apicid_mcp55, 0x10 + (2+i+j)%4); } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ diff --git a/src/mainboard/supermicro/h8scm_fam10/mptable.c b/src/mainboard/supermicro/h8scm_fam10/mptable.c index db593ca..22f064a 100644 --- a/src/mainboard/supermicro/h8scm_fam10/mptable.c +++ b/src/mainboard/supermicro/h8scm_fam10/mptable.c @@ -103,18 +103,18 @@ * PCI_INT(bus_sr5650[0x6], 0x0, 0x0, 0x12); * PCI_INT(bus_sr5650[0x7], 0x0, 0x0, 0x13); */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((2)<<2)|(0)), apicid_sr5650, 28); /* dev 2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((4)<<2)|(0)), apicid_sr5650, 28); /* dev 4 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((12)<<2)|(0)), apicid_sr5650, 30); /* dev 11 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((12)<<2)|(0)), apicid_sr5650, 30); /* dev 12 */ + smp_write_pci_intsrc(mc, mp_INT, 0, 2, 0, apicid_sr5650, 28); /* dev 2 */ + smp_write_pci_intsrc(mc, mp_INT, 0, 4, 0, apicid_sr5650, 28); /* dev 4 */ + smp_write_pci_intsrc(mc, mp_INT, 0, 12, 0, apicid_sr5650, 30); /* dev 11 */ + smp_write_pci_intsrc(mc, mp_INT, 0, 12, 0, apicid_sr5650, 30); /* dev 12 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[2], (((0)<<2)|(0)), apicid_sr5650, 0); /* card behind dev2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[4], (((0)<<2)|(0)), apicid_sr5650, 20); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[4], (((0)<<2)|(1)), apicid_sr5650, 21); /* NIC */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[11], (((0)<<2)|(0)), apicid_sr5650, 8); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[11], (((0)<<2)|(1)), apicid_sr5650, 9); /* card behind dev11 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[12], (((0)<<2)|(0)), apicid_sr5650, 12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[12], (((0)<<2)|(1)), apicid_sr5650, 13); /* card behind dev12 */ + smp_write_pci_intsrc(mc, mp_INT, bus_sr5650[2], 0, 0, apicid_sr5650, 0); /* card behind dev2 */ + smp_write_pci_intsrc(mc, mp_INT, bus_sr5650[4], 0, 0, apicid_sr5650, 20); + smp_write_pci_intsrc(mc, mp_INT, bus_sr5650[4], 0, 1, apicid_sr5650, 21); /* NIC */ + smp_write_pci_intsrc(mc, mp_INT, bus_sr5650[11], 0, 0, apicid_sr5650, 8); + smp_write_pci_intsrc(mc, mp_INT, bus_sr5650[11], 0, 1, apicid_sr5650, 9); /* card behind dev11 */ + smp_write_pci_intsrc(mc, mp_INT, bus_sr5650[12], 0, 0, apicid_sr5650, 12); + smp_write_pci_intsrc(mc, mp_INT, bus_sr5650[12], 0, 1, apicid_sr5650, 13); /* card behind dev12 */ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); diff --git a/src/mainboard/tyan/s2912_fam10/mptable.c b/src/mainboard/tyan/s2912_fam10/mptable.c index 3b77689..928feb3 100644 --- a/src/mainboard/tyan/s2912_fam10/mptable.c +++ b/src/mainboard/tyan/s2912_fam10/mptable.c @@ -71,29 +71,29 @@ mptable_add_isa_interrupts(mc, bus_isa, m->apicid_mcp55, 0); /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa); + smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 1, 1, m->apicid_mcp55, 0xa); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|0, m->apicid_mcp55, 0x16); // 22 + smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 2, 0, m->apicid_mcp55, 0x16); // 22) - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|1, m->apicid_mcp55, 0x17); // 23 + smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 2, 1, m->apicid_mcp55, 0x17); // 23) - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x14); // 20 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|1, m->apicid_mcp55, 0x17); // 23 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|2, m->apicid_mcp55, 0x15); // 21 + smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 5, 0, m->apicid_mcp55, 0x14); // 20) + smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 5, 1, m->apicid_mcp55, 0x17); // 23) + smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 5, 2, m->apicid_mcp55, 0x15); // 21) - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21 + smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 8, 0, m->apicid_mcp55, 0x16); // 22) + smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 9, 0, m->apicid_mcp55, 0x15); // 21) for(j = 7; j >= 2; j--) { if(!m->bus_mcp55[j]) continue; for(i = 0; i < 4; i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00 << 2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); + smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[j], 0x00, i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); } } for(j = 0; j < 1; j++) for(i = 0; i < 4; i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x04+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4); + smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[1], 0x04+j, i, m->apicid_mcp55, 0x10 + (2+i+j)%4); } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ -- To view, visit https://review.coreboot.org/c/coreboot/+/30739 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c924a70d00a9139719f8078bbf1e4d04b576324 Gerrit-Change-Number: 30739 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: mainboard/h8scm_fam10: Use apicid_sr5650
by Kyösti Mälkki (Code Review) 08 Jan '19

08 Jan '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30738 Change subject: mainboard/h8scm_fam10: Use apicid_sr5650 ...................................................................... mainboard/h8scm_fam10: Use apicid_sr5650 Do this for consistency and to ease further bulk-sed work on those lines. Change-Id: Ic9706de4278d163d1ba0c0706ec5d4c6c87ffa45 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/supermicro/h8scm_fam10/mptable.c 1 file changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/30738/1 diff --git a/src/mainboard/supermicro/h8scm_fam10/mptable.c b/src/mainboard/supermicro/h8scm_fam10/mptable.c index 4715be9..db593ca 100644 --- a/src/mainboard/supermicro/h8scm_fam10/mptable.c +++ b/src/mainboard/supermicro/h8scm_fam10/mptable.c @@ -86,7 +86,7 @@ if (dev) { pci_write_config32(dev, 0xF8, 0x1); dword = (u32 *)(pci_read_config32(dev, 0xFC) & 0xfffffff0); - smp_write_ioapic(mc, apicid_sp5100+1, 0x11, dword); + smp_write_ioapic(mc, apicid_sr5650, 0x11, dword); } } @@ -103,18 +103,18 @@ * PCI_INT(bus_sr5650[0x6], 0x0, 0x0, 0x12); * PCI_INT(bus_sr5650[0x7], 0x0, 0x0, 0x13); */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((2)<<2)|(0)), apicid_sp5100+1, 28); /* dev 2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((4)<<2)|(0)), apicid_sp5100+1, 28); /* dev 4 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((12)<<2)|(0)), apicid_sp5100+1, 30); /* dev 11 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((12)<<2)|(0)), apicid_sp5100+1, 30); /* dev 12 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((2)<<2)|(0)), apicid_sr5650, 28); /* dev 2 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((4)<<2)|(0)), apicid_sr5650, 28); /* dev 4 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((12)<<2)|(0)), apicid_sr5650, 30); /* dev 11 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((12)<<2)|(0)), apicid_sr5650, 30); /* dev 12 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[2], (((0)<<2)|(0)), apicid_sp5100+1, 0); /* card behind dev2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[4], (((0)<<2)|(0)), apicid_sp5100+1, 20); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[4], (((0)<<2)|(1)), apicid_sp5100+1, 21); /* NIC */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[11], (((0)<<2)|(0)), apicid_sp5100+1, 8); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[11], (((0)<<2)|(1)), apicid_sp5100+1, 9); /* card behind dev11 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[12], (((0)<<2)|(0)), apicid_sp5100+1, 12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[12], (((0)<<2)|(1)), apicid_sp5100+1, 13); /* card behind dev12 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[2], (((0)<<2)|(0)), apicid_sr5650, 0); /* card behind dev2 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[4], (((0)<<2)|(0)), apicid_sr5650, 20); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[4], (((0)<<2)|(1)), apicid_sr5650, 21); /* NIC */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[11], (((0)<<2)|(0)), apicid_sr5650, 8); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[11], (((0)<<2)|(1)), apicid_sr5650, 9); /* card behind dev11 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[12], (((0)<<2)|(0)), apicid_sr5650, 12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[12], (((0)<<2)|(1)), apicid_sr5650, 13); /* card behind dev12 */ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); -- To view, visit https://review.coreboot.org/c/coreboot/+/30738 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9706de4278d163d1ba0c0706ec5d4c6c87ffa45 Gerrit-Change-Number: 30738 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: amdfam10 boards: Use PCI_DEVFN()
by Kyösti Mälkki (Code Review) 08 Jan '19

08 Jan '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30737 Change subject: amdfam10 boards: Use PCI_DEVFN() ...................................................................... amdfam10 boards: Use PCI_DEVFN() Change-Id: I7b9aeaaa1cfa20efc9d187d91ece4eb9ee659c3f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/asus/kfsn4-dre/irq_tables.c M src/mainboard/msi/ms9652_fam10/irq_tables.c M src/mainboard/supermicro/h8dmr_fam10/irq_tables.c M src/mainboard/supermicro/h8qme_fam10/irq_tables.c M src/mainboard/tyan/s2912_fam10/irq_tables.c 5 files changed, 30 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/30737/1 diff --git a/src/mainboard/asus/kfsn4-dre/irq_tables.c b/src/mainboard/asus/kfsn4-dre/irq_tables.c index a5dc965..c1bd305 100644 --- a/src/mainboard/asus/kfsn4-dre/irq_tables.c +++ b/src/mainboard/asus/kfsn4-dre/irq_tables.c @@ -83,7 +83,7 @@ pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; pirq->rtr_bus = bus_ck804[0]; - pirq->rtr_devfn = ((sbdn + 9) << 3) | 0; + pirq->rtr_devfn = PCI_DEVFN(sbdn + 9, 0); pirq->exclusive_irqs = 0x828; pirq->rtr_vendor = 0x10de; pirq->rtr_device = 0x005c; @@ -95,26 +95,26 @@ slot_num = 0; /* Slot1 PCIE 16x */ - write_pirq_info(pirq_info, bus_ck804[1], (0 << 3) | 0, 0x3, 0xdeb8, 0x4, + write_pirq_info(pirq_info, bus_ck804[1], PCI_DEVFN(0, 0), 0x3, 0xdeb8, 0x4, 0xdeb8, 0x1, 0xdeb8, 0x2, 0xdeb8, 4, 0); pirq_info++; slot_num++; /* Slot2 PCIE 1x */ - write_pirq_info(pirq_info, bus_ck804[2], (0 << 3) | 0, 0x4, 0xdeb8, 0x1, + write_pirq_info(pirq_info, bus_ck804[2], PCI_DEVFN(0, 0), 0x4, 0xdeb8, 0x1, 0xdeb8, 0x2, 0xdeb8, 0x3, 0xdeb8, 5, 0); pirq_info++; slot_num++; /* Slot3 PCIE 1x */ - write_pirq_info(pirq_info, bus_ck804[3], (0 << 3) | 0, 0x1, 0xdeb8, 0x2, + write_pirq_info(pirq_info, bus_ck804[3], PCI_DEVFN(0, 0), 0x1, 0xdeb8, 0x2, 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 6, 0); pirq_info++; slot_num++; /* Slot4 PCIE 4x */ - write_pirq_info(pirq_info, bus_ck804[4], (0x4 << 3) | 0, 0x2, + write_pirq_info(pirq_info, bus_ck804[4], PCI_DEVFN(0x4, 0), 0x2, 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 0x1, 0xdeb8, 7, 0); pirq_info++; slot_num++; @@ -131,31 +131,31 @@ } /* PCI bridge */ - write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 9) << 3) | 0, 0x1, + write_pirq_info(pirq_info, bus_ck804[0], PCI_DEVFN(sbdn + 9, 0), 0x1, 0xdeb8, 0x2, 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 0, 0); pirq_info++; slot_num++; /* SMBus */ - write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 1) << 3) | 0, 0x2, + write_pirq_info(pirq_info, bus_ck804[0], PCI_DEVFN(sbdn + 1, 0), 0x2, 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0); pirq_info++; slot_num++; /* USB */ - write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 2) << 3) | 0, 0x1, + write_pirq_info(pirq_info, bus_ck804[0], PCI_DEVFN(sbdn + 2, 0), 0x1, 0xdeb8, 0x2, 0xdeb8, 0, 0, 0, 0, 0, 0); pirq_info++; slot_num++; /* SATA */ - write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 7) << 3) | 0, 0x1, + write_pirq_info(pirq_info, bus_ck804[0], PCI_DEVFN(sbdn + 7, 0), 0x1, 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0); pirq_info++; slot_num++; /* SATA */ - write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 8) << 3) | 0, 0x1, + write_pirq_info(pirq_info, bus_ck804[0], PCI_DEVFN(sbdn + 8, 0), 0x1, 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0); pirq_info++; slot_num++; diff --git a/src/mainboard/msi/ms9652_fam10/irq_tables.c b/src/mainboard/msi/ms9652_fam10/irq_tables.c index 97245ec..e33ceec 100644 --- a/src/mainboard/msi/ms9652_fam10/irq_tables.c +++ b/src/mainboard/msi/ms9652_fam10/irq_tables.c @@ -74,7 +74,7 @@ pirq->version = PIRQ_VERSION; pirq->rtr_bus = m->bus_mcp55[0]; - pirq->rtr_devfn = ((sbdn + 6) << 3) | 0; + pirq->rtr_devfn = PCI_DEVFN(sbdn + 6, 0); pirq->exclusive_irqs = 0; @@ -88,7 +88,7 @@ pirq_info = (void *)(&pirq->checksum + 1); slot_num = 0; //pci bridge - write_pirq_info(pirq_info, m->bus_mcp55[0], ((sbdn + 6) << 3) | 0, 0x1, + write_pirq_info(pirq_info, m->bus_mcp55[0], PCI_DEVFN(sbdn + 6, 0), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; @@ -99,19 +99,19 @@ unsigned busn = (sysconf.pci1234[i] >> 12) & 0xff; unsigned devn = sysconf.hcdn[i] & 0xff; - write_pirq_info(pirq_info, busn, (devn << 3) | 0, 0x1, 0xdef8, + write_pirq_info(pirq_info, busn, PCI_DEVFN(devn, 0), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; } #if CONFIG_CBB - write_pirq_info(pirq_info, CONFIG_CBB, (0 << 3) | 0, 0x1, 0xdef8, 0x2, + write_pirq_info(pirq_info, CONFIG_CBB, PCI_DEVFN(0, 0), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; if (sysconf.nodes > 32) { - write_pirq_info(pirq_info, CONFIG_CBB - 1, (0 << 3) | 0, 0x1, + write_pirq_info(pirq_info, CONFIG_CBB - 1, PCI_DEVFN(0, 0), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; diff --git a/src/mainboard/supermicro/h8dmr_fam10/irq_tables.c b/src/mainboard/supermicro/h8dmr_fam10/irq_tables.c index 97245ec..e33ceec 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/irq_tables.c +++ b/src/mainboard/supermicro/h8dmr_fam10/irq_tables.c @@ -74,7 +74,7 @@ pirq->version = PIRQ_VERSION; pirq->rtr_bus = m->bus_mcp55[0]; - pirq->rtr_devfn = ((sbdn + 6) << 3) | 0; + pirq->rtr_devfn = PCI_DEVFN(sbdn + 6, 0); pirq->exclusive_irqs = 0; @@ -88,7 +88,7 @@ pirq_info = (void *)(&pirq->checksum + 1); slot_num = 0; //pci bridge - write_pirq_info(pirq_info, m->bus_mcp55[0], ((sbdn + 6) << 3) | 0, 0x1, + write_pirq_info(pirq_info, m->bus_mcp55[0], PCI_DEVFN(sbdn + 6, 0), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; @@ -99,19 +99,19 @@ unsigned busn = (sysconf.pci1234[i] >> 12) & 0xff; unsigned devn = sysconf.hcdn[i] & 0xff; - write_pirq_info(pirq_info, busn, (devn << 3) | 0, 0x1, 0xdef8, + write_pirq_info(pirq_info, busn, PCI_DEVFN(devn, 0), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; } #if CONFIG_CBB - write_pirq_info(pirq_info, CONFIG_CBB, (0 << 3) | 0, 0x1, 0xdef8, 0x2, + write_pirq_info(pirq_info, CONFIG_CBB, PCI_DEVFN(0, 0), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; if (sysconf.nodes > 32) { - write_pirq_info(pirq_info, CONFIG_CBB - 1, (0 << 3) | 0, 0x1, + write_pirq_info(pirq_info, CONFIG_CBB - 1, PCI_DEVFN(0, 0), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; diff --git a/src/mainboard/supermicro/h8qme_fam10/irq_tables.c b/src/mainboard/supermicro/h8qme_fam10/irq_tables.c index b5ea2c2..5248567 100644 --- a/src/mainboard/supermicro/h8qme_fam10/irq_tables.c +++ b/src/mainboard/supermicro/h8qme_fam10/irq_tables.c @@ -74,7 +74,7 @@ pirq->version = PIRQ_VERSION; pirq->rtr_bus = m->bus_mcp55[0]; - pirq->rtr_devfn = ((sbdn + 6) << 3) | 0; + pirq->rtr_devfn = PCI_DEVFN(sbdn + 6, 0); pirq->exclusive_irqs = 0; @@ -88,7 +88,7 @@ pirq_info = (void *)(&pirq->checksum + 1); slot_num = 0; //pci bridge - write_pirq_info(pirq_info, m->bus_mcp55[0], ((sbdn + 6) << 3) | 0, 0x1, + write_pirq_info(pirq_info, m->bus_mcp55[0], PCI_DEVFN(sbdn + 6, 0), 0x1, 0x4ca0, 0x2, 0x4ca0, 0x3, 0x4ca0, 0x4, 0x4ca0, 0, 0); pirq_info++; slot_num++; @@ -99,19 +99,19 @@ unsigned busn = (sysconf.pci1234[i] >> 12) & 0xff; unsigned devn = sysconf.hcdn[i] & 0xff; - write_pirq_info(pirq_info, busn, (devn << 3) | 0, 0x1, 0x4ca0, + write_pirq_info(pirq_info, busn, PCI_DEVFN(devn, 0), 0x1, 0x4ca0, 0x2, 0x4ca0, 0x3, 0x4ca0, 0x4, 0x4ca0, 0, 0); pirq_info++; slot_num++; } #if CONFIG_CBB - write_pirq_info(pirq_info, CONFIG_CBB, (0 << 3) | 0, 0x1, 0x4ca0, 0x2, + write_pirq_info(pirq_info, CONFIG_CBB, PCI_DEVFN(0, 0), 0x1, 0x4ca0, 0x2, 0x4ca0, 0x3, 0x4ca0, 0x4, 0x4ca0, 0, 0); pirq_info++; slot_num++; if (sysconf.nodes > 32) { - write_pirq_info(pirq_info, CONFIG_CBB - 1, (0 << 3) | 0, 0x1, + write_pirq_info(pirq_info, CONFIG_CBB - 1, PCI_DEVFN(0, 0), 0x1, 0x4ca0, 0x2, 0x4ca0, 0x3, 0x4ca0, 0x4, 0x4ca0, 0, 0); pirq_info++; diff --git a/src/mainboard/tyan/s2912_fam10/irq_tables.c b/src/mainboard/tyan/s2912_fam10/irq_tables.c index 97245ec..e33ceec 100644 --- a/src/mainboard/tyan/s2912_fam10/irq_tables.c +++ b/src/mainboard/tyan/s2912_fam10/irq_tables.c @@ -74,7 +74,7 @@ pirq->version = PIRQ_VERSION; pirq->rtr_bus = m->bus_mcp55[0]; - pirq->rtr_devfn = ((sbdn + 6) << 3) | 0; + pirq->rtr_devfn = PCI_DEVFN(sbdn + 6, 0); pirq->exclusive_irqs = 0; @@ -88,7 +88,7 @@ pirq_info = (void *)(&pirq->checksum + 1); slot_num = 0; //pci bridge - write_pirq_info(pirq_info, m->bus_mcp55[0], ((sbdn + 6) << 3) | 0, 0x1, + write_pirq_info(pirq_info, m->bus_mcp55[0], PCI_DEVFN(sbdn + 6, 0), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; @@ -99,19 +99,19 @@ unsigned busn = (sysconf.pci1234[i] >> 12) & 0xff; unsigned devn = sysconf.hcdn[i] & 0xff; - write_pirq_info(pirq_info, busn, (devn << 3) | 0, 0x1, 0xdef8, + write_pirq_info(pirq_info, busn, PCI_DEVFN(devn, 0), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; } #if CONFIG_CBB - write_pirq_info(pirq_info, CONFIG_CBB, (0 << 3) | 0, 0x1, 0xdef8, 0x2, + write_pirq_info(pirq_info, CONFIG_CBB, PCI_DEVFN(0, 0), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; if (sysconf.nodes > 32) { - write_pirq_info(pirq_info, CONFIG_CBB - 1, (0 << 3) | 0, 0x1, + write_pirq_info(pirq_info, CONFIG_CBB - 1, PCI_DEVFN(0, 0), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; -- To view, visit https://review.coreboot.org/c/coreboot/+/30737 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b9aeaaa1cfa20efc9d187d91ece4eb9ee659c3f Gerrit-Change-Number: 30737 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit January 2019