coreboot-gerrit January 2019

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Change in ...coreboot[master]: arch/x86/lapic: Remove second stack poisoning
by Kyösti Mälkki (Code Review) 10 Jan '19

10 Jan '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30796 Change subject: arch/x86/lapic: Remove second stack poisoning ...................................................................... arch/x86/lapic: Remove second stack poisoning It was already done once in c_start.S. Change-Id: I1cb0ea25251644dbd1127d177247a02ba52bb550 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/x86/lapic/lapic_cpu_init.c 1 file changed, 2 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/30796/1 diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 0a51a08..cf61530 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -269,7 +269,6 @@ unsigned long apicid; unsigned int index; unsigned long count; - int i; int result; spin_lock(&start_cpu_lock); @@ -287,10 +286,8 @@ stack_base = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*(index+1)); printk(BIOS_SPEW, "CPU%d: stack_base %p, stack_end %p\n", index, (void *)stack_base, (void *)stack_end); - /* poison the stack */ - for (stack = (void *)stack_base, i = 0; i < CONFIG_STACK_SIZE; i++) - stack[i/sizeof(*stack)] = 0xDEADBEEF; - stacks[index] = stack; + stacks[index] = (void *)stack_base; + /* Record the index and which CPU structure we are using */ info = (struct cpu_info *)stack_end; info->index = index; -- To view, visit https://review.coreboot.org/c/coreboot/+/30796 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1cb0ea25251644dbd1127d177247a02ba52bb550 Gerrit-Change-Number: 30796 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: arch/x86/ebda: Don't trash the EBDA on the resume path
by Arthur Heymans (Code Review) 09 Jan '19

09 Jan '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30789 Change subject: arch/x86/ebda: Don't trash the EBDA on the resume path ...................................................................... arch/x86/ebda: Don't trash the EBDA on the resume path With some payloads the RSDP can end up in an area this function is trashing hence breaking S3 resume. Change-Id: I9c54156bd8247e8a34dec6edc27cfc2d33cde595 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/ebda.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/30789/1 diff --git a/src/arch/x86/ebda.c b/src/arch/x86/ebda.c index f6726cf..62c81bd 100644 --- a/src/arch/x86/ebda.c +++ b/src/arch/x86/ebda.c @@ -18,6 +18,7 @@ #include <string.h> #include <arch/io.h> #include <arch/ebda.h> +#include <arch/acpi.h> #include <commonlib/endian.h> #include <console/console.h> @@ -104,6 +105,8 @@ void setup_default_ebda(void) { + if (acpi_is_wakeup_s3()) + return; setup_ebda(DEFAULT_EBDA_LOWMEM, DEFAULT_EBDA_SEGMENT, DEFAULT_EBDA_SIZE); -- To view, visit https://review.coreboot.org/c/coreboot/+/30789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c54156bd8247e8a34dec6edc27cfc2d33cde595 Gerrit-Change-Number: 30789 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mainboard/google/octopus: configure EC_AP_INT_ODL
by Jett Rink (Code Review) 09 Jan '19

09 Jan '19

Jett Rink has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30788 Change subject: mainboard/google/octopus: configure EC_AP_INT_ODL ...................................................................... mainboard/google/octopus: configure EC_AP_INT_ODL Enable the EC_AP_INT_ODL interrupt on GPIO_134 for all octopus boards that support it. BRANCH=octopus BUG=b:122552125 TEST=CTS tests with changes Change-Id: I018864ae5fa400372b5b443e49828e8202b9aa4d Signed-off-by: Jett Rink <jettrink(a)chromium.org> --- M src/mainboard/google/octopus/variants/ampton/gpio.c M src/mainboard/google/octopus/variants/ampton/include/variant/ec.h M src/mainboard/google/octopus/variants/ampton/include/variant/gpio.h M src/mainboard/google/octopus/variants/bobba/gpio.c M src/mainboard/google/octopus/variants/casta/gpio.c M src/mainboard/google/octopus/variants/casta/include/variant/ec.h M src/mainboard/google/octopus/variants/casta/include/variant/gpio.h M src/mainboard/google/octopus/variants/fleex/gpio.c M src/mainboard/google/octopus/variants/fleex/include/variant/ec.h M src/mainboard/google/octopus/variants/fleex/include/variant/gpio.h M src/mainboard/google/octopus/variants/meep/gpio.c M src/mainboard/google/octopus/variants/meep/include/variant/ec.h M src/mainboard/google/octopus/variants/meep/include/variant/gpio.h M src/mainboard/google/octopus/variants/phaser/gpio.c M src/mainboard/google/octopus/variants/phaser/include/variant/ec.h M src/mainboard/google/octopus/variants/phaser/include/variant/gpio.h 16 files changed, 50 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/30788/1 diff --git a/src/mainboard/google/octopus/variants/ampton/gpio.c b/src/mainboard/google/octopus/variants/ampton/gpio.c index f34645d..f9eb718 100644 --- a/src/mainboard/google/octopus/variants/ampton/gpio.c +++ b/src/mainboard/google/octopus/variants/ampton/gpio.c @@ -194,7 +194,10 @@ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_132, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* HV_DDI1_HPD */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_133, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* HV_EDP_HPD */ - PAD_NC(GPIO_134, NONE),/* GPIO_134 -- EC_AP_INT_ODL */ + /* EC_AP_INT_ODL */ + PAD_CFG_GPI_APIC_IOS(GPIO_134, NONE, DEEP, LEVEL, INVERT, TxDRxE, + DISPUPD), + /* GPIO_135 -- TRACKPAD_INT1_1V8_ODL */ PAD_CFG_GPI_IRQ_WAKE(GPIO_135, NONE, DEEP, LEVEL, INVERT), PAD_CFG_GPI_APIC_IOS(GPIO_136, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD),/* GPIO_136 -- PMIC_PCH_INT_ODL */ diff --git a/src/mainboard/google/octopus/variants/ampton/include/variant/ec.h b/src/mainboard/google/octopus/variants/ampton/include/variant/ec.h index 16f931b..b75794a 100644 --- a/src/mainboard/google/octopus/variants/ampton/include/variant/ec.h +++ b/src/mainboard/google/octopus/variants/ampton/include/variant/ec.h @@ -18,4 +18,7 @@ #include <baseboard/ec.h> +/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in variant/gpio.h */ +#define EC_ENABLE_SYNC_IRQ + #endif diff --git a/src/mainboard/google/octopus/variants/ampton/include/variant/gpio.h b/src/mainboard/google/octopus/variants/ampton/include/variant/gpio.h index 1fd1e11..a59bbf4 100644 --- a/src/mainboard/google/octopus/variants/ampton/include/variant/gpio.h +++ b/src/mainboard/google/octopus/variants/ampton/include/variant/gpio.h @@ -18,4 +18,7 @@ #include <baseboard/gpio.h> +/* EC sync irq is GPP_134_IRQ */ +#define EC_SYNC_IRQ GPIO_134_IRQ + #endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/octopus/variants/bobba/gpio.c b/src/mainboard/google/octopus/variants/bobba/gpio.c index acdcf97..f1a3973 100644 --- a/src/mainboard/google/octopus/variants/bobba/gpio.c +++ b/src/mainboard/google/octopus/variants/bobba/gpio.c @@ -22,7 +22,7 @@ static const struct pad_config default_override_table[] = { PAD_NC(GPIO_104, UP_20K), - /* CAM_SOC_EC_SYNC */ + /* EC_AP_INT_ODL */ PAD_CFG_GPI_APIC_IOS(GPIO_134, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD), diff --git a/src/mainboard/google/octopus/variants/casta/gpio.c b/src/mainboard/google/octopus/variants/casta/gpio.c index ba26e31..bbb8a98 100644 --- a/src/mainboard/google/octopus/variants/casta/gpio.c +++ b/src/mainboard/google/octopus/variants/casta/gpio.c @@ -38,8 +38,9 @@ /* PCIE_CLKREQ3_B -- unused */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_122, UP_20K, DEEP, NF1, HIZCRx1, ENPU), - /* CAM_SOC_EC_SYNC */ - PAD_CFG_GPI_APIC_IOS(GPIO_134, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE, + + /* EC_AP_INT_ODL */ + PAD_CFG_GPI_APIC_IOS(GPIO_134, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD), PAD_NC(GPIO_138, UP_20K), /* PEN_PDCT_ODL -- unused */ diff --git a/src/mainboard/google/octopus/variants/casta/include/variant/ec.h b/src/mainboard/google/octopus/variants/casta/include/variant/ec.h index 16f931b..b75794a 100644 --- a/src/mainboard/google/octopus/variants/casta/include/variant/ec.h +++ b/src/mainboard/google/octopus/variants/casta/include/variant/ec.h @@ -18,4 +18,7 @@ #include <baseboard/ec.h> +/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in variant/gpio.h */ +#define EC_ENABLE_SYNC_IRQ + #endif diff --git a/src/mainboard/google/octopus/variants/casta/include/variant/gpio.h b/src/mainboard/google/octopus/variants/casta/include/variant/gpio.h index 1fd1e11..a59bbf4 100644 --- a/src/mainboard/google/octopus/variants/casta/include/variant/gpio.h +++ b/src/mainboard/google/octopus/variants/casta/include/variant/gpio.h @@ -18,4 +18,7 @@ #include <baseboard/gpio.h> +/* EC sync irq is GPP_134_IRQ */ +#define EC_SYNC_IRQ GPIO_134_IRQ + #endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/octopus/variants/fleex/gpio.c b/src/mainboard/google/octopus/variants/fleex/gpio.c index 39d239b..d112a2c 100644 --- a/src/mainboard/google/octopus/variants/fleex/gpio.c +++ b/src/mainboard/google/octopus/variants/fleex/gpio.c @@ -28,8 +28,8 @@ PAD_NC(GPIO_67, UP_20K), PAD_NC(GPIO_117, UP_20K), - /* CAM_SOC_EC_SYNC */ - PAD_CFG_GPI_APIC_IOS(GPIO_134, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE, + /* EC_AP_INT_ODL */ + PAD_CFG_GPI_APIC_IOS(GPIO_134, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD), PAD_NC(GPIO_138, DN_20K), diff --git a/src/mainboard/google/octopus/variants/fleex/include/variant/ec.h b/src/mainboard/google/octopus/variants/fleex/include/variant/ec.h index 16f931b..b75794a 100644 --- a/src/mainboard/google/octopus/variants/fleex/include/variant/ec.h +++ b/src/mainboard/google/octopus/variants/fleex/include/variant/ec.h @@ -18,4 +18,7 @@ #include <baseboard/ec.h> +/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in variant/gpio.h */ +#define EC_ENABLE_SYNC_IRQ + #endif diff --git a/src/mainboard/google/octopus/variants/fleex/include/variant/gpio.h b/src/mainboard/google/octopus/variants/fleex/include/variant/gpio.h index 1fd1e11..a59bbf4 100644 --- a/src/mainboard/google/octopus/variants/fleex/include/variant/gpio.h +++ b/src/mainboard/google/octopus/variants/fleex/include/variant/gpio.h @@ -18,4 +18,7 @@ #include <baseboard/gpio.h> +/* EC sync irq is GPP_134_IRQ */ +#define EC_SYNC_IRQ GPIO_134_IRQ + #endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/octopus/variants/meep/gpio.c b/src/mainboard/google/octopus/variants/meep/gpio.c index 7e57287..29733e8 100644 --- a/src/mainboard/google/octopus/variants/meep/gpio.c +++ b/src/mainboard/google/octopus/variants/meep/gpio.c @@ -21,8 +21,8 @@ static const struct pad_config default_override_table[] = { PAD_NC(GPIO_104, UP_20K), - /* CAM_SOC_EC_SYNC */ - PAD_CFG_GPI_APIC_IOS(GPIO_134, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE, + /* EC_AP_INT_ODL */ + PAD_CFG_GPI_APIC_IOS(GPIO_134, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD), /* EN_PP3300_TOUCHSCREEN */ diff --git a/src/mainboard/google/octopus/variants/meep/include/variant/ec.h b/src/mainboard/google/octopus/variants/meep/include/variant/ec.h index 16f931b..b75794a 100644 --- a/src/mainboard/google/octopus/variants/meep/include/variant/ec.h +++ b/src/mainboard/google/octopus/variants/meep/include/variant/ec.h @@ -18,4 +18,7 @@ #include <baseboard/ec.h> +/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in variant/gpio.h */ +#define EC_ENABLE_SYNC_IRQ + #endif diff --git a/src/mainboard/google/octopus/variants/meep/include/variant/gpio.h b/src/mainboard/google/octopus/variants/meep/include/variant/gpio.h index 1fd1e11..a59bbf4 100644 --- a/src/mainboard/google/octopus/variants/meep/include/variant/gpio.h +++ b/src/mainboard/google/octopus/variants/meep/include/variant/gpio.h @@ -18,4 +18,7 @@ #include <baseboard/gpio.h> +/* EC sync irq is GPP_134_IRQ */ +#define EC_SYNC_IRQ GPIO_134_IRQ + #endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/octopus/variants/phaser/gpio.c b/src/mainboard/google/octopus/variants/phaser/gpio.c index 322b44b..c4e1e69 100644 --- a/src/mainboard/google/octopus/variants/phaser/gpio.c +++ b/src/mainboard/google/octopus/variants/phaser/gpio.c @@ -30,6 +30,10 @@ PAD_NC(GPIO_117, UP_20K), PAD_NC(GPIO_143, UP_20K), + /* EC_AP_INT_ODL */ + PAD_CFG_GPI_APIC_IOS(GPIO_134, NONE, DEEP, LEVEL, INVERT, TxDRxE, + DISPUPD), + /* EN_PP3300_TOUCHSCREEN */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), @@ -54,6 +58,10 @@ PAD_NC(GPIO_117, UP_20K), PAD_NC(GPIO_143, UP_20K), + /* EC_AP_INT_ODL */ + PAD_CFG_GPI_APIC_IOS(GPIO_134, NONE, DEEP, LEVEL, INVERT, TxDRxE, + DISPUPD), + /* EN_PP3300_TOUCHSCREEN */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), diff --git a/src/mainboard/google/octopus/variants/phaser/include/variant/ec.h b/src/mainboard/google/octopus/variants/phaser/include/variant/ec.h index 16f931b..b75794a 100644 --- a/src/mainboard/google/octopus/variants/phaser/include/variant/ec.h +++ b/src/mainboard/google/octopus/variants/phaser/include/variant/ec.h @@ -18,4 +18,7 @@ #include <baseboard/ec.h> +/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in variant/gpio.h */ +#define EC_ENABLE_SYNC_IRQ + #endif diff --git a/src/mainboard/google/octopus/variants/phaser/include/variant/gpio.h b/src/mainboard/google/octopus/variants/phaser/include/variant/gpio.h index 1fd1e11..a59bbf4 100644 --- a/src/mainboard/google/octopus/variants/phaser/include/variant/gpio.h +++ b/src/mainboard/google/octopus/variants/phaser/include/variant/gpio.h @@ -18,4 +18,7 @@ #include <baseboard/gpio.h> +/* EC sync irq is GPP_134_IRQ */ +#define EC_SYNC_IRQ GPIO_134_IRQ + #endif /* MAINBOARD_GPIO_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30788 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I018864ae5fa400372b5b443e49828e8202b9aa4d Gerrit-Change-Number: 30788 Gerrit-PatchSet: 1 Gerrit-Owner: Jett Rink <jettrink(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/amd/{cimx,sb{7,8}00}: Use PCI_DEVFN()
by HAOUAS Elyes (Code Review) 09 Jan '19

09 Jan '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30786 Change subject: sb/amd/{cimx,sb{7,8}00}: Use PCI_DEVFN() ...................................................................... sb/amd/{cimx,sb{7,8}00}: Use PCI_DEVFN() Change-Id: I731fd4ecfab679cd3d830a89bc82c56cf9008bc4 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/amd/cimx/sb900/late.c M src/southbridge/amd/sb700/sb700.c M src/southbridge/amd/sb800/sb800.c 3 files changed, 48 insertions(+), 48 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/30786/1 diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c index 25e087f..e5366e9 100644 --- a/src/southbridge/amd/cimx/sb900/late.c +++ b/src/southbridge/amd/cimx/sb900/late.c @@ -347,11 +347,11 @@ //- commonInitEarlyPost(sb_config); switch (dev->path.pci.devfn) { - case (0x10 << 3) | 0: /* 0:10:0 XHCI-USB */ + case PCI_DEVFN(0x10, 0): /* XHCI-USB */ //- usbInitBeforePciEnum(sb_config); // USB POST TIME Only break; - case (0x11 << 3) | 0: /* 0:11.0 SATA */ + case PCI_DEVFN(0x11, 0): /* SATA */ if (dev->enabled) { sb_config->SATAMODE.SataMode.SataController = ENABLED; if (sb_chip->boot_switch_sata_ide == 1) @@ -365,18 +365,18 @@ //- sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY break; - case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */ - case (0x12 << 3) | 2: /* 0:12:2 EHCI-USB1 */ - case (0x13 << 3) | 0: /* 0:13:0 OHCI-USB2 */ - case (0x13 << 3) | 2: /* 0:13:2 EHCI-USB2 */ - case (0x14 << 3) | 5: /* 0:14:5 OHCI-USB4 */ + case PCI_DEVFN(0x12, 0): /* OHCI-USB1 */ + case PCI_DEVFN(0x12, 2): /* EHCI-USB1 */ + case PCI_DEVFN(0x13, 0): /* OHCI-USB2 */ + case PCI_DEVFN(0x13, 2): /* EHCI-USB2 */ + case PCI_DEVFN(0x14, 5): /* OHCI-USB4 */ //- usbInitBeforePciEnum(sb_config); // USB POST TIME Only break; - case (0x14 << 3) | 0: /* 0:14:0 SMBUS */ + case PCI_DEVFN(0x14, 0): /* SMBUS */ break; - case (0x14 << 3) | 1: /* 0:14:1 IDE */ + case PCI_DEVFN(0x14, 1): /* IDE */ if (dev->enabled) { sb_config->SATAMODE.SataMode.SataIdeCombinedMode = ENABLED; } else { @@ -385,7 +385,7 @@ //- sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY break; - case (0x14 << 3) | 2: /* 0:14:2 HDA */ + case PCI_DEVFN(0x14, 2): /* HDA */ if (dev->enabled) { if (sb_config->AzaliaController == AZALIA_DISABLE) { sb_config->AzaliaController = AZALIA_AUTO; @@ -399,13 +399,13 @@ break; - case (0x14 << 3) | 3: /* 0:14:3 LPC */ + case PCI_DEVFN(0x14, 3): /* LPC */ break; - case (0x14 << 3) | 4: /* 0:14:4 PCI */ + case PCI_DEVFN(0x14, 4): /* PCI */ break; - case (0x14 << 3) | 6: /* 0:14:6 GEC */ + case PCI_DEVFN(0x14, 6): /* GEC */ if (dev->enabled) { sb_config->GecConfig = 0; printk(BIOS_DEBUG, "gec enabled\n"); @@ -416,10 +416,10 @@ //- gecInitBeforePciEnum(sb_config); // Init GEC break; - case (0x15 << 3) | 0: /* 0:15:0 PCIe PortA */ - case (0x15 << 3) | 1: /* 0:15:1 PCIe PortB */ - case (0x15 << 3) | 2: /* 0:15:2 PCIe PortC */ - case (0x15 << 3) | 3: /* 0:15:3 PCIe PortD */ + case PCI_DEVFN(0x15, 0): /* PCIe PortA */ + case PCI_DEVFN(0x15, 1): /* PCIe PortB */ + case PCI_DEVFN(0x15, 2): /* PCIe PortC */ + case PCI_DEVFN(0x15, 3): /* PCIe PortD */ gpp_port = (dev->path.pci.devfn) & 0x03; if (dev->enabled) { sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent = ENABLED; diff --git a/src/southbridge/amd/sb700/sb700.c b/src/southbridge/amd/sb700/sb700.c index b7ff58d..8929f3f 100644 --- a/src/southbridge/amd/sb700/sb700.c +++ b/src/southbridge/amd/sb700/sb700.c @@ -167,53 +167,53 @@ return; switch (dev->path.pci.devfn - (devfn - (0x14 << 3))) { - case (0x11 << 3) | 0: + case PCI_DEVFN(0x11, 0): index = 8; set_sm_enable_bits(sm_dev, 0xac, 1 << index, (dev->enabled ? 1 : 0) << index); index += 32 * 3; break; - case (0x12 << 3) | 0: - case (0x12 << 3) | 1: - case (0x12 << 3) | 2: + case PCI_DEVFN(0x12, 0): + case PCI_DEVFN(0x12, 1): + case PCI_DEVFN(0x12, 2): index = dev->path.pci.devfn & 3; set_sm_enable_bits(sm_dev, 0x68, 1 << index, (dev->enabled ? 1 : 0) << index); index += 32 * 2; break; - case (0x13 << 3) | 0: - case (0x13 << 3) | 1: - case (0x13 << 3) | 2: + case PCI_DEVFN(0x13, 0): + case PCI_DEVFN(0x13, 1): + case PCI_DEVFN(0x13, 2): index = (dev->path.pci.devfn & 3) + 4; set_sm_enable_bits(sm_dev, 0x68, 1 << index, (dev->enabled ? 1 : 0) << index); index += 32 * 2; break; - case (0x14 << 3) | 5: + case PCI_DEVFN(0x14, 5): index = 7; set_sm_enable_bits(sm_dev, 0x68, 1 << index, (dev->enabled ? 1 : 0) << index); index += 32 * 2; break; - case (0x14 << 3) | 0: + case PCI_DEVFN(0x14, 0): index = 0; break; - case (0x14 << 3) | 1: + case PCI_DEVFN(0x14, 1): index = 1; break; - case (0x14 << 3) | 2: + case PCI_DEVFN(0x14, 2): index = 3; set_pmio_enable_bits(sm_dev, 0x59, 1 << index, (dev->enabled ? 1 : 0) << index); index += 32 * 4; break; - case (0x14 << 3) | 3: + case PCI_DEVFN(0x14, 3): index = 20; set_sm_enable_bits(sm_dev, 0x64, 1 << index, (dev->enabled ? 1 : 0) << index); index += 32 * 1; break; - case (0x14 << 3) | 4: + case PCI_DEVFN(0x14, 4): index = 4; break; default: diff --git a/src/southbridge/amd/sb800/sb800.c b/src/southbridge/amd/sb800/sb800.c index bd4dc68..eda4d30 100644 --- a/src/southbridge/amd/sb800/sb800.c +++ b/src/southbridge/amd/sb800/sb800.c @@ -294,7 +294,7 @@ printk(BIOS_DEBUG, "sb800_enable() 2\n"); switch (dev->path.pci.devfn - (devfn - (0x14 << 3))) { - case (0x11 << 3) | 0: + case PCI_DEVFN(0x11, 0): index = 8; set_pmio_enable_bits(0xDA, 1 << 0, (dev->enabled ? 1 : 0) << 0); @@ -307,63 +307,63 @@ pci_write_config32(dev, 0x40, dword);//for (;;); index += 32 * 3; break; - case (0x12 << 3) | 0: - case (0x12 << 3) | 2: + case PCI_DEVFN(0x12, 0): + case PCI_DEVFN(0x12, 2): index = (dev->path.pci.devfn & 0x3) / 2; set_pmio_enable_bits(0xEF, 1 << index, (dev->enabled ? 1 : 0) << index); break; - case (0x13 << 3) | 0: - case (0x13 << 3) | 2: + case PCI_DEVFN(0x13, 0): + case PCI_DEVFN(0x13, 2): index = (dev->path.pci.devfn & 0x3) / 2 + 2; set_pmio_enable_bits(0xEF, 1 << index, (dev->enabled ? 1 : 0) << index); index += 32 * 2; break; - case (0x14 << 3) | 0: + case PCI_DEVFN(0x14, 0): index = 0; break; - case (0x14 << 3) | 1: + case PCI_DEVFN(0x14, 1): index = 1; set_pmio_enable_bits(0xDA, 1 << 3, (dev->enabled ? 0 : 1) << 3); break; - case (0x14 << 3) | 2: + case PCI_DEVFN(0x14, 2): index = 0; set_pmio_enable_bits(0xEB, 1 << index, (dev->enabled ? 1 : 0) << index); break; - case (0x14 << 3) | 3: + case PCI_DEVFN(0x14, 3): index = 0; set_pmio_enable_bits(0xEC, 1 << index, (dev->enabled ? 1 : 0) << index); index += 32 * 1; break; - case (0x14 << 3) | 4: + case PCI_DEVFN(0x14, 4): index = 0; set_pmio_enable_bits(0xEA, 1 << index, (dev->enabled ? 0 : 1) << index); break; - case (0x14 << 3) | 5: + case PCI_DEVFN(0x14, 5): index = 6; set_pmio_enable_bits(0xEF, 1 << index, (dev->enabled ? 1 : 0) << index); break; - case (0x14 << 3) | 6: + case PCI_DEVFN(0x14, 6): index = 0; set_pmio_enable_bits(0xF6, 1 << index, (dev->enabled ? 0 : 1) << index); break; - case (0x15 << 3) | 0: + case PCI_DEVFN(0x15, 0): set_sb800_gpp(dev); index = 4; break; - case (0x15 << 3) | 1: - case (0x15 << 3) | 2: - case (0x15 << 3) | 3: + case PCI_DEVFN(0x15, 1): + case PCI_DEVFN(0x15, 2): + case PCI_DEVFN(0x15, 3): break; - case (0x16 << 3) | 0: - case (0x16 << 3) | 2: + case PCI_DEVFN(0x16, 0): + case PCI_DEVFN(0x16, 2): index = (dev->path.pci.devfn & 0x3) / 2 + 4; set_pmio_enable_bits(0xEF, 1 << index, (dev->enabled ? 1 : 0) << index); -- To view, visit https://review.coreboot.org/c/coreboot/+/30786 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I731fd4ecfab679cd3d830a89bc82c56cf9008bc4 Gerrit-Change-Number: 30786 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: mb/google/hatch: enable CPU cluster device
by Aamir Bohra (Code Review) 09 Jan '19

09 Jan '19

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30785 Change subject: mb/google/hatch: enable CPU cluster device ...................................................................... mb/google/hatch: enable CPU cluster device Change-Id: I28c67fbdf2b4f371c4b533b64cad2c4376ca2bd2 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/30785/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 402a97e..ca04507 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -74,6 +74,10 @@ # ClkReq-to-ClkSrc mapping for CLK SRC 1 register "PcieClkSrcClkReq[1]" = "1" + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device -- To view, visit https://review.coreboot.org/c/coreboot/+/30785 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28c67fbdf2b4f371c4b533b64cad2c4376ca2bd2 Gerrit-Change-Number: 30785 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: northbridge/amdfam10: Deal with PCI_ADDR() better
by Kyösti Mälkki (Code Review) 09 Jan '19

09 Jan '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30784 Change subject: northbridge/amdfam10: Deal with PCI_ADDR() better ...................................................................... northbridge/amdfam10: Deal with PCI_ADDR() better PCI_ADDR() is tightly coupled with different setup_resource_map() variants so move the declaration away from global namespace. In the implementation of setup_resource_map() use the bottom 12 bits as the register mask like the other variants do already. Change-Id: Iadedfe993621a4458ce8f12c5e98c8cee537d2db Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/include/arch/io.h M src/northbridge/amd/amdfam10/amdfam10.h M src/northbridge/amd/amdfam10/setup_resource_map.c 3 files changed, 10 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/30784/1 diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index 9e2a877..e4e3067 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -235,12 +235,6 @@ #ifdef __SIMPLE_DEVICE__ -#define PCI_ADDR(SEGBUS, DEV, FN, WHERE) ( \ - (((SEGBUS) & 0xFFF) << 20) | \ - (((DEV) & 0x1F) << 15) | \ - (((FN) & 0x07) << 12) | \ - ((WHERE) & 0xFFF)) - #define PCI_DEV(SEGBUS, DEV, FN) ( \ (((SEGBUS) & 0xFFF) << 20) | \ (((DEV) & 0x1F) << 15) | \ diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index e1c88c9..c912f18 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -29,6 +29,12 @@ /* Definitions for setup_resourcemap() variants. */ +#define PCI_ADDR(SEGBUS, DEV, FN, WHERE) ( \ + (((SEGBUS) & 0xFFF) << 20) | \ + (((DEV) & 0x1F) << 15) | \ + (((FN) & 0x07) << 12) | \ + ((WHERE) & 0xFFF)) + #define ADDRMAP_REG(r) PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, r) #define RES_PCI_IO 0x10 diff --git a/src/northbridge/amd/amdfam10/setup_resource_map.c b/src/northbridge/amd/amdfam10/setup_resource_map.c index 23e2ba3..5984178 100644 --- a/src/northbridge/amd/amdfam10/setup_resource_map.c +++ b/src/northbridge/amd/amdfam10/setup_resource_map.c @@ -30,8 +30,8 @@ u32 where; u32 reg; - dev = register_values[i] & ~0xff; - where = register_values[i] & 0xff; + dev = register_values[i] & ~0xfff; + where = register_values[i] & 0xfff; reg = pci_read_config32(dev, where); reg &= register_values[i+1]; reg |= register_values[i+2]; @@ -144,8 +144,8 @@ pci_devfn_t dev; u32 where; u32 reg; - dev = register_values[i+1] & ~0xff; - where = register_values[i+1] & 0xff; + dev = register_values[i+1] & ~0xfff; + where = register_values[i+1] & 0xfff; reg = pci_read_config32(dev, where); reg &= register_values[i+2]; reg |= register_values[i+3]; -- To view, visit https://review.coreboot.org/c/coreboot/+/30784 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iadedfe993621a4458ce8f12c5e98c8cee537d2db Gerrit-Change-Number: 30784 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: amdfam10 boards: Simplify early resourcemap
by Kyösti Mälkki (Code Review) 09 Jan '19

09 Jan '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30783 Change subject: amdfam10 boards: Simplify early resourcemap ...................................................................... amdfam10 boards: Simplify early resourcemap Purpose of the table is to load initial address maps on PCI function 0:18.1. Provide a macro of its own so it is clear no other PCI devfn is accessed here. Change-Id: Ic146207580a5625c4f6799693157b02422bef00a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/advansus/a785e-i/resourcemap.c M src/mainboard/amd/bimini_fam10/resourcemap.c M src/mainboard/amd/mahogany_fam10/resourcemap.c M src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c M src/mainboard/amd/tilapia_fam10/resourcemap.c M src/mainboard/asus/kcma-d8/resourcemap.c M src/mainboard/asus/kfsn4-dre/resourcemap.c M src/mainboard/asus/kgpe-d16/resourcemap.c M src/mainboard/asus/m4a78-em/resourcemap.c M src/mainboard/asus/m4a785-m/resourcemap.c M src/mainboard/asus/m5a88-v/resourcemap.c M src/mainboard/avalue/eax-785e/resourcemap.c M src/mainboard/gigabyte/ma785gm/resourcemap.c M src/mainboard/gigabyte/ma785gmt/resourcemap.c M src/mainboard/gigabyte/ma78gm/resourcemap.c M src/mainboard/iei/kino-780am2-fam10/resourcemap.c M src/mainboard/jetway/pa78vm5/resourcemap.c M src/mainboard/msi/ms9652_fam10/resourcemap.c M src/mainboard/supermicro/h8dmr_fam10/resourcemap.c M src/mainboard/supermicro/h8qme_fam10/resourcemap.c M src/mainboard/supermicro/h8scm_fam10/resourcemap.c M src/mainboard/tyan/s2912_fam10/resourcemap.c M src/northbridge/amd/amdfam10/amdfam10.h M src/northbridge/amd/amdfam10/resourcemap.c 24 files changed, 1,072 insertions(+), 1,067 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/30783/1 diff --git a/src/mainboard/advansus/a785e-i/resourcemap.c b/src/mainboard/advansus/a785e-i/resourcemap.c index 8390f49..ba264f3 100644 --- a/src/mainboard/advansus/a785e-i/resourcemap.c +++ b/src/mainboard/advansus/a785e-i/resourcemap.c @@ -48,13 +48,13 @@ * that define the end of the DRAM region. */ /* Don't touch it, we need it for CONFIG_CAR_FAM10 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, + ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, + ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, + ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, + ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, + ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, + ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, + ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, /* DRAM Base i Registers * F1:0x40 i = 0 * F1:0x48 i = 1 @@ -86,13 +86,13 @@ * that define the start of the DRAM region. */ /* don't touch it, we need it for CONFIG_CAR_FAM10 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, /* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -126,13 +126,13 @@ * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, + ADDRMAP_REG(0x84), 0x00000048, 0x00000000, + ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, + ADDRMAP_REG(0x94), 0x00000048, 0x00000000, + ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, + ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, + ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -160,13 +160,13 @@ * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -193,9 +193,9 @@ * This field defines the end of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, /* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -222,9 +222,9 @@ * This field defines the start of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, /* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -263,9 +263,9 @@ * This field defines the highest bus number in configuration regin i */ /* AMD 8111 on link0 of CPU 0 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, }; int max; diff --git a/src/mainboard/amd/bimini_fam10/resourcemap.c b/src/mainboard/amd/bimini_fam10/resourcemap.c index ce4351f..84897db 100644 --- a/src/mainboard/amd/bimini_fam10/resourcemap.c +++ b/src/mainboard/amd/bimini_fam10/resourcemap.c @@ -48,13 +48,13 @@ * that define the end of the DRAM region. */ /* Don't touch it, we need it for CONFIG_CAR_FAM10 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, + ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, + ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, + ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, + ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, + ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, + ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, + ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, /* DRAM Base i Registers * F1:0x40 i = 0 * F1:0x48 i = 1 @@ -87,13 +87,13 @@ */ /* don't touch it, we need it for CONFIG_CAR_FAM10 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, /* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -127,13 +127,13 @@ * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, + ADDRMAP_REG(0x84), 0x00000048, 0x00000000, + ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, + ADDRMAP_REG(0x94), 0x00000048, 0x00000000, + ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, + ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, + ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -161,13 +161,13 @@ * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -194,9 +194,9 @@ * This field defines the end of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, /* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -223,9 +223,9 @@ * This field defines the start of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, /* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -264,9 +264,9 @@ * This field defines the highest bus number in configuration regin i */ /* AMD 8111 on link0 of CPU 0 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, }; int max; diff --git a/src/mainboard/amd/mahogany_fam10/resourcemap.c b/src/mainboard/amd/mahogany_fam10/resourcemap.c index a4a1d92..e7a8cbf 100644 --- a/src/mainboard/amd/mahogany_fam10/resourcemap.c +++ b/src/mainboard/amd/mahogany_fam10/resourcemap.c @@ -49,14 +49,14 @@ * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, +// ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 + ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, + ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, + ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, + ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, + ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, + ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, + ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, /* DRAM Base i Registers * F1:0x40 i = 0 * F1:0x48 i = 1 @@ -87,14 +87,14 @@ * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, +// ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 + ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, /* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -128,14 +128,14 @@ * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, + ADDRMAP_REG(0x84), 0x00000048, 0x00000000, + ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, + ADDRMAP_REG(0x94), 0x00000048, 0x00000000, + ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, + ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, + ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, +// ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -163,14 +163,14 @@ * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, + ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, +// ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -197,10 +197,10 @@ * This field defines the end of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, +// ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff000, + ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, /* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -227,10 +227,10 @@ * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, +// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000003, + ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, /* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -268,10 +268,10 @@ * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, +// ADDRMAP_REG(0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 + ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, }; int max; diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c b/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c index 2a2380a..2c5c907 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c @@ -48,13 +48,13 @@ * that define the end of the DRAM region. */ /* Don't touch it, we need it for CAR with FAM10 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, + ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, + ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, + ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, + ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, + ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, + ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, + ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, /* DRAM Base i Registers * F1:0x40 i = 0 * F1:0x48 i = 1 @@ -86,13 +86,13 @@ * that define the start of the DRAM region. */ /* don't touch it, we need it for CAR with FAM10 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, /* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -126,13 +126,13 @@ * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, + ADDRMAP_REG(0x84), 0x00000048, 0x00000000, + ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, + ADDRMAP_REG(0x94), 0x00000048, 0x00000000, + ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, + ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, + ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -160,13 +160,13 @@ * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -193,9 +193,9 @@ * This field defines the end of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, /* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -222,9 +222,9 @@ * This field defines the start of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, /* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -263,9 +263,9 @@ * This field defines the highest bus number in configuration regin i */ /* AMD 8111 on link0 of CPU 0 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, }; int max; diff --git a/src/mainboard/amd/tilapia_fam10/resourcemap.c b/src/mainboard/amd/tilapia_fam10/resourcemap.c index 37b6d20..d51e128 100644 --- a/src/mainboard/amd/tilapia_fam10/resourcemap.c +++ b/src/mainboard/amd/tilapia_fam10/resourcemap.c @@ -48,13 +48,13 @@ * that define the end of the DRAM region. */ /* Don't touch it, we need it for CONFIG_CAR_FAM10 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, + ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, + ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, + ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, + ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, + ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, + ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, + ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, /* DRAM Base i Registers * F1:0x40 i = 0 * F1:0x48 i = 1 @@ -86,13 +86,13 @@ * that define the start of the DRAM region. */ /* don't touch it, we need it for CONFIG_CAR_FAM10 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, /* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -126,13 +126,13 @@ * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, + ADDRMAP_REG(0x84), 0x00000048, 0x00000000, + ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, + ADDRMAP_REG(0x94), 0x00000048, 0x00000000, + ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, + ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, + ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -160,13 +160,13 @@ * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -193,9 +193,9 @@ * This field defines the end of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, /* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -222,9 +222,9 @@ * This field defines the start of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, /* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -263,9 +263,9 @@ * This field defines the highest bus number in configuration regin i */ /* AMD 8111 on link0 of CPU 0 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, }; int max; diff --git a/src/mainboard/asus/kcma-d8/resourcemap.c b/src/mainboard/asus/kcma-d8/resourcemap.c index 0edc3d1..0dd0a9f 100644 --- a/src/mainboard/asus/kcma-d8/resourcemap.c +++ b/src/mainboard/asus/kcma-d8/resourcemap.c @@ -51,14 +51,14 @@ * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ - // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, + // ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, + ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, + ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, + ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, + ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, + ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, + ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, + ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, /* DRAM Base i Registers * F1:0x40 i = 0 @@ -90,14 +90,14 @@ * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ - // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, + // ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, /* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -131,14 +131,14 @@ * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00000000, + ADDRMAP_REG(0x84), 0x00000048, 0x00000000, + ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, + ADDRMAP_REG(0x94), 0x00000048, 0x00000000, + ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, + ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, + ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xBC), 0x00000048, 0x00000000, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -166,14 +166,14 @@ * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB8), 0x000000f0, 0x00000000, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -200,10 +200,10 @@ * This field defines the end of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff020, /* link 2 of CPU 0 --> AMD SR5690 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xC4), 0xFE000FC8, 0x00fff020, /* link 2 of CPU 0 --> AMD SR5690 */ + ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, /* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -230,10 +230,10 @@ * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, +// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00001013, + ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, /* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -271,10 +271,10 @@ * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000203, /* link 2 of CPU 0 --> AMD SR5690 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE0), 0x0000FC88, 0x05000203, /* link 2 of CPU 0 --> AMD SR5690 */ + ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, }; @@ -306,14 +306,14 @@ * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ - // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, + // ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, + ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, + ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, + ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, + ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, + ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, + ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, + ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, /* DRAM Base i Registers * F1:0x40 i = 0 @@ -345,14 +345,14 @@ * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ - // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, + // ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, /* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -386,14 +386,14 @@ * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00000000, + ADDRMAP_REG(0x84), 0x00000048, 0x00000000, + ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, + ADDRMAP_REG(0x94), 0x00000048, 0x00000000, + ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, + ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, + ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xBC), 0x00000048, 0x00000000, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -421,14 +421,14 @@ * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB8), 0x000000f0, 0x00000000, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -455,10 +455,10 @@ * This field defines the end of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff020, /* link 2 of CPU 0 --> AMD SR5690 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xC4), 0xFE000FC8, 0x00fff020, /* link 2 of CPU 0 --> AMD SR5690 */ + ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, /* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -485,10 +485,10 @@ * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, +// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00001013, + ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, /* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -526,10 +526,10 @@ * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000203, /* link 2 of CPU 0 --> AMD SR5690 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE0), 0x0000FC88, 0x05000203, /* link 2 of CPU 0 --> AMD SR5690 */ + ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, }; diff --git a/src/mainboard/asus/kfsn4-dre/resourcemap.c b/src/mainboard/asus/kfsn4-dre/resourcemap.c index 3591488..9efc60c 100644 --- a/src/mainboard/asus/kfsn4-dre/resourcemap.c +++ b/src/mainboard/asus/kfsn4-dre/resourcemap.c @@ -51,14 +51,14 @@ * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ - // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, + // ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, + ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, + ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, + ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, + ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, + ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, + ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, + ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, /* DRAM Base i Registers * F1:0x40 i = 0 @@ -90,14 +90,14 @@ * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ - // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, + // ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, /* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -131,14 +131,14 @@ * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00000000, + ADDRMAP_REG(0x84), 0x00000048, 0x00000000, + ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, + ADDRMAP_REG(0x94), 0x00000048, 0x00000000, + ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, + ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, + ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xBC), 0x00000048, 0x00000000, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -166,14 +166,14 @@ * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB8), 0x000000f0, 0x00000000, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -200,10 +200,10 @@ * This field defines the end of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff010, /* link 1 of CPU 0 --> Nvidia CK 804 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xC4), 0xFE000FC8, 0x00fff010, /* link 1 of CPU 0 --> Nvidia CK 804 */ + ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, /* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -230,10 +230,10 @@ * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, +// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00001013, + ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, /* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -271,10 +271,10 @@ * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000103, /* link 1 of CPU 0 --> Nvidia CK 804 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE0), 0x0000FC88, 0x05000103, /* link 1 of CPU 0 --> Nvidia CK 804 */ + ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, }; diff --git a/src/mainboard/asus/kgpe-d16/resourcemap.c b/src/mainboard/asus/kgpe-d16/resourcemap.c index b3c4465..cc3a23a 100644 --- a/src/mainboard/asus/kgpe-d16/resourcemap.c +++ b/src/mainboard/asus/kgpe-d16/resourcemap.c @@ -51,14 +51,14 @@ * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ - // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, + // ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, + ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, + ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, + ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, + ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, + ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, + ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, + ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, /* DRAM Base i Registers * F1:0x40 i = 0 @@ -90,14 +90,14 @@ * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ - // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, + // ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, /* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -131,14 +131,14 @@ * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00000000, + ADDRMAP_REG(0x84), 0x00000048, 0x00000000, + ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, + ADDRMAP_REG(0x94), 0x00000048, 0x00000000, + ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, + ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, + ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xBC), 0x00000048, 0x00000000, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -166,14 +166,14 @@ * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB8), 0x000000f0, 0x00000000, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -200,10 +200,10 @@ * This field defines the end of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff010, /* link 1 of CPU 0 --> AMD SR5690 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xC4), 0xFE000FC8, 0x00fff010, /* link 1 of CPU 0 --> AMD SR5690 */ + ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, /* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -230,10 +230,10 @@ * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, +// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00001013, + ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, /* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -271,10 +271,10 @@ * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000103, /* link 1 of CPU 0 --> AMD SR5690 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE0), 0x0000FC88, 0x05000103, /* link 1 of CPU 0 --> AMD SR5690 */ + ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, }; @@ -306,14 +306,14 @@ * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ - // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, + // ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, + ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, + ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, + ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, + ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, + ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, + ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, + ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, /* DRAM Base i Registers * F1:0x40 i = 0 @@ -345,14 +345,14 @@ * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ - // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, + // ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, /* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -386,14 +386,14 @@ * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00000000, + ADDRMAP_REG(0x84), 0x00000048, 0x00000000, + ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, + ADDRMAP_REG(0x94), 0x00000048, 0x00000000, + ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, + ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, + ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xBC), 0x00000048, 0x00000000, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -421,14 +421,14 @@ * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB8), 0x000000f0, 0x00000000, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -455,10 +455,10 @@ * This field defines the end of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff110, /* link 3 of CPU 0 --> AMD SR5690 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xC4), 0xFE000FC8, 0x00fff110, /* link 3 of CPU 0 --> AMD SR5690 */ + ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, /* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -485,10 +485,10 @@ * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, +// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00001013, + ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, /* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -526,10 +526,10 @@ * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000303, /* link 3 of CPU 0 --> AMD SR5690 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE0), 0x0000FC88, 0x05000303, /* link 3 of CPU 0 --> AMD SR5690 */ + ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, }; diff --git a/src/mainboard/asus/m4a78-em/resourcemap.c b/src/mainboard/asus/m4a78-em/resourcemap.c index a4a1d92..e7a8cbf 100644 --- a/src/mainboard/asus/m4a78-em/resourcemap.c +++ b/src/mainboard/asus/m4a78-em/resourcemap.c @@ -49,14 +49,14 @@ * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, +// ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 + ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, + ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, + ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, + ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, + ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, + ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, + ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, /* DRAM Base i Registers * F1:0x40 i = 0 * F1:0x48 i = 1 @@ -87,14 +87,14 @@ * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, +// ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 + ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, /* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -128,14 +128,14 @@ * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, + ADDRMAP_REG(0x84), 0x00000048, 0x00000000, + ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, + ADDRMAP_REG(0x94), 0x00000048, 0x00000000, + ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, + ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, + ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, +// ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -163,14 +163,14 @@ * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, + ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, +// ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -197,10 +197,10 @@ * This field defines the end of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, +// ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff000, + ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, /* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -227,10 +227,10 @@ * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, +// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000003, + ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, /* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -268,10 +268,10 @@ * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, +// ADDRMAP_REG(0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 + ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, }; int max; diff --git a/src/mainboard/asus/m4a785-m/resourcemap.c b/src/mainboard/asus/m4a785-m/resourcemap.c index a4a1d92..e7a8cbf 100644 --- a/src/mainboard/asus/m4a785-m/resourcemap.c +++ b/src/mainboard/asus/m4a785-m/resourcemap.c @@ -49,14 +49,14 @@ * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, +// ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 + ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, + ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, + ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, + ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, + ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, + ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, + ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, /* DRAM Base i Registers * F1:0x40 i = 0 * F1:0x48 i = 1 @@ -87,14 +87,14 @@ * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, +// ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 + ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, /* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -128,14 +128,14 @@ * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, + ADDRMAP_REG(0x84), 0x00000048, 0x00000000, + ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, + ADDRMAP_REG(0x94), 0x00000048, 0x00000000, + ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, + ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, + ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, +// ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -163,14 +163,14 @@ * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, + ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, +// ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -197,10 +197,10 @@ * This field defines the end of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, +// ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff000, + ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, /* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -227,10 +227,10 @@ * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, +// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000003, + ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, /* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -268,10 +268,10 @@ * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, +// ADDRMAP_REG(0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 + ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, }; int max; diff --git a/src/mainboard/asus/m5a88-v/resourcemap.c b/src/mainboard/asus/m5a88-v/resourcemap.c index 94ada1e..85ba50b 100644 --- a/src/mainboard/asus/m5a88-v/resourcemap.c +++ b/src/mainboard/asus/m5a88-v/resourcemap.c @@ -47,14 +47,14 @@ * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, +// ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 + ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, + ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, + ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, + ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, + ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, + ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, + ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, /* DRAM Base i Registers * F1:0x40 i = 0 * F1:0x48 i = 1 @@ -85,14 +85,14 @@ * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, +// ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 + ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, /* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -126,14 +126,14 @@ * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, + ADDRMAP_REG(0x84), 0x00000048, 0x00000000, + ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, + ADDRMAP_REG(0x94), 0x00000048, 0x00000000, + ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, + ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, + ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, +// ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -161,14 +161,14 @@ * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, + ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, +// ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -195,10 +195,10 @@ * This field defines the end of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, +// ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff000, + ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, /* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -225,10 +225,10 @@ * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, +// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000003, + ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, /* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -266,10 +266,10 @@ * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, +// ADDRMAP_REG(0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 + ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, }; int max; diff --git a/src/mainboard/avalue/eax-785e/resourcemap.c b/src/mainboard/avalue/eax-785e/resourcemap.c index 8390f49..ba264f3 100644 --- a/src/mainboard/avalue/eax-785e/resourcemap.c +++ b/src/mainboard/avalue/eax-785e/resourcemap.c @@ -48,13 +48,13 @@ * that define the end of the DRAM region. */ /* Don't touch it, we need it for CONFIG_CAR_FAM10 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, + ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, + ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, + ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, + ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, + ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, + ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, + ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, /* DRAM Base i Registers * F1:0x40 i = 0 * F1:0x48 i = 1 @@ -86,13 +86,13 @@ * that define the start of the DRAM region. */ /* don't touch it, we need it for CONFIG_CAR_FAM10 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, /* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -126,13 +126,13 @@ * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, + ADDRMAP_REG(0x84), 0x00000048, 0x00000000, + ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, + ADDRMAP_REG(0x94), 0x00000048, 0x00000000, + ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, + ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, + ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -160,13 +160,13 @@ * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -193,9 +193,9 @@ * This field defines the end of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, /* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -222,9 +222,9 @@ * This field defines the start of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, /* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -263,9 +263,9 @@ * This field defines the highest bus number in configuration regin i */ /* AMD 8111 on link0 of CPU 0 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, }; int max; diff --git a/src/mainboard/gigabyte/ma785gm/resourcemap.c b/src/mainboard/gigabyte/ma785gm/resourcemap.c index a4a1d92..e7a8cbf 100644 --- a/src/mainboard/gigabyte/ma785gm/resourcemap.c +++ b/src/mainboard/gigabyte/ma785gm/resourcemap.c @@ -49,14 +49,14 @@ * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, +// ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 + ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, + ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, + ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, + ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, + ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, + ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, + ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, /* DRAM Base i Registers * F1:0x40 i = 0 * F1:0x48 i = 1 @@ -87,14 +87,14 @@ * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, +// ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 + ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, /* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -128,14 +128,14 @@ * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, + ADDRMAP_REG(0x84), 0x00000048, 0x00000000, + ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, + ADDRMAP_REG(0x94), 0x00000048, 0x00000000, + ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, + ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, + ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, +// ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -163,14 +163,14 @@ * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, + ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, +// ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -197,10 +197,10 @@ * This field defines the end of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, +// ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff000, + ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, /* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -227,10 +227,10 @@ * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, +// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000003, + ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, /* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -268,10 +268,10 @@ * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, +// ADDRMAP_REG(0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 + ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, }; int max; diff --git a/src/mainboard/gigabyte/ma785gmt/resourcemap.c b/src/mainboard/gigabyte/ma785gmt/resourcemap.c index a4a1d92..e7a8cbf 100644 --- a/src/mainboard/gigabyte/ma785gmt/resourcemap.c +++ b/src/mainboard/gigabyte/ma785gmt/resourcemap.c @@ -49,14 +49,14 @@ * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, +// ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 + ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, + ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, + ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, + ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, + ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, + ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, + ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, /* DRAM Base i Registers * F1:0x40 i = 0 * F1:0x48 i = 1 @@ -87,14 +87,14 @@ * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, +// ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 + ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, /* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -128,14 +128,14 @@ * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, + ADDRMAP_REG(0x84), 0x00000048, 0x00000000, + ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, + ADDRMAP_REG(0x94), 0x00000048, 0x00000000, + ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, + ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, + ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, +// ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -163,14 +163,14 @@ * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, + ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, +// ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -197,10 +197,10 @@ * This field defines the end of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, +// ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff000, + ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, /* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -227,10 +227,10 @@ * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, +// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000003, + ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, /* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -268,10 +268,10 @@ * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, +// ADDRMAP_REG(0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 + ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, }; int max; diff --git a/src/mainboard/gigabyte/ma78gm/resourcemap.c b/src/mainboard/gigabyte/ma78gm/resourcemap.c index a4a1d92..e7a8cbf 100644 --- a/src/mainboard/gigabyte/ma78gm/resourcemap.c +++ b/src/mainboard/gigabyte/ma78gm/resourcemap.c @@ -49,14 +49,14 @@ * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, +// ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 + ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, + ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, + ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, + ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, + ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, + ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, + ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, /* DRAM Base i Registers * F1:0x40 i = 0 * F1:0x48 i = 1 @@ -87,14 +87,14 @@ * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, +// ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 + ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, /* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -128,14 +128,14 @@ * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, + ADDRMAP_REG(0x84), 0x00000048, 0x00000000, + ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, + ADDRMAP_REG(0x94), 0x00000048, 0x00000000, + ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, + ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, + ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, +// ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -163,14 +163,14 @@ * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, + ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, +// ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -197,10 +197,10 @@ * This field defines the end of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, +// ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff000, + ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, /* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -227,10 +227,10 @@ * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, +// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000003, + ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, /* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -268,10 +268,10 @@ * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, +// ADDRMAP_REG(0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 + ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, }; int max; diff --git a/src/mainboard/iei/kino-780am2-fam10/resourcemap.c b/src/mainboard/iei/kino-780am2-fam10/resourcemap.c index a4a1d92..e7a8cbf 100644 --- a/src/mainboard/iei/kino-780am2-fam10/resourcemap.c +++ b/src/mainboard/iei/kino-780am2-fam10/resourcemap.c @@ -49,14 +49,14 @@ * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, +// ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 + ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, + ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, + ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, + ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, + ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, + ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, + ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, /* DRAM Base i Registers * F1:0x40 i = 0 * F1:0x48 i = 1 @@ -87,14 +87,14 @@ * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, +// ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 + ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, /* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -128,14 +128,14 @@ * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, + ADDRMAP_REG(0x84), 0x00000048, 0x00000000, + ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, + ADDRMAP_REG(0x94), 0x00000048, 0x00000000, + ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, + ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, + ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, +// ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -163,14 +163,14 @@ * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, + ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, +// ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -197,10 +197,10 @@ * This field defines the end of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, +// ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff000, + ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, /* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -227,10 +227,10 @@ * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, +// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000003, + ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, /* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -268,10 +268,10 @@ * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, +// ADDRMAP_REG(0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 + ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, }; int max; diff --git a/src/mainboard/jetway/pa78vm5/resourcemap.c b/src/mainboard/jetway/pa78vm5/resourcemap.c index da7fc1b..1162d54 100644 --- a/src/mainboard/jetway/pa78vm5/resourcemap.c +++ b/src/mainboard/jetway/pa78vm5/resourcemap.c @@ -50,14 +50,14 @@ * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, +// ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 + ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, + ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, + ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, + ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, + ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, + ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, + ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, /* DRAM Base i Registers * F1:0x40 i = 0 * F1:0x48 i = 1 @@ -88,14 +88,14 @@ * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, +// ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 + ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, /* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -129,14 +129,14 @@ * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, + ADDRMAP_REG(0x84), 0x00000048, 0x00000000, + ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, + ADDRMAP_REG(0x94), 0x00000048, 0x00000000, + ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, + ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, + ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, +// ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -164,14 +164,14 @@ * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, + ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, +// ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -198,10 +198,10 @@ * This field defines the end of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, +// ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff000, + ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, /* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -228,10 +228,10 @@ * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, +// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000003, + ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, /* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -269,10 +269,10 @@ * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, +// ADDRMAP_REG(0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 + ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, }; int max; diff --git a/src/mainboard/msi/ms9652_fam10/resourcemap.c b/src/mainboard/msi/ms9652_fam10/resourcemap.c index 59155c6..7f8daac 100644 --- a/src/mainboard/msi/ms9652_fam10/resourcemap.c +++ b/src/mainboard/msi/ms9652_fam10/resourcemap.c @@ -49,14 +49,14 @@ * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ - // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CAR with FAM10 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, + // ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CAR with FAM10 + ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, + ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, + ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, + ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, + ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, + ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, + ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, /* DRAM Base i Registers * F1:0x40 i = 0 @@ -88,14 +88,14 @@ * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ - // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000, // don't touch it, we need it for CAR with FAM10 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, + // ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000, // don't touch it, we need it for CAR with FAM10 + ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, /* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -129,14 +129,14 @@ * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, + ADDRMAP_REG(0x84), 0x00000048, 0x00000000, + ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, + ADDRMAP_REG(0x94), 0x00000048, 0x00000000, + ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, + ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, + ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, +// ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -164,14 +164,14 @@ * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, + ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, +// ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -198,11 +198,11 @@ * This field defines the end of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00004000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, +// ADDRMAP_REG(0xC4), 0xFE000FC8, 0x00004000, + ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff000, + ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, /* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -230,11 +230,11 @@ * [31:25] Reserved */ /* Verified against board configuration registers after normal proprietary BIOS boot */ - //PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001033, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000033, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, + //ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00001033, + ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000033, + ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, /* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -273,10 +273,10 @@ * This field defines the highest bus number in configuration region i */ /* Verified against board configuration registers after normal proprietary BIOS boot */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of CPU 0 --> Nvidia MCP55 Pro */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE0), 0x0000FC88, 0xff000003, /* link 0 of CPU 0 --> Nvidia MCP55 Pro */ + ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, }; diff --git a/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c b/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c index 7dc4df1..55126d9 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c +++ b/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c @@ -49,14 +49,14 @@ * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ - // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CAR with FAM10 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, + // ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CAR with FAM10 + ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, + ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, + ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, + ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, + ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, + ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, + ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, /* DRAM Base i Registers * F1:0x40 i = 0 @@ -88,14 +88,14 @@ * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ - // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000, // don't touch it, we need it for CAR with FAM10 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, + // ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000, // don't touch it, we need it for CAR with FAM10 + ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, /* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -129,14 +129,14 @@ * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, + ADDRMAP_REG(0x84), 0x00000048, 0x00000000, + ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, + ADDRMAP_REG(0x94), 0x00000048, 0x00000000, + ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, + ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, + ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, +// ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -164,14 +164,14 @@ * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, + ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, +// ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -199,10 +199,10 @@ * [31:25] Reserved */ // WARD CHANGED - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff020, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, // need to talk to ANALOG of second CK804 to release PCI E reset - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff020, + ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, // need to talk to ANALOG of second CK804 to release PCI E reset + ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, /* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -230,10 +230,10 @@ * [31:25] Reserved */ // WARD CHANGED - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000033, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000033, + ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, /* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -272,10 +272,10 @@ * This field defines the highest bus number in configuration region i */ // WARD CHANGED - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of CPU 0 --> Nvidia MCP55 Pro */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE0), 0x0000FC88, 0x3f000203, /* link 2 of CPU 0 --> Nvidia MCP55 Pro */ + ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, }; diff --git a/src/mainboard/supermicro/h8qme_fam10/resourcemap.c b/src/mainboard/supermicro/h8qme_fam10/resourcemap.c index 7dc4df1..55126d9 100644 --- a/src/mainboard/supermicro/h8qme_fam10/resourcemap.c +++ b/src/mainboard/supermicro/h8qme_fam10/resourcemap.c @@ -49,14 +49,14 @@ * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ - // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CAR with FAM10 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, + // ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CAR with FAM10 + ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, + ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, + ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, + ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, + ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, + ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, + ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, /* DRAM Base i Registers * F1:0x40 i = 0 @@ -88,14 +88,14 @@ * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ - // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000, // don't touch it, we need it for CAR with FAM10 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, + // ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000, // don't touch it, we need it for CAR with FAM10 + ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, /* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -129,14 +129,14 @@ * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, + ADDRMAP_REG(0x84), 0x00000048, 0x00000000, + ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, + ADDRMAP_REG(0x94), 0x00000048, 0x00000000, + ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, + ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, + ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, +// ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -164,14 +164,14 @@ * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, + ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, +// ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -199,10 +199,10 @@ * [31:25] Reserved */ // WARD CHANGED - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff020, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, // need to talk to ANALOG of second CK804 to release PCI E reset - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff020, + ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, // need to talk to ANALOG of second CK804 to release PCI E reset + ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, /* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -230,10 +230,10 @@ * [31:25] Reserved */ // WARD CHANGED - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000033, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000033, + ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, /* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -272,10 +272,10 @@ * This field defines the highest bus number in configuration region i */ // WARD CHANGED - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of CPU 0 --> Nvidia MCP55 Pro */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE0), 0x0000FC88, 0x3f000203, /* link 2 of CPU 0 --> Nvidia MCP55 Pro */ + ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, }; diff --git a/src/mainboard/supermicro/h8scm_fam10/resourcemap.c b/src/mainboard/supermicro/h8scm_fam10/resourcemap.c index a4a1d92..e7a8cbf 100644 --- a/src/mainboard/supermicro/h8scm_fam10/resourcemap.c +++ b/src/mainboard/supermicro/h8scm_fam10/resourcemap.c @@ -49,14 +49,14 @@ * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, +// ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 + ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, + ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, + ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, + ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, + ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, + ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, + ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, /* DRAM Base i Registers * F1:0x40 i = 0 * F1:0x48 i = 1 @@ -87,14 +87,14 @@ * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, +// ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 + ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, /* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -128,14 +128,14 @@ * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, + ADDRMAP_REG(0x84), 0x00000048, 0x00000000, + ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, + ADDRMAP_REG(0x94), 0x00000048, 0x00000000, + ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, + ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, + ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, +// ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -163,14 +163,14 @@ * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, + ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, +// ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -197,10 +197,10 @@ * This field defines the end of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, +// ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff000, + ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, /* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -227,10 +227,10 @@ * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, +// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000003, + ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, /* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -268,10 +268,10 @@ * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, +// ADDRMAP_REG(0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 + ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, }; int max; diff --git a/src/mainboard/tyan/s2912_fam10/resourcemap.c b/src/mainboard/tyan/s2912_fam10/resourcemap.c index f02d6a7..51e257d 100644 --- a/src/mainboard/tyan/s2912_fam10/resourcemap.c +++ b/src/mainboard/tyan/s2912_fam10/resourcemap.c @@ -49,14 +49,14 @@ * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ - // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, + // ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, + ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, + ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, + ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, + ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, + ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, + ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, + ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, /* DRAM Base i Registers * F1:0x40 i = 0 @@ -88,14 +88,14 @@ * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ - // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, + // ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, /* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -129,14 +129,14 @@ * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, + ADDRMAP_REG(0x84), 0x00000048, 0x00000000, + ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, + ADDRMAP_REG(0x94), 0x00000048, 0x00000000, + ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, + ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, + ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, +// ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -164,14 +164,14 @@ * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, + ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, +// ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -198,10 +198,10 @@ * This field defines the end of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00007000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x01fff020, // need to talk to ANALOG of second CK804 to release PCI E reset - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, +// ADDRMAP_REG(0xC4), 0xFE000FC8, 0x00007000, +// ADDRMAP_REG(0xCC), 0xFE000FC8, 0x01fff020, // need to talk to ANALOG of second CK804 to release PCI E reset + ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, /* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -228,10 +228,10 @@ * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000033, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00008033, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, +// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000033, +// ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00008033, + ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, /* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -269,10 +269,10 @@ * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration region i */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x3f000003, /* link 0 of CPU 0 --> Nvidia MCP55 Pro */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of CPU 0 --> nvidia io55 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, +// ADDRMAP_REG(0xE0), 0x0000FC88, 0x3f000003, /* link 0 of CPU 0 --> Nvidia MCP55 Pro */ +// ADDRMAP_REG(0xE4), 0x0000FC88, 0x7f400203, /* link 2 of CPU 0 --> nvidia io55 */ + ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, }; diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index 163d9df..e1c88c9 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -26,6 +26,11 @@ struct DCTStatStruc; struct MCTStatStruc; + +/* Definitions for setup_resourcemap() variants. */ + +#define ADDRMAP_REG(r) PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, r) + #define RES_PCI_IO 0x10 #define RES_PORT_IO_8 0x22 #define RES_PORT_IO_32 0x20 diff --git a/src/northbridge/amd/amdfam10/resourcemap.c b/src/northbridge/amd/amdfam10/resourcemap.c index 362872b..fa4ab3c 100644 --- a/src/northbridge/amd/amdfam10/resourcemap.c +++ b/src/northbridge/amd/amdfam10/resourcemap.c @@ -45,14 +45,14 @@ * This field defines the upper address bits of a 40 bit * address that define the end of the DRAM region. */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, + ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, + ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, + ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, + ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, + ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, + ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, + ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, + ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, /* DRAM Base i Registers * F1:0x40 i = 0 * F1:0x48 i = 1 @@ -83,14 +83,14 @@ * This field defines the upper address bits of a 40-bit * address that define the start of the DRAM region. */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, /* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -125,14 +125,14 @@ * address that defines the end of a memory-mapped * I/O region n */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, + ADDRMAP_REG(0x84), 0x00000048, 0x00000000, + ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, + ADDRMAP_REG(0x94), 0x00000048, 0x00000000, + ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, + ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, + ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -161,14 +161,14 @@ * address that defines the start of memory-mapped * I/O region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, + ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -195,10 +195,10 @@ * This field defines the end of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff000, + ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, /* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -227,10 +227,10 @@ * This field defines the start of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000003, + ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, /* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -270,10 +270,10 @@ * This field defines the highest bus number in * configuration regin i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0xff000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE0), 0x0000FC88, 0xff000003, + ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, }; u32 max; -- To view, visit https://review.coreboot.org/c/coreboot/+/30783 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic146207580a5625c4f6799693157b02422bef00a Gerrit-Change-Number: 30783 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: sb/nvidia/mcp55: Avoid confusion with PCI_ADDR()
by Kyösti Mälkki (Code Review) 09 Jan '19

09 Jan '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30782 Change subject: sb/nvidia/mcp55: Avoid confusion with PCI_ADDR() ...................................................................... sb/nvidia/mcp55: Avoid confusion with PCI_ADDR() What you see in the table are not the PCI devices that will be written to. Use a helper MCP55_DEV() to make you look twice what is actually done. Change-Id: I1349af9f734aaabb576d1370ae29a56c91569a7c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/nvidia/mcp55/early_setup_car.c 1 file changed, 66 insertions(+), 61 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/30782/1 diff --git a/src/southbridge/nvidia/mcp55/early_setup_car.c b/src/southbridge/nvidia/mcp55/early_setup_car.c index 5289146..cc5e539 100644 --- a/src/southbridge/nvidia/mcp55/early_setup_car.c +++ b/src/southbridge/nvidia/mcp55/early_setup_car.c @@ -72,14 +72,19 @@ #define MCP55_CHIP_REV 3 +/* There will be implicit offsets applied, the writes below do not + * really happen at the PCI_ADDR() this expands to. + */ +#define MCP55_DEV(d, f, r) PCI_ADDR(0, d, f, r) + static void mcp55_early_set_port(unsigned mcp55_num, unsigned *busn, unsigned *devn, unsigned *io_base) { static const unsigned int ctrl_devport_conf[] = { - PCI_ADDR(0, 1, 1, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE, - PCI_ADDR(0, 1, 1, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE, - PCI_ADDR(0, 1, 1, ACPICTRL_REG_POS), ~(0x0000ff00), ACPICTRL_IO_BASE, + MCP55_DEV(1, 1, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE, + MCP55_DEV(1, 1, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE, + MCP55_DEV(1, 1, ACPICTRL_REG_POS), ~(0x0000ff00), ACPICTRL_IO_BASE, }; int j; @@ -94,9 +99,9 @@ unsigned *devn, unsigned *io_base) { static const unsigned int ctrl_devport_conf_clear[] = { - PCI_ADDR(0, 1, 1, ANACTRL_REG_POS), ~(0x0000ff00), 0, - PCI_ADDR(0, 1, 1, SYSCTRL_REG_POS), ~(0x0000ff00), 0, - PCI_ADDR(0, 1, 1, ACPICTRL_REG_POS), ~(0x0000ff00), 0, + MCP55_DEV(1, 1, ANACTRL_REG_POS), ~(0x0000ff00), 0, + MCP55_DEV(1, 1, SYSCTRL_REG_POS), ~(0x0000ff00), 0, + MCP55_DEV(1, 1, ACPICTRL_REG_POS), ~(0x0000ff00), 0, }; int j; @@ -174,70 +179,70 @@ RES_PORT_IO_32, ANACTRL_IO_BASE + 0x90, 0xFFFF00FF, 0x0000FF00, RES_PORT_IO_32, ANACTRL_IO_BASE + 0x9C, 0xFF00FFFF, 0x00070000, - RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x40), 0x00000000, 0xCB8410DE, - RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x48), 0xFFFFDCED, 0x00002002, - RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x78), 0xFFFFFF8E, 0x00000011, - RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x80), 0xFFFF0000, 0x00009923, - RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x88), 0xFFFFFFFE, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x8C), 0xFFFF0000, 0x0000007F, - RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xDC), 0xFFFEFFFF, 0x00010000, + RES_PCI_IO, MCP55_DEV(0, 0, 0x40), 0x00000000, 0xCB8410DE, + RES_PCI_IO, MCP55_DEV(0, 0, 0x48), 0xFFFFDCED, 0x00002002, + RES_PCI_IO, MCP55_DEV(0, 0, 0x78), 0xFFFFFF8E, 0x00000011, + RES_PCI_IO, MCP55_DEV(0, 0, 0x80), 0xFFFF0000, 0x00009923, + RES_PCI_IO, MCP55_DEV(0, 0, 0x88), 0xFFFFFFFE, 0x00000000, + RES_PCI_IO, MCP55_DEV(0, 0, 0x8C), 0xFFFF0000, 0x0000007F, + RES_PCI_IO, MCP55_DEV(0, 0, 0xDC), 0xFFFEFFFF, 0x00010000, - RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x40), 0x00000000, 0xCB8410DE, - RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x74), 0xFFFFFF7B, 0x00000084, - RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xF8), 0xFFFFFFCF, 0x00000010, + RES_PCI_IO, MCP55_DEV(1, 0, 0x40), 0x00000000, 0xCB8410DE, + RES_PCI_IO, MCP55_DEV(1, 0, 0x74), 0xFFFFFF7B, 0x00000084, + RES_PCI_IO, MCP55_DEV(1, 0, 0xF8), 0xFFFFFFCF, 0x00000010, - RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xC4), 0xFFFFFFFE, 0x00000001, - RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xF0), 0x7FFFFFFD, 0x00000002, - RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xF8), 0xFFFFFFCF, 0x00000010, + RES_PCI_IO, MCP55_DEV(1, 1, 0xC4), 0xFFFFFFFE, 0x00000001, + RES_PCI_IO, MCP55_DEV(1, 1, 0xF0), 0x7FFFFFFD, 0x00000002, + RES_PCI_IO, MCP55_DEV(1, 1, 0xF8), 0xFFFFFFCF, 0x00000010, - RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x40), 0x00000000, 0xCB8410DE, - RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x68), 0xFFFFFF00, 0x000000FF, - RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xF8), 0xFFFFFFBF, 0x00000040, /* Enable bridge mode. */ + RES_PCI_IO, MCP55_DEV(8, 0, 0x40), 0x00000000, 0xCB8410DE, + RES_PCI_IO, MCP55_DEV(8, 0, 0x68), 0xFFFFFF00, 0x000000FF, + RES_PCI_IO, MCP55_DEV(8, 0, 0xF8), 0xFFFFFFBF, 0x00000040, /* Enable bridge mode. */ - RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x40), 0x00000000, 0xCB8410DE, - RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x68), 0xFFFFFF00, 0x000000FF, - RES_PCI_IO, PCI_ADDR(0, 9, 0, 0xF8), 0xFFFFFFBF, 0x00000040, /* Enable bridge mode. */ + RES_PCI_IO, MCP55_DEV(9, 0, 0x40), 0x00000000, 0xCB8410DE, + RES_PCI_IO, MCP55_DEV(9, 0, 0x68), 0xFFFFFF00, 0x000000FF, + RES_PCI_IO, MCP55_DEV(9, 0, 0xF8), 0xFFFFFFBF, 0x00000040, /* Enable bridge mode. */ }; static const unsigned int ctrl_conf_1_1[] = { - RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x40), 0x00000000, 0xCB8410DE, - RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x50), 0xFFFFFFFC, 0x00000003, - RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x64), 0xFFFFFFFE, 0x00000001, - RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x70), 0xFFF0FFFF, 0x00040000, - RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xAC), 0xFFFFF0FF, 0x00000100, - RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x7C), 0xFFFFFFEF, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xC8), 0xFF00FF00, 0x000A000A, - RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xD0), 0xF0FFFFFF, 0x03000000, - RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xE0), 0xF0FFFFFF, 0x03000000, + RES_PCI_IO, MCP55_DEV(5, 0, 0x40), 0x00000000, 0xCB8410DE, + RES_PCI_IO, MCP55_DEV(5, 0, 0x50), 0xFFFFFFFC, 0x00000003, + RES_PCI_IO, MCP55_DEV(5, 0, 0x64), 0xFFFFFFFE, 0x00000001, + RES_PCI_IO, MCP55_DEV(5, 0, 0x70), 0xFFF0FFFF, 0x00040000, + RES_PCI_IO, MCP55_DEV(5, 0, 0xAC), 0xFFFFF0FF, 0x00000100, + RES_PCI_IO, MCP55_DEV(5, 0, 0x7C), 0xFFFFFFEF, 0x00000000, + RES_PCI_IO, MCP55_DEV(5, 0, 0xC8), 0xFF00FF00, 0x000A000A, + RES_PCI_IO, MCP55_DEV(5, 0, 0xD0), 0xF0FFFFFF, 0x03000000, + RES_PCI_IO, MCP55_DEV(5, 0, 0xE0), 0xF0FFFFFF, 0x03000000, }; static const unsigned int ctrl_conf_mcp55_only[] = { - RES_PCI_IO, PCI_ADDR(0, 1, 1, 0x40), 0x00000000, 0xCB8410DE, - RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE0), 0xFFFFFEFF, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE4), 0xFFFFFFFB, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE8), 0xFFA9C8FF, 0x00003000, + RES_PCI_IO, MCP55_DEV(1, 1, 0x40), 0x00000000, 0xCB8410DE, + RES_PCI_IO, MCP55_DEV(1, 1, 0xE0), 0xFFFFFEFF, 0x00000000, + RES_PCI_IO, MCP55_DEV(1, 1, 0xE4), 0xFFFFFFFB, 0x00000000, + RES_PCI_IO, MCP55_DEV(1, 1, 0xE8), 0xFFA9C8FF, 0x00003000, - RES_PCI_IO, PCI_ADDR(0, 4, 0, 0x40), 0x00000000, 0xCB8410DE, - RES_PCI_IO, PCI_ADDR(0, 4, 0, 0xF8), 0xFFFFFFCF, 0x00000010, + RES_PCI_IO, MCP55_DEV(4, 0, 0x40), 0x00000000, 0xCB8410DE, + RES_PCI_IO, MCP55_DEV(4, 0, 0xF8), 0xFFFFFFCF, 0x00000010, - RES_PCI_IO, PCI_ADDR(0, 2, 0, 0x40), 0x00000000, 0xCB8410DE, + RES_PCI_IO, MCP55_DEV(2, 0, 0x40), 0x00000000, 0xCB8410DE, - RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x40), 0x00000000, 0xCB8410DE, - RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x64), 0xF87FFFFF, 0x05000000, - RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x78), 0xFFC07FFF, 0x00360000, - RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x68), 0xFE00D03F, 0x013F2C00, - RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x70), 0xFFF7FFFF, 0x00080000, - RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x7C), 0xFFFFF00F, 0x00000570, - RES_PCI_IO, PCI_ADDR(0, 2, 1, 0xF8), 0xFFFFFFCF, 0x00000010, + RES_PCI_IO, MCP55_DEV(2, 1, 0x40), 0x00000000, 0xCB8410DE, + RES_PCI_IO, MCP55_DEV(2, 1, 0x64), 0xF87FFFFF, 0x05000000, + RES_PCI_IO, MCP55_DEV(2, 1, 0x78), 0xFFC07FFF, 0x00360000, + RES_PCI_IO, MCP55_DEV(2, 1, 0x68), 0xFE00D03F, 0x013F2C00, + RES_PCI_IO, MCP55_DEV(2, 1, 0x70), 0xFFF7FFFF, 0x00080000, + RES_PCI_IO, MCP55_DEV(2, 1, 0x7C), 0xFFFFF00F, 0x00000570, + RES_PCI_IO, MCP55_DEV(2, 1, 0xF8), 0xFFFFFFCF, 0x00000010, - RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x04), 0xFFFFFEFB, 0x00000104, - RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x3C), 0xF5FFFFFF, 0x0A000000, - RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x40), 0x00C8FFFF, 0x07330000, - RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x48), 0xFFFFFFF8, 0x00000005, - RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x4C), 0xFE02FFFF, 0x004C0000, - RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x74), 0xFFFFFFC0, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC0), 0x00000000, 0xCB8410DE, - RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC4), 0xFFFFFFF8, 0x00000007, + RES_PCI_IO, MCP55_DEV(6, 0, 0x04), 0xFFFFFEFB, 0x00000104, + RES_PCI_IO, MCP55_DEV(6, 0, 0x3C), 0xF5FFFFFF, 0x0A000000, + RES_PCI_IO, MCP55_DEV(6, 0, 0x40), 0x00C8FFFF, 0x07330000, + RES_PCI_IO, MCP55_DEV(6, 0, 0x48), 0xFFFFFFF8, 0x00000005, + RES_PCI_IO, MCP55_DEV(6, 0, 0x4C), 0xFE02FFFF, 0x004C0000, + RES_PCI_IO, MCP55_DEV(6, 0, 0x74), 0xFFFFFFC0, 0x00000000, + RES_PCI_IO, MCP55_DEV(6, 0, 0xC0), 0x00000000, 0xCB8410DE, + RES_PCI_IO, MCP55_DEV(6, 0, 0xC4), 0xFFFFFFF8, 0x00000007, #if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) /* * Avoid crash (complete with severe memory corruption!) during initial CAR boot @@ -247,11 +252,11 @@ * required to fix this is non-negligible and of unknown real-world benefit */ #else - RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xC0FFFFFF, 0x19000000, + RES_PCI_IO, MCP55_DEV(1, 0, 0x78), 0xC0FFFFFF, 0x19000000, #endif #if IS_ENABLED(CONFIG_MCP55_USE_AZA) - RES_PCI_IO, PCI_ADDR(0, 6, 1, 0x40), 0x00000000, 0xCB8410DE, + RES_PCI_IO, MCP55_DEV(6, 1, 0x40), 0x00000000, 0xCB8410DE, #endif @@ -277,15 +282,15 @@ static const unsigned int ctrl_conf_2[] = { /* I didn't put PCI-E related stuff here. */ - RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x74), 0xFFFFF00F, 0x000009D0, - RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x74), 0xFFFF7FFF, 0x00008000, + RES_PCI_IO, MCP55_DEV(0, 0, 0x74), 0xFFFFF00F, 0x000009D0, + RES_PCI_IO, MCP55_DEV(1, 0, 0x74), 0xFFFF7FFF, 0x00008000, RES_PORT_IO_32, SYSCTRL_IO_BASE + 0x48, 0xFFFEFFFF, 0x00010000, RES_PORT_IO_32, ANACTRL_IO_BASE + 0x60, 0xFFFFFF00, 0x00000012, #if IS_ENABLED(CONFIG_MCP55_USE_NIC) - RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xe4), ~((1 << 22) | (1 << 20)), (1 << 22) | (1 << 20), + RES_PCI_IO, MCP55_DEV(1, 1, 0xe4), ~((1 << 22) | (1 << 20)), (1 << 22) | (1 << 20), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), -- To view, visit https://review.coreboot.org/c/coreboot/+/30782 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1349af9f734aaabb576d1370ae29a56c91569a7c Gerrit-Change-Number: 30782 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: sb/nvidia/ck804: Avoid confusion with PCI_ADDR()
by Kyösti Mälkki (Code Review) 09 Jan '19

09 Jan '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30781 Change subject: sb/nvidia/ck804: Avoid confusion with PCI_ADDR() ...................................................................... sb/nvidia/ck804: Avoid confusion with PCI_ADDR() What you see in the table are not the PCI devices that will be written to. Use a helper CK804_DEV() to make you look twice what is actually done. Change-Id: I0ee244dacd6bbd0a88a5e6a5c634f381b0cf713d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/nvidia/ck804/early_setup_car.c 1 file changed, 83 insertions(+), 78 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/30781/1 diff --git a/src/southbridge/nvidia/ck804/early_setup_car.c b/src/southbridge/nvidia/ck804/early_setup_car.c index 266b97c..25faa35 100644 --- a/src/southbridge/nvidia/ck804/early_setup_car.c +++ b/src/southbridge/nvidia/ck804/early_setup_car.c @@ -68,12 +68,17 @@ * 16 4 :4 */ +/* There will be implicit offsets applied, the writes below do not + * really happen at the PCI_ADDR() this expands to. + */ +#define CK804_DEV(d, f, r) PCI_ADDR(0, d, f, r) + static void ck804_early_set_port(unsigned ck804_num, unsigned *busn, unsigned *io_base) { static const unsigned int ctrl_devport_conf[] = { - PCI_ADDR(0, 0x1, 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE, - PCI_ADDR(0, 0x1, 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE, + CK804_DEV(0x1, 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE, + CK804_DEV(0x1, 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE, }; int j; @@ -92,8 +97,8 @@ unsigned *io_base) { static const unsigned int ctrl_devport_conf_clear[] = { - PCI_ADDR(0, 0x1, 0, ANACTRL_REG_POS), ~(0x0000ff01), 0, - PCI_ADDR(0, 0x1, 0, SYSCTRL_REG_POS), ~(0x0000ff01), 0, + CK804_DEV(0x1, 0, ANACTRL_REG_POS), ~(0x0000ff01), 0, + CK804_DEV(0x1, 0, SYSCTRL_REG_POS), ~(0x0000ff01), 0, }; int j; @@ -112,26 +117,26 @@ unsigned *io_base) { static const unsigned int ctrl_conf_master[] = { - RES_PCI_IO, PCI_ADDR(0, 1, 2, 0x8c), 0xffff0000, 0x00009880, - RES_PCI_IO, PCI_ADDR(0, 1, 2, 0x90), 0xffff000f, 0x000074a0, - RES_PCI_IO, PCI_ADDR(0, 1, 2, 0xa0), 0xfffff0ff, 0x00000a00, - RES_PCI_IO, PCI_ADDR(0, 1, 2, 0xac), 0xffffff00, 0x00000000, + RES_PCI_IO, CK804_DEV(1, 2, 0x8c), 0xffff0000, 0x00009880, + RES_PCI_IO, CK804_DEV(1, 2, 0x90), 0xffff000f, 0x000074a0, + RES_PCI_IO, CK804_DEV(1, 2, 0xa0), 0xfffff0ff, 0x00000a00, + RES_PCI_IO, CK804_DEV(1, 2, 0xac), 0xffffff00, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x48), 0xfffffffd, 0x00000002, - RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x74), 0xfffff00f, 0x000009d0, - RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x8c), 0xffff0000, 0x0000007f, - RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xcc), 0xfffffff8, 0x00000003, - RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xd0), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xd4), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xd8), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xdc), 0x7f000000, 0x00000000, + RES_PCI_IO, CK804_DEV(0, 0, 0x48), 0xfffffffd, 0x00000002, + RES_PCI_IO, CK804_DEV(0, 0, 0x74), 0xfffff00f, 0x000009d0, + RES_PCI_IO, CK804_DEV(0, 0, 0x8c), 0xffff0000, 0x0000007f, + RES_PCI_IO, CK804_DEV(0, 0, 0xcc), 0xfffffff8, 0x00000003, + RES_PCI_IO, CK804_DEV(0, 0, 0xd0), 0xff000000, 0x00000000, + RES_PCI_IO, CK804_DEV(0, 0, 0xd4), 0xff000000, 0x00000000, + RES_PCI_IO, CK804_DEV(0, 0, 0xd8), 0xff000000, 0x00000000, + RES_PCI_IO, CK804_DEV(0, 0, 0xdc), 0x7f000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xf0), 0xfffffffd, 0x00000002, - RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xf8), 0xffffffcf, 0x00000010, + RES_PCI_IO, CK804_DEV(1, 0, 0xf0), 0xfffffffd, 0x00000002, + RES_PCI_IO, CK804_DEV(1, 0, 0xf8), 0xffffffcf, 0x00000010, - RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x40), 0xfff8ffff, 0x00030000, - RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x4c), 0xfe00ffff, 0x00440000, - RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x74), 0xffffffc0, 0x00000000, + RES_PCI_IO, CK804_DEV(9, 0, 0x40), 0xfff8ffff, 0x00030000, + RES_PCI_IO, CK804_DEV(9, 0, 0x4c), 0xfe00ffff, 0x00440000, + RES_PCI_IO, CK804_DEV(9, 0, 0x74), 0xffffffc0, 0x00000000, #ifdef CK804_MB_SETUP CK804_MB_SETUP @@ -146,9 +151,9 @@ * required to fix this is non-negligible and of unknown real-world benefit */ #else - RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xc0ffffff, 0x19000000, + RES_PCI_IO, CK804_DEV(1, 0, 0x78), 0xc0ffffff, 0x19000000, #endif - RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xe0), 0xfffffeff, 0x00000100, + RES_PCI_IO, CK804_DEV(1, 0, 0xe0), 0xfffffeff, 0x00000100, RES_PORT_IO_32, ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000, RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000, @@ -164,27 +169,27 @@ RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0, /* Activate master port on primary SATA controller. */ - RES_PCI_IO, PCI_ADDR(0, 7, 0, 0x50), ~(0x1f000013), 0x15000013, - RES_PCI_IO, PCI_ADDR(0, 7, 0, 0x64), ~(0x00000001), 0x00000001, - RES_PCI_IO, PCI_ADDR(0, 7, 0, 0x68), ~(0x02000000), 0x02000000, - RES_PCI_IO, PCI_ADDR(0, 7, 0, 0x70), ~(0x000f0000), 0x00040000, - RES_PCI_IO, PCI_ADDR(0, 7, 0, 0xa0), ~(0x000001ff), 0x00000150, - RES_PCI_IO, PCI_ADDR(0, 7, 0, 0xac), ~(0xffff8f00), 0x02aa8b00, - RES_PCI_IO, PCI_ADDR(0, 7, 0, 0x7c), ~(0x00000010), 0x00000000, - RES_PCI_IO, PCI_ADDR(0, 7, 0, 0xc8), ~(0x0fff0fff), 0x000a000a, - RES_PCI_IO, PCI_ADDR(0, 7, 0, 0xd0), ~(0xf0000000), 0x00000000, - RES_PCI_IO, PCI_ADDR(0, 7, 0, 0xe0), ~(0xf0000000), 0x00000000, + RES_PCI_IO, CK804_DEV(7, 0, 0x50), ~(0x1f000013), 0x15000013, + RES_PCI_IO, CK804_DEV(7, 0, 0x64), ~(0x00000001), 0x00000001, + RES_PCI_IO, CK804_DEV(7, 0, 0x68), ~(0x02000000), 0x02000000, + RES_PCI_IO, CK804_DEV(7, 0, 0x70), ~(0x000f0000), 0x00040000, + RES_PCI_IO, CK804_DEV(7, 0, 0xa0), ~(0x000001ff), 0x00000150, + RES_PCI_IO, CK804_DEV(7, 0, 0xac), ~(0xffff8f00), 0x02aa8b00, + RES_PCI_IO, CK804_DEV(7, 0, 0x7c), ~(0x00000010), 0x00000000, + RES_PCI_IO, CK804_DEV(7, 0, 0xc8), ~(0x0fff0fff), 0x000a000a, + RES_PCI_IO, CK804_DEV(7, 0, 0xd0), ~(0xf0000000), 0x00000000, + RES_PCI_IO, CK804_DEV(7, 0, 0xe0), ~(0xf0000000), 0x00000000, - RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x50), ~(0x1f000013), 0x15000013, - RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x64), ~(0x00000001), 0x00000001, - RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x68), ~(0x02000000), 0x02000000, - RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x70), ~(0x000f0000), 0x00040000, - RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xa0), ~(0x000001ff), 0x00000150, - RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xac), ~(0xffff8f00), 0x02aa8b00, - RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x7c), ~(0x00000010), 0x00000000, - RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xc8), ~(0x0fff0fff), 0x000a000a, - RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xd0), ~(0xf0000000), 0x00000000, - RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xe0), ~(0xf0000000), 0x00000000, + RES_PCI_IO, CK804_DEV(8, 0, 0x50), ~(0x1f000013), 0x15000013, + RES_PCI_IO, CK804_DEV(8, 0, 0x64), ~(0x00000001), 0x00000001, + RES_PCI_IO, CK804_DEV(8, 0, 0x68), ~(0x02000000), 0x02000000, + RES_PCI_IO, CK804_DEV(8, 0, 0x70), ~(0x000f0000), 0x00040000, + RES_PCI_IO, CK804_DEV(8, 0, 0xa0), ~(0x000001ff), 0x00000150, + RES_PCI_IO, CK804_DEV(8, 0, 0xac), ~(0xffff8f00), 0x02aa8b00, + RES_PCI_IO, CK804_DEV(8, 0, 0x7c), ~(0x00000010), 0x00000000, + RES_PCI_IO, CK804_DEV(8, 0, 0xc8), ~(0x0fff0fff), 0x000a000a, + RES_PCI_IO, CK804_DEV(8, 0, 0xd0), ~(0xf0000000), 0x00000000, + RES_PCI_IO, CK804_DEV(8, 0, 0xe0), ~(0xf0000000), 0x00000000, RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10), @@ -198,11 +203,11 @@ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 8, ~(0xff), ((0 << 4) | (0 << 2) | (0 << 0)), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 9, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), #if IS_ENABLED(CONFIG_CK804_USE_NIC) - RES_PCI_IO, PCI_ADDR(0, 0xa, 0, 0xf8), 0xffffffbf, 0x00000040, + RES_PCI_IO, CK804_DEV(0xa, 0, 0xf8), 0xffffffbf, 0x00000040, RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), - RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xe4), ~(1 << 23), (1 << 23), + RES_PCI_IO, CK804_DEV(1, 0, 0xe4), ~(1 << 23), (1 << 23), #endif #if IS_ENABLED(CONFIG_CK804_USE_ACI) @@ -211,9 +216,9 @@ #endif #if IS_ENABLED(CONFIG_CK804_PCIE_PME_WAKE) - RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xe4), 0xffffffff, 0x00400000, + RES_PCI_IO, CK804_DEV(1, 0, 0xe4), 0xffffffff, 0x00400000, #else - RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xe4), 0xffbfffff, 0x00000000, + RES_PCI_IO, CK804_DEV(1, 0, 0xe4), 0xffbfffff, 0x00000000, #endif }; @@ -222,33 +227,33 @@ }; static const unsigned int ctrl_conf_slave[] = { - RES_PCI_IO, PCI_ADDR(0, 1, 2, 0x8c), 0xffff0000, 0x00009880, - RES_PCI_IO, PCI_ADDR(0, 1, 2, 0x90), 0xffff000f, 0x000074a0, - RES_PCI_IO, PCI_ADDR(0, 1, 2, 0xa0), 0xfffff0ff, 0x00000a00, + RES_PCI_IO, CK804_DEV(1, 2, 0x8c), 0xffff0000, 0x00009880, + RES_PCI_IO, CK804_DEV(1, 2, 0x90), 0xffff000f, 0x000074a0, + RES_PCI_IO, CK804_DEV(1, 2, 0xa0), 0xfffff0ff, 0x00000a00, - RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x48), 0xfffffffd, 0x00000002, - RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x74), 0xfffff00f, 0x000009d0, - RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x8c), 0xffff0000, 0x0000007f, - RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xcc), 0xfffffff8, 0x00000003, - RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xd0), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xd4), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xd8), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xdc), 0x7f000000, 0x00000000, + RES_PCI_IO, CK804_DEV(0, 0, 0x48), 0xfffffffd, 0x00000002, + RES_PCI_IO, CK804_DEV(0, 0, 0x74), 0xfffff00f, 0x000009d0, + RES_PCI_IO, CK804_DEV(0, 0, 0x8c), 0xffff0000, 0x0000007f, + RES_PCI_IO, CK804_DEV(0, 0, 0xcc), 0xfffffff8, 0x00000003, + RES_PCI_IO, CK804_DEV(0, 0, 0xd0), 0xff000000, 0x00000000, + RES_PCI_IO, CK804_DEV(0, 0, 0xd4), 0xff000000, 0x00000000, + RES_PCI_IO, CK804_DEV(0, 0, 0xd8), 0xff000000, 0x00000000, + RES_PCI_IO, CK804_DEV(0, 0, 0xdc), 0x7f000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xf0), 0xfffffffd, 0x00000002, - RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xf8), 0xffffffcf, 0x00000010, + RES_PCI_IO, CK804_DEV(1, 0, 0xf0), 0xfffffffd, 0x00000002, + RES_PCI_IO, CK804_DEV(1, 0, 0xf8), 0xffffffcf, 0x00000010, - RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x40), 0xfff8ffff, 0x00030000, - RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x4c), 0xfe00ffff, 0x00440000, - RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x74), 0xffffffc0, 0x00000000, + RES_PCI_IO, CK804_DEV(9, 0, 0x40), 0xfff8ffff, 0x00030000, + RES_PCI_IO, CK804_DEV(9, 0, 0x4c), 0xfe00ffff, 0x00440000, + RES_PCI_IO, CK804_DEV(9, 0, 0x74), 0xffffffc0, 0x00000000, /* * Avoid touching 0x78 for CONFIG_NORTHBRIDGE_AMD_AMDFAM10 for * non-primary chains too??? */ - RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xc0ffffff, 0x20000000, - RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xe0), 0xfffffeff, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xe8), 0xffffff00, 0x000000ff, + RES_PCI_IO, CK804_DEV(1, 0, 0x78), 0xc0ffffff, 0x20000000, + RES_PCI_IO, CK804_DEV(1, 0, 0xe0), 0xfffffeff, 0x00000000, + RES_PCI_IO, CK804_DEV(1, 0, 0xe8), 0xffffff00, 0x000000ff, RES_PORT_IO_32, ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000, RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000, @@ -259,16 +264,16 @@ RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0, - RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x50), ~(0x1f000013), 0x15000013, - RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x64), ~(0x00000001), 0x00000001, - RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x68), ~(0x02000000), 0x02000000, - RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x70), ~(0x000f0000), 0x00040000, - RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xa0), ~(0x000001ff), 0x00000150, - RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xac), ~(0xffff8f00), 0x02aa8b00, - RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x7c), ~(0x00000010), 0x00000000, - RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xc8), ~(0x0fff0fff), 0x000a000a, - RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xd0), ~(0xf0000000), 0x00000000, - RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xe0), ~(0xf0000000), 0x00000000, + RES_PCI_IO, CK804_DEV(8, 0, 0x50), ~(0x1f000013), 0x15000013, + RES_PCI_IO, CK804_DEV(8, 0, 0x64), ~(0x00000001), 0x00000001, + RES_PCI_IO, CK804_DEV(8, 0, 0x68), ~(0x02000000), 0x02000000, + RES_PCI_IO, CK804_DEV(8, 0, 0x70), ~(0x000f0000), 0x00040000, + RES_PCI_IO, CK804_DEV(8, 0, 0xa0), ~(0x000001ff), 0x00000150, + RES_PCI_IO, CK804_DEV(8, 0, 0xac), ~(0xffff8f00), 0x02aa8b00, + RES_PCI_IO, CK804_DEV(8, 0, 0x7c), ~(0x00000010), 0x00000000, + RES_PCI_IO, CK804_DEV(8, 0, 0xc8), ~(0x0fff0fff), 0x000a000a, + RES_PCI_IO, CK804_DEV(8, 0, 0xd0), ~(0xf0000000), 0x00000000, + RES_PCI_IO, CK804_DEV(8, 0, 0xe0), ~(0xf0000000), 0x00000000, RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10), @@ -280,11 +285,11 @@ RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CONFIG_CK804B_PCI_E_X << 4) | (1 << 8), #if IS_ENABLED(CONFIG_CK804_USE_NIC) - RES_PCI_IO, PCI_ADDR(0, 0xa, 0, 0xf8), 0xffffffbf, 0x00000040, + RES_PCI_IO, CK804_DEV(0xa, 0, 0xf8), 0xffffffbf, 0x00000040, RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), - RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xe4), ~(1 << 23), (1 << 23), + RES_PCI_IO, CK804_DEV(1, 0, 0xe4), ~(1 << 23), (1 << 23), #endif }; -- To view, visit https://review.coreboot.org/c/coreboot/+/30781 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ee244dacd6bbd0a88a5e6a5c634f381b0cf713d Gerrit-Change-Number: 30781 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: amdfam10 boards: Drop extern on apicid_sp5100
by Kyösti Mälkki (Code Review) 09 Jan '19

09 Jan '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30780 Change subject: amdfam10 boards: Drop extern on apicid_sp5100 ...................................................................... amdfam10 boards: Drop extern on apicid_sp5100 The value get_bus_conf() initialises this value to is discarded. Change-Id: I8382861574e6f8ab52839169502a5af7c3742daa Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/asus/kcma-d8/get_bus_conf.c M src/mainboard/asus/kcma-d8/mptable.c M src/mainboard/asus/kgpe-d16/get_bus_conf.c M src/mainboard/asus/kgpe-d16/mptable.c M src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c M src/mainboard/supermicro/h8scm_fam10/mptable.c 6 files changed, 3 insertions(+), 48 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/30780/1 diff --git a/src/mainboard/asus/kcma-d8/get_bus_conf.c b/src/mainboard/asus/kcma-d8/get_bus_conf.c index 3a9eb9e..30be038 100644 --- a/src/mainboard/asus/kcma-d8/get_bus_conf.c +++ b/src/mainboard/asus/kcma-d8/get_bus_conf.c @@ -22,12 +22,6 @@ #include <cpu/amd/amdfam10_sysconf.h> -/* Global variables for MB layouts and these will be shared by irqtable mptable -* and acpi_tables busnum is default. -*/ -u32 apicid_sp5100; - - void get_bus_conf(void) { u32 apicid_base; @@ -36,11 +30,4 @@ sysconf.sbdn = (sysconf.hcdn[0] & 0xff); pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff; - - /* I/O APICs: APIC ID Version State Address */ - if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) - apicid_base = get_apicid_base(1); - else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; - apicid_sp5100 = apicid_base + 0; } diff --git a/src/mainboard/asus/kcma-d8/mptable.c b/src/mainboard/asus/kcma-d8/mptable.c index 54cf5ed..22dbd1a 100644 --- a/src/mainboard/asus/kcma-d8/mptable.c +++ b/src/mainboard/asus/kcma-d8/mptable.c @@ -21,14 +21,11 @@ #include <stdint.h> #include <cpu/amd/amdfam10_sysconf.h> -extern u32 apicid_sp5100; - - - static void *smp_write_config_table(void *v) { struct mp_config_table *mc; int bus_isa; + u32 apicid_sp5100; u32 apicid_sr5650; struct device *dev; uint8_t sp5100_bus_number; diff --git a/src/mainboard/asus/kgpe-d16/get_bus_conf.c b/src/mainboard/asus/kgpe-d16/get_bus_conf.c index 903e7e1..9264720 100644 --- a/src/mainboard/asus/kgpe-d16/get_bus_conf.c +++ b/src/mainboard/asus/kgpe-d16/get_bus_conf.c @@ -22,26 +22,12 @@ #include <cpu/amd/amdfam10_sysconf.h> -/* Global variables for MB layouts and these will be shared by irqtable mptable -* and acpi_tables busnum is default. -*/ -u32 apicid_sp5100; - void get_bus_conf(void) { - u32 apicid_base; - get_default_pci1234(1); sysconf.sbdn = (sysconf.hcdn[0] & 0xff); pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff; - - /* I/O APICs: APIC ID Version State Address */ - if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) - apicid_base = get_apicid_base(1); - else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; - apicid_sp5100 = apicid_base + 0; } diff --git a/src/mainboard/asus/kgpe-d16/mptable.c b/src/mainboard/asus/kgpe-d16/mptable.c index 3b7ff52..e91a424 100644 --- a/src/mainboard/asus/kgpe-d16/mptable.c +++ b/src/mainboard/asus/kgpe-d16/mptable.c @@ -21,14 +21,11 @@ #include <stdint.h> #include <cpu/amd/amdfam10_sysconf.h> -extern u32 apicid_sp5100; - - - static void *smp_write_config_table(void *v) { struct mp_config_table *mc; int bus_isa; + u32 apicid_sp5100; u32 apicid_sr5650; struct device *dev; uint8_t sp5100_bus_number; diff --git a/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c index 7153f79..f6ea933 100644 --- a/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c +++ b/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c @@ -25,11 +25,9 @@ * and acpi_tables busnum is default. */ u8 bus_sr5650[14]; -u32 apicid_sp5100; void get_bus_conf(void) { - u32 apicid_base; struct device *dev; int i; @@ -54,11 +52,4 @@ } } } - - /* I/O APICs: APIC ID Version State Address */ - if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) - apicid_base = get_apicid_base(1); - else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; - apicid_sp5100 = apicid_base + 0; } diff --git a/src/mainboard/supermicro/h8scm_fam10/mptable.c b/src/mainboard/supermicro/h8scm_fam10/mptable.c index 22f064a..ca91368 100644 --- a/src/mainboard/supermicro/h8scm_fam10/mptable.c +++ b/src/mainboard/supermicro/h8scm_fam10/mptable.c @@ -22,14 +22,11 @@ extern u8 bus_sr5650[14]; -extern u32 apicid_sp5100; - - - static void *smp_write_config_table(void *v) { struct mp_config_table *mc; int bus_isa; + u32 apicid_sp5100; u32 apicid_sr5650; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); -- To view, visit https://review.coreboot.org/c/coreboot/+/30780 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8382861574e6f8ab52839169502a5af7c3742daa Gerrit-Change-Number: 30780 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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