coreboot-gerrit January 2019

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Change in ...coreboot[master]: southbridge/nvidia/ck804: Drop leftover code
by Kyösti Mälkki (Code Review) 08 Jan '19

08 Jan '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30736 Change subject: southbridge/nvidia/ck804: Drop leftover code ...................................................................... southbridge/nvidia/ck804: Drop leftover code Code was for romcc romstage. Change-Id: If368610651ce950169ef71d9ed768a509c2a5c5c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/nvidia/ck804/Kconfig M src/southbridge/nvidia/ck804/ck804.h D src/southbridge/nvidia/ck804/early_setup.c 3 files changed, 0 insertions(+), 339 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/30736/1 diff --git a/src/southbridge/nvidia/ck804/Kconfig b/src/southbridge/nvidia/ck804/Kconfig index 203890b..f931d48 100644 --- a/src/southbridge/nvidia/ck804/Kconfig +++ b/src/southbridge/nvidia/ck804/Kconfig @@ -34,10 +34,6 @@ bool "Enable system wake on PCIe PME# signal" default n -config CK804_NUM - int - default 1 - config HPET_MIN_TICKS hex default 0xfa diff --git a/src/southbridge/nvidia/ck804/ck804.h b/src/southbridge/nvidia/ck804/ck804.h index 405211a..fc99d9a 100644 --- a/src/southbridge/nvidia/ck804/ck804.h +++ b/src/southbridge/nvidia/ck804/ck804.h @@ -26,11 +26,6 @@ #define CK804B_BUSN 0x80 #define CK804B_DEVN_BASE (!CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY ? CK804_DEVN_BASE : 1) -#if CONFIG_CK804_NUM > 1 -#define CK804B_ANACTRL_IO_BASE (ANACTRL_IO_BASE + 0x8000) -#define CK804B_SYSCTRL_IO_BASE (SYSCTRL_IO_BASE + 0x8000) -#endif - #ifdef __PRE_RAM__ void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); #endif diff --git a/src/southbridge/nvidia/ck804/early_setup.c b/src/southbridge/nvidia/ck804/early_setup.c deleted file mode 100644 index f2121f0..0000000 --- a/src/southbridge/nvidia/ck804/early_setup.c +++ /dev/null @@ -1,330 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <reset.h> -#include <southbridge/amd/common/reset.h> -#include "ck804.h" - -static int set_ht_link_ck804(u8 ht_c_num) -{ - unsigned vendorid = 0x10de; - unsigned val = 0x01610169; - return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val); -} - -static void setup_ss_table(unsigned index, unsigned where, unsigned control, - const unsigned int *register_values, int max) -{ - int i; - unsigned val; - - val = inl(control); - val &= 0xfffffffe; - outl(val, control); - - outl(0, index); - - for (i = 0; i < max; i++) { - unsigned long reg; - reg = register_values[i]; - outl(reg, where); - } - val = inl(control); - val |= 1; - outl(val, control); -} - -#define ANACTRL_IO_BASE 0x7000 -#define ANACTRL_REG_POS 0x68 - -#define SYSCTRL_IO_BASE 0x6000 -#define SYSCTRL_REG_POS 0x64 - -/* - * Values for CONFIG_CK804_PCI_E_X and CONFIG_CK804B_PCI_E_X. - * Apparently some sort of lane configuration. - * - * 16 1 1 2 :0 - * 8 8 2 2 :1 - * 8 8 4 :2 - * 8 4 4 4 :3 - * 16 4 :4 - */ - -static void ck804_early_set_port(void) -{ - static const unsigned int ctrl_devport_conf[] = { - PCI_ADDR(0, (CK804_DEVN_BASE + 0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE, -#if CONFIG_CK804_NUM > 1 - PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), CK804B_ANACTRL_IO_BASE, -#endif - - PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE, -#if CONFIG_CK804_NUM > 1 - PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), CK804B_SYSCTRL_IO_BASE, -#endif - }; - - setup_resource_map(ctrl_devport_conf, ARRAY_SIZE(ctrl_devport_conf)); -} - -static void ck804_early_clear_port(void) -{ - static const unsigned int ctrl_devport_conf_clear[] = { - PCI_ADDR(0, (CK804_DEVN_BASE + 0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0, -#if CONFIG_CK804_NUM > 1 - PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0, -#endif - PCI_ADDR(0, (CK804_DEVN_BASE + 0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0, -#if CONFIG_CK804_NUM > 1 - PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0, -#endif - }; - - setup_resource_map(ctrl_devport_conf_clear, ARRAY_SIZE(ctrl_devport_conf_clear)); -} - -static void ck804_early_setup(void) -{ - static const unsigned int ctrl_conf[] = { - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0x8c), 0xffff0000, 0x00009880, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0x90), 0xffff000f, 0x000074a0, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0xa0), 0xfffff0ff, 0x00000a00, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0xac), 0xffffff00, 0x00000000, - -#if CONFIG_CK804_NUM > 1 - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0x8c), 0xffff0000, 0x00009880, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0x90), 0xffff000f, 0x000074a0, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0xa0), 0xfffff0ff, 0x00000a00, -#endif - - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0x48), 0xfffffffd, 0x00000002, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0x74), 0xfffff00f, 0x000009d0, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0x8c), 0xffff0000, 0x0000007f, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xcc), 0xfffffff8, 0x00000003, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xd0), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xd4), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xd8), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xdc), 0x7f000000, 0x00000000, - -#if CONFIG_CK804_NUM > 1 - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x48), 0xfffffffd, 0x00000002, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x74), 0xfffff00f, 0x000009d0, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x8c), 0xffff0000, 0x0000007f, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xcc), 0xfffffff8, 0x00000003, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xd0), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xd4), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xd8), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xdc), 0x7f000000, 0x00000000, -#endif - - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xf0), 0xfffffffd, 0x00000002, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xf8), 0xffffffcf, 0x00000010, - -#if CONFIG_CK804_NUM > 1 - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xf0), 0xfffffffd, 0x00000002, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xf8), 0xffffffcf, 0x00000010, -#endif - - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 9, 0, 0x40), 0xfff8ffff, 0x00030000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 9, 0, 0x4c), 0xfe00ffff, 0x00440000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 9, 0, 0x74), 0xffffffc0, 0x00000000, - -#if CONFIG_CK804_NUM > 1 - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x40), 0xfff8ffff, 0x00030000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x4c), 0xfe00ffff, 0x00440000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x74), 0xffffffc0, 0x00000000, -#endif - -#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) - /* - * Avoid crash (complete with severe memory corruption!) during initial CAR boot - * in ck804_early_setup_x() on Fam10h systems by not touching 0x78. - * Interestingly once the system is fully booted into Linux this can be set, but - * not before! Apparently something isn't initialized but the amount of effort - * required to fix this is non-negligible and of unknown real-world benefit - */ -#else - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0x78), 0xc0ffffff, 0x19000000, -#endif - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xe0), 0xfffffeff, 0x00000100, - -#if CONFIG_CK804_NUM > 1 - /* - * Avoid touching 0x78 for CONFIG_NORTHBRIDGE_AMD_AMDFAM10 for - * non-primary chain too??? - */ - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0x78), 0xc0ffffff, 0x20000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe0), 0xfffffeff, 0x00000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe8), 0xffffff00, 0x000000ff, -#endif - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000, - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x74, ~(0xffff), 0x0f008, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, ~((0xff) | (0xff << 16)), (0x41 << 16) | (0x32), - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7c, ~(0xff << 16), (0xa0 << 16), - -#if CONFIG_CK804_NUM > 1 - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000, - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000, - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120, - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010, - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000, - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000, -#endif - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0, -#if CONFIG_CK804_NUM > 1 - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0, -#endif - - /* Activate master port on primary SATA controller. */ - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0x50), ~(0x1f000013), 0x15000013, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0x64), ~(0x00000001), 0x00000001, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0x68), ~(0x02000000), 0x02000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0x70), ~(0x000f0000), 0x00040000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0xa0), ~(0x000001ff), 0x00000150, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0xac), ~(0xffff8f00), 0x02aa8b00, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0x7c), ~(0x00000010), 0x00000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0xc8), ~(0x0fff0fff), 0x000a000a, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0xd0), ~(0xf0000000), 0x00000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0xe0), ~(0xf0000000), 0x00000000, - - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x50), ~(0x1f000013), 0x15000013, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x64), ~(0x00000001), 0x00000001, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x68), ~(0x02000000), 0x02000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x70), ~(0x000f0000), 0x00040000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xa0), ~(0x000001ff), 0x00000150, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xac), ~(0xffff8f00), 0x02aa8b00, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x7c), ~(0x00000010), 0x00000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xc8), ~(0x0fff0fff), 0x000a000a, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xd0), ~(0xf0000000), 0x00000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xe0), ~(0xf0000000), 0x00000000, -#if CONFIG_CK804_NUM > 1 - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x50), ~(0x1f000013), 0x15000013, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x64), ~(0x00000001), 0x00000001, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x68), ~(0x02000000), 0x02000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x70), ~(0x000f0000), 0x00040000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xa0), ~(0x000001ff), 0x00000150, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xac), ~(0xffff8f00), 0x02aa8b00, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x7c), ~(0x00000010), 0x00000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xc8), ~(0x0fff0fff), 0x000a000a, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xd0), ~(0xf0000000), 0x00000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xe0), ~(0xf0000000), 0x00000000, -#endif - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10), -#if CONFIG_CK804_NUM > 1 - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10), -#endif - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b, -#if CONFIG_CK804_NUM > 1 - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b, -#endif - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000, - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CONFIG_CK804_PCI_E_X << 4) | (1 << 8), -#if CONFIG_CK804_NUM > 1 - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CONFIG_CK804B_PCI_E_X << 4) | (1 << 8), -#endif - - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 8, ~(0xff), ((0 << 4) | (0 << 2) | (0 << 0)), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 9, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), -#if IS_ENABLED(CONFIG_CK804_USE_NIC) - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE +0xa, 0, 0xf8), 0xffffffbf, 0x00000040, - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xe4), ~(1 << 23), (1 << 23), -#endif - -#if IS_ENABLED(CONFIG_CK804_USE_ACI) - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x0d, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x1a, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)), -#endif - -#if CONFIG_CK804_NUM > 1 - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0, ~(3 << 2), (0 << 2), -#endif - -#if CONFIG_CK804_NUM > 1 -#if IS_ENABLED(CONFIG_CK804_USE_NIC) - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE +0xa, 0, 0xf8), 0xffffffbf, 0x00000040, - RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), - RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), - RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe4), ~(1 << 23), (1 << 23), -#endif -#endif - -#if IS_ENABLED(CONFIG_CK804_PCIE_PME_WAKE) - RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xe4), 0xffffffff, 0x00400000, -#else - RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xe4), 0xffbfffff, 0x00000000, -#endif - -#ifdef CK804_MB_SETUP - CK804_MB_SETUP -#endif - }; - - setup_resource_map_x(ctrl_conf, ARRAY_SIZE(ctrl_conf)); - - setup_ss_table(ANACTRL_IO_BASE + 0x40, ANACTRL_IO_BASE + 0x44, ANACTRL_IO_BASE + 0x48, pcie_ss_tbl, 64); - setup_ss_table(ANACTRL_IO_BASE + 0xb0, ANACTRL_IO_BASE + 0xb4, ANACTRL_IO_BASE + 0xb8, sata_ss_tbl, 64); - setup_ss_table(ANACTRL_IO_BASE + 0xc0, ANACTRL_IO_BASE + 0xc4, ANACTRL_IO_BASE + 0xc8, cpu_ss_tbl, 64); - -#if CONFIG_CK804_NUM > 1 - setup_ss_table(CK804B_ANACTRL_IO_BASE + 0x40, CK804B_ANACTRL_IO_BASE + 0x44, CK804B_ANACTRL_IO_BASE + 0x48, pcie_ss_tbl, 64); - setup_ss_table(CK804B_ANACTRL_IO_BASE + 0xb0, CK804B_ANACTRL_IO_BASE + 0xb4, CK804B_ANACTRL_IO_BASE + 0xb8, sata_ss_tbl, 64); - setup_ss_table(CK804B_ANACTRL_IO_BASE + 0xc0, CK804B_ANACTRL_IO_BASE + 0xc4, CK804B_ANACTRL_IO_BASE + 0xc8, cpu_ss_tbl, 64); -#endif - -} - -static int ck804_early_setup_x(void) -{ - ck804_early_set_port(); - ck804_early_setup(); - ck804_early_clear_port(); - return set_ht_link_ck804(4); -} - -void do_board_reset(void) -{ - set_bios_reset(); - - /* full reset */ - outb(0x0a, 0x0cf9); - outb(0x0e, 0x0cf9); -} - -void do_soft_reset(void) -{ - set_bios_reset(); - - /* link reset */ - outb(0x02, 0x0cf9); - outb(0x06, 0x0cf9); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/30736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If368610651ce950169ef71d9ed768a509c2a5c5c Gerrit-Change-Number: 30736 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: binaryPI: Drop warning on EXT_CONF_SUPPORT
by Kyösti Mälkki (Code Review) 08 Jan '19

08 Jan '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30730 Change subject: binaryPI: Drop warning on EXT_CONF_SUPPORT ...................................................................... binaryPI: Drop warning on EXT_CONF_SUPPORT Copy-paste from fam15 code. Change-Id: Ic52031c57a8b659bff5ca03a66ec2291140d2233 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/amd/pi/00630F01/Kconfig M src/cpu/amd/pi/00660F01/Kconfig M src/northbridge/amd/pi/00630F01/northbridge.c M src/northbridge/amd/pi/00660F01/northbridge.c 4 files changed, 0 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/30730/1 diff --git a/src/cpu/amd/pi/00630F01/Kconfig b/src/cpu/amd/pi/00630F01/Kconfig index cb0d53c..f3ed237 100644 --- a/src/cpu/amd/pi/00630F01/Kconfig +++ b/src/cpu/amd/pi/00630F01/Kconfig @@ -23,10 +23,6 @@ int default 48 -config EXT_CONF_SUPPORT - bool - default n - config CBB hex default 0x0 diff --git a/src/cpu/amd/pi/00660F01/Kconfig b/src/cpu/amd/pi/00660F01/Kconfig index 96eb179..d57cfb1 100644 --- a/src/cpu/amd/pi/00660F01/Kconfig +++ b/src/cpu/amd/pi/00660F01/Kconfig @@ -23,10 +23,6 @@ int default 48 -config EXT_CONF_SUPPORT - bool - default n - config CBB hex default 0x0 diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index ecd259e..11158d0 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -44,10 +44,6 @@ #define MAX_NODE_NUMS MAX_NODES -#if IS_ENABLED(CONFIG_EXT_CONF_SUPPORT) -#error CONFIG_EXT_CONF_SUPPORT == 1 not support anymore! -#endif - typedef struct dram_base_mask { u32 base; //[47:27] at [28:8] u32 mask; //[47:27] at [28:8] and enable at bit 0 diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index 427e99e..d107964 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -42,10 +42,6 @@ #define MAX_NODE_NUMS MAX_NODES -#if IS_ENABLED(CONFIG_EXT_CONF_SUPPORT) -#error CONFIG_EXT_CONF_SUPPORT == 1 not support anymore! -#endif - typedef struct dram_base_mask { u32 base; //[47:27] at [28:8] u32 mask; //[47:27] at [28:8] and enable at bit 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/30730 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic52031c57a8b659bff5ca03a66ec2291140d2233 Gerrit-Change-Number: 30730 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mainboard/amd: Drop incorrect Kconfig select
by Kyösti Mälkki (Code Review) 08 Jan '19

08 Jan '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30729 Change subject: mainboard/amd: Drop incorrect Kconfig select ...................................................................... mainboard/amd: Drop incorrect Kconfig select Copy-paste from fam15. Change-Id: I87af312870063aaa498bbfc2f059f69dcdab0094 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/amd/inagua/Kconfig M src/mainboard/amd/torpedo/Kconfig 2 files changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/30729/1 diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig index 4f4a3f1..6d6ec4f 100644 --- a/src/mainboard/amd/inagua/Kconfig +++ b/src/mainboard/amd/inagua/Kconfig @@ -26,7 +26,6 @@ select HAVE_MP_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_2048 - select ENABLE_APIC_EXT_ID select GFXUMA config MAINBOARD_DIR diff --git a/src/mainboard/amd/torpedo/Kconfig b/src/mainboard/amd/torpedo/Kconfig index 88bc90c..7f72c0b 100644 --- a/src/mainboard/amd/torpedo/Kconfig +++ b/src/mainboard/amd/torpedo/Kconfig @@ -26,7 +26,6 @@ select HAVE_MP_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_2048 - select ENABLE_APIC_EXT_ID select GFXUMA config MAINBOARD_DIR -- To view, visit https://review.coreboot.org/c/coreboot/+/30729 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87af312870063aaa498bbfc2f059f69dcdab0094 Gerrit-Change-Number: 30729 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: southbridge/amd/cimx: Drop unused functions
by Kyösti Mälkki (Code Review) 08 Jan '19

08 Jan '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30728 Change subject: southbridge/amd/cimx: Drop unused functions ...................................................................... southbridge/amd/cimx: Drop unused functions Leftovers from attempts of using these with native (non-AGESA) amdfam10/15 support code. Change-Id: I8eaed338438e1de5baee462376e339e1439f72f1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/amd/cimx/sb800/early.c M src/southbridge/amd/cimx/sb800/late.c M src/southbridge/amd/cimx/sb800/sb_cimx.h M src/southbridge/amd/cimx/sb900/early.c M src/southbridge/amd/cimx/sb900/sb_cimx.h 5 files changed, 0 insertions(+), 65 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/30728/1 diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c index 3e2c10a..adc69d8 100644 --- a/src/southbridge/amd/cimx/sb800/early.c +++ b/src/southbridge/amd/cimx/sb800/early.c @@ -22,25 +22,6 @@ #include "cbmem.h" /** - * @brief Get SouthBridge device number - * @param[in] bus target bus number - * @return southbridge device number - */ -u32 get_sbdn(u32 bus) -{ - pci_devfn_t dev; - - printk(BIOS_DEBUG, "SB800 - %s - %s - Start.\n", __FILE__, __func__); - //dev = PCI_DEV(bus, 0x14, 0); - dev = pci_locate_device_on_bus( - PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB800_SM), - bus); - - printk(BIOS_DEBUG, "SB800 - %s - %s - End.\n", __FILE__, __func__); - return (dev >> 15) & 0x1f; -} - -/** * @brief South Bridge CIMx romstage entry, * wrapper of sbPowerOnInit entry point. */ diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index e3390d5..c66206f 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -364,22 +364,8 @@ case PCI_DEVFN(0x14, 0): /* 0:14:0 SMBUS */ clear_ioapic(VIO_APIC_VADDR); -#if IS_ENABLED(CONFIG_CPU_AMD_AGESA) /* Assign the ioapic ID the next available number after the processor core local APIC IDs */ setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS); -#else - /* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */ -#if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS < 16) - /* Assign the ioapic ID the next available number after the processor core local APIC IDs */ - setup_ioapic(VIO_APIC_VADDR, - CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS); -#elif (CONFIG_APIC_ID_OFFSET > 0) - /* Assign the ioapic ID the value 0. Processor APIC IDs follow. */ - setup_ioapic(VIO_APIC_VADDR, 0); -#else -#error "The processor APIC IDs must be lifted to make room for the I/O APIC ID" -#endif -#endif break; case PCI_DEVFN(0x14, 1): /* 0:14:1 IDE */ diff --git a/src/southbridge/amd/cimx/sb800/sb_cimx.h b/src/southbridge/amd/cimx/sb800/sb_cimx.h index 16ac6fe..6c924ca 100644 --- a/src/southbridge/amd/cimx/sb800/sb_cimx.h +++ b/src/southbridge/amd/cimx/sb800/sb_cimx.h @@ -34,10 +34,4 @@ */ void sb800_clk_output_48Mhz(void); -/** - * @brief Get SouthBridge device number, called by finalize_node_setup() - * @param[in] bus target bus number - * @return southbridge device number - */ -u32 get_sbdn(u32 bus); #endif diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c index 96f5e33..6fe133b 100644 --- a/src/southbridge/amd/cimx/sb900/early.c +++ b/src/southbridge/amd/cimx/sb900/early.c @@ -25,25 +25,6 @@ #include <commonlib/loglevel.h> #include "smbus.h" -/** - * @brief Get SouthBridge device number - * @param[in] bus target bus number - * @return southbridge device number - */ -u32 get_sbdn(u32 bus) -{ - pci_devfn_t dev; - - printk(BIOS_SPEW, "SB900 - Early.c - get_sbdn - Start.\n"); - - dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_AMD, - PCI_DEVICE_ID_AMD_SB900_SM), bus); - - printk(BIOS_SPEW, "SB900 - Early.c - get_sbdn - End.\n"); - - return (dev >> 15) & 0x1f; -} - /** * @brief South Bridge CIMx romstage entry, diff --git a/src/southbridge/amd/cimx/sb900/sb_cimx.h b/src/southbridge/amd/cimx/sb900/sb_cimx.h index 99b246e..d13c79d 100644 --- a/src/southbridge/amd/cimx/sb900/sb_cimx.h +++ b/src/southbridge/amd/cimx/sb900/sb_cimx.h @@ -33,13 +33,6 @@ #define REV_SB900_A12 0x12 /** - * @brief Get SouthBridge device number, called by finalize_node_setup() - * @param[in] bus target bus number - * @return southbridge device number - */ -u32 get_sbdn(u32 bus); - -/** * South Bridge CIMx romstage entry, sbPowerOnInit entry point wrapper. */ void sb_poweron_init(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/30728 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8eaed338438e1de5baee462376e339e1439f72f1 Gerrit-Change-Number: 30728 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/sarien: Set minimum assertion width values
by Duncan Laurie (Code Review) 07 Jan '19

07 Jan '19

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30722 Change subject: mb/google/sarien: Set minimum assertion width values ...................................................................... mb/google/sarien: Set minimum assertion width values Explicitly configure the minimum assertion width values to ensure that they are set as expected and are not using unknown defaults. Change-Id: I9a88e5b6002137df6e572b84d0de8a69522938f9 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb 2 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/30722/1 diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 5fdf8fd..cccddce 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -23,6 +23,10 @@ register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" register "VmxEnable" = "1" + register "PchPmSlpS3MinAssert" = "3" # 50ms + register "PchPmSlpS4MinAssert" = "4" # 4s + register "PchPmSlpSusMinAssert" = "4" # 4s + register "PchPmSlpAMinAssert" = "4" # 2s register "speed_shift_enable" = "1" register "s0ix_enable" = "1" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 358d131..b590bac 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -27,6 +27,10 @@ register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" register "VmxEnable" = "1" + register "PchPmSlpS3MinAssert" = "3" # 50ms + register "PchPmSlpS4MinAssert" = "4" # 4s + register "PchPmSlpSusMinAssert" = "4" # 4s + register "PchPmSlpAMinAssert" = "4" # 2s register "speed_shift_enable" = "1" register "s0ix_enable" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/30722 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a88e5b6002137df6e572b84d0de8a69522938f9 Gerrit-Change-Number: 30722 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/sarien: Enable recovery mode GPIO
by Duncan Laurie (Code Review) 07 Jan '19

07 Jan '19

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30721 Change subject: mb/google/sarien: Enable recovery mode GPIO ...................................................................... mb/google/sarien: Enable recovery mode GPIO Enable the active-low recovery mode GPIO now that new boards are available which have an external pull-up instead of a pull-down so it can be asserted properly by servo. This was tested on a Sarien system by holding the recovery button on the servo board and tapping the cold reset button and ensuring that it enters recovery mode. Change-Id: I3216580bc94de71b05bf9382f15d0c4d428cb9fa Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/mainboard/google/sarien/variants/sarien/gpio.c 1 file changed, 1 insertion(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/30721/1 diff --git a/src/mainboard/google/sarien/variants/sarien/gpio.c b/src/mainboard/google/sarien/variants/sarien/gpio.c index 3f43e73..f773265 100644 --- a/src/mainboard/google/sarien/variants/sarien/gpio.c +++ b/src/mainboard/google/sarien/variants/sarien/gpio.c @@ -252,10 +252,7 @@ } static const struct cros_gpio cros_gpios[] = { - /* - * TODO: re-enable recovery mode when boards are updated: - * CROS_GPIO_REC_AL(GPP_E8, CROS_GPIO_DEVICE_NAME), - */ + CROS_GPIO_REC_AL(GPP_E8, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPP_E15, CROS_GPIO_DEVICE_NAME), }; -- To view, visit https://review.coreboot.org/c/coreboot/+/30721 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3216580bc94de71b05bf9382f15d0c4d428cb9fa Gerrit-Change-Number: 30721 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/sarien: Remove power button ACPI device
by Duncan Laurie (Code Review) 07 Jan '19

07 Jan '19

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30720 Change subject: mb/google/sarien: Remove power button ACPI device ...................................................................... mb/google/sarien: Remove power button ACPI device These platforms use the standard fixed function power button and do not need a second power button device declared or the kernel will end up with two devices reporting the same event. Change-Id: I6fe2b201a6a6f6307a0c4bd6a61f56cfcdd88bf4 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/mainboard/google/sarien/dsdt.asl 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/30720/1 diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl index 7f46e4f..e5e48bb 100644 --- a/src/mainboard/google/sarien/dsdt.asl +++ b/src/mainboard/google/sarien/dsdt.asl @@ -35,10 +35,6 @@ #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { - Device (PWRB) - { - Name (_HID, EisaId ("PNP0C0C")) - } Device (PCI0) { #include <soc/intel/cannonlake/acpi/northbridge.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/30720 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6fe2b201a6a6f6307a0c4bd6a61f56cfcdd88bf4 Gerrit-Change-Number: 30720 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: Add FSP UPD for minimum assertion width
by Duncan Laurie (Code Review) 07 Jan '19

07 Jan '19

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30719 Change subject: soc/intel/cannonlake: Add FSP UPD for minimum assertion width ...................................................................... soc/intel/cannonlake: Add FSP UPD for minimum assertion width Expose the FSP tunables for the chipset minimum assertion width settings which can be configured per-board. The defaults appear to be different from what is listed in the FSP header documentation so I tried to list what the actual default is based on the source rather than what is stated the header comments. Change-Id: Ie0606c2984727adf13c9fb8395586287162e49ca Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/fsp_params.c 2 files changed, 47 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/30719/1 diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 3a723d2..6517b9e 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -222,6 +222,43 @@ */ uint32_t PrmrrSize; uint8_t PmTimerDisabled; + + /* + * SLP_S3 Minimum Assertion Width Policy + * 1 = 60us + * 2 = 1ms (default) + * 3 = 50ms + * 4 = 2s + */ + uint8_t PchPmSlpS3MinAssert; + + /* + * SLP_S4 Minimum Assertion Width Policy + * 1 = 1s + * 2 = 2s + * 3 = 3s + * 4 = 4s (default) + */ + uint8_t PchPmSlpS4MinAssert; + + /* + * SLP_SUS Minimum Assertion Width Policy + * 1 = 0ms + * 2 = 500ms + * 3 = 1s (default) + * 4 = 4s + */ + uint8_t PchPmSlpSusMinAssert; + + /* + * SLP_A Minimum Assertion Width Policy + * 1 = 0ms + * 2 = 4s + * 3 = 98ms (default) + * 4 = 2s + */ + uint8_t PchPmSlpAMinAssert; + /* Desired platform debug type. */ enum { DebugConsent_Disabled, diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 8166dea..ea781bc 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -229,6 +229,16 @@ /* Power Optimizer */ params->PchPwrOptEnable = config->dmipwroptimize; params->SataPwrOptEnable = config->satapwroptimize; + + /* Apply minimum assertion width settings if non-zero */ + if (config->PchPmSlpS3MinAssert) + params->PchPmSlpS3MinAssert = config->PchPmSlpS3MinAssert; + if (config->PchPmSlpS4MinAssert) + params->PchPmSlpS4MinAssert = config->PchPmSlpS4MinAssert; + if (config->PchPmSlpSusMinAssert) + params->PchPmSlpSusMinAssert = config->PchPmSlpSusMinAssert; + if (config->PchPmSlpAMinAssert) + params->PchPmSlpAMinAssert = config->PchPmSlpAMinAssert; } /* Mainboard GPIO Configuration */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30719 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0606c2984727adf13c9fb8395586287162e49ca Gerrit-Change-Number: 30719 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: Add chipset event logging
by Duncan Laurie (Code Review) 07 Jan '19

07 Jan '19

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30718 Change subject: soc/intel/cannonlake: Add chipset event logging ...................................................................... soc/intel/cannonlake: Add chipset event logging Add logging of chipset events on boot into the flash event log. This was tested on a google/sarien board to ensure that events like "System Reset" are added to the log as expected. Change-Id: I38498cef36d8cc9c8a1f63d12618ea768b65254c Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/soc/intel/cannonlake/Makefile.inc A src/soc/intel/cannonlake/elog.c M src/soc/intel/cannonlake/include/soc/pch.h 3 files changed, 126 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/30718/1 diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 2452f50..faa22f0 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -34,6 +34,7 @@ ramstage-y += acpi.c ramstage-y += chip.c ramstage-y += cpu.c +ramstage-y += elog.c ramstage-y += finalize.c ramstage-y += fsp_params.c ramstage-y += graphics.c diff --git a/src/soc/intel/cannonlake/elog.c b/src/soc/intel/cannonlake/elog.c new file mode 100644 index 0000000..f11b926 --- /dev/null +++ b/src/soc/intel/cannonlake/elog.c @@ -0,0 +1,125 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * Copyright 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootstate.h> +#include <cbmem.h> +#include <console/console.h> +#include <stdint.h> +#include <elog.h> +#include <intelblocks/pmclib.h> +#include <soc/pci_devs.h> +#include <soc/pm.h> + +static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) +{ + int i; + + gpe0_sts &= gpe0_en; + + for (i = 0; i <= 31; i++) { + if (gpe0_sts & (1 << i)) + elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i + start); + } +} + +static void pch_log_wake_source(struct chipset_power_state *ps) +{ + /* Power Button */ + if (ps->pm1_sts & PWRBTN_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0); + + /* RTC */ + if (ps->pm1_sts & RTC_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0); + + /* PCI Express (TODO: determine wake device) */ + if (ps->pm1_sts & PCIEXPWAK_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0); + + /* PME (TODO: determine wake device) */ + if (ps->gpe0_sts[GPE_STD] & PME_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0); + + /* Internal PME (TODO: determine wake device) */ + if (ps->gpe0_sts[GPE_STD] & PME_B0_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); + + /* SMBUS Wake */ + if (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_SMBUS, 0); + + /* Log GPIO events in set 1-3 */ + pch_log_gpio_gpe(ps->gpe0_sts[GPE_31_0], ps->gpe0_en[GPE_31_0], 0); + pch_log_gpio_gpe(ps->gpe0_sts[GPE_63_32], ps->gpe0_en[GPE_63_32], 32); + pch_log_gpio_gpe(ps->gpe0_sts[GPE_95_64], ps->gpe0_en[GPE_95_64], 64); + /* Treat the STD as an extension of GPIO to obtain visibility. */ + pch_log_gpio_gpe(ps->gpe0_sts[GPE_STD], ps->gpe0_en[GPE_STD], 96); +} + +static void pch_log_power_and_resets(struct chipset_power_state *ps) +{ + /* Thermal Trip */ + if (ps->gblrst_cause[0] & GBLRST_CAUSE0_THERMTRIP) + elog_add_event(ELOG_TYPE_THERM_TRIP); + + /* PWR_FLR Power Failure */ + if (ps->gen_pmcon_b & PWR_FLR) + elog_add_event(ELOG_TYPE_POWER_FAIL); + + /* SUS Well Power Failure */ + if (ps->gen_pmcon_b & SUS_PWR_FLR) + elog_add_event(ELOG_TYPE_SUS_POWER_FAIL); + + /* TCO Timeout */ + if (ps->prev_sleep_state != ACPI_S3 && + ps->tco2_sts & TCO2_STS_SECOND_TO) + elog_add_event(ELOG_TYPE_TCO_RESET); + + /* Power Button Override */ + if (ps->pm1_sts & PRBTNOR_STS) + elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE); + + /* RTC reset */ + if (ps->gen_pmcon_b & RTC_BATTERY_DEAD) + elog_add_event(ELOG_TYPE_RTC_RESET); + + /* Host Reset Status */ + if (ps->gen_pmcon_b & HOST_RST_STS) + elog_add_event(ELOG_TYPE_SYSTEM_RESET); + + /* ACPI Wake Event */ + if (ps->prev_sleep_state != ACPI_S0) + elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, ps->prev_sleep_state); +} + +static void pch_log_state(void *unused) +{ + struct chipset_power_state *ps = pmc_get_power_state(); + + if (!ps) { + printk(BIOS_ERR, "chipset_power_state not found!\n"); + return; + } + + /* Power and Reset */ + pch_log_power_and_resets(ps); + + /* Wake Sources */ + if (ps->prev_sleep_state > ACPI_S0) + pch_log_wake_source(ps); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, pch_log_state, NULL); diff --git a/src/soc/intel/cannonlake/include/soc/pch.h b/src/soc/intel/cannonlake/include/soc/pch.h index da64a7a8..5253053 100644 --- a/src/soc/intel/cannonlake/include/soc/pch.h +++ b/src/soc/intel/cannonlake/include/soc/pch.h @@ -28,6 +28,4 @@ #define PCIE_CLK_LAN 0x70 #define PCIE_CLK_FREE 0x80 -void pch_log_state(void); - #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/30718 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38498cef36d8cc9c8a1f63d12618ea768b65254c Gerrit-Change-Number: 30718 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: Fix chipset_power_state structure
by Duncan Laurie (Code Review) 07 Jan '19

07 Jan '19

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30717 Change subject: soc/intel/cannonlake: Fix chipset_power_state structure ...................................................................... soc/intel/cannonlake: Fix chipset_power_state structure This structure is declared as a static CAR_GLOBAL in the common PMC library code and in the SOC specific code. Remove the SOC specific version and instead get the chipset_power_state pointer from the PMC library. This fixes events that were recorded in chipset_power_state at boot but were reading as all zero when it was time to parse the structure when logging events to flash. Change-Id: I67a4f724c0707d98766ad28abd8d0b66a5615745 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/soc/intel/cannonlake/romstage/romstage.c 1 file changed, 1 insertion(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/30717/1 diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index 246e0ea..9224ba6 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -33,8 +33,6 @@ #include <string.h> #include <timestamp.h> -static struct chipset_power_state power_state CAR_GLOBAL; - #define FSP_SMBIOS_MEMORY_INFO_GUID \ { \ 0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \ @@ -112,7 +110,7 @@ bool s3wake; struct postcar_frame pcf; uintptr_t top_of_ram; - struct chipset_power_state *ps = car_get_var_ptr(&power_state); + struct chipset_power_state *ps = pmc_get_power_state(); console_init(); -- To view, visit https://review.coreboot.org/c/coreboot/+/30717 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67a4f724c0707d98766ad28abd8d0b66a5615745 Gerrit-Change-Number: 30717 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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coreboot-gerrit January 2019