coreboot-gerrit January 2019

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Change in ...coreboot[master]: [WIP] Fix amdfam10 regression on dev_find_slot() removal
by Kyösti Mälkki (Code Review) 06 Jan '19

06 Jan '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30695 Change subject: [WIP] Fix amdfam10 regression on dev_find_slot() removal ...................................................................... [WIP] Fix amdfam10 regression on dev_find_slot() removal For these platforms, the first PCI node on devicetree is not the root of PCI bus hierarchy. Change-Id: I19745c3070c12e562ffab2f0243c9d91dd051c72 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/device/device_const.c 1 file changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/30695/1 diff --git a/src/device/device_const.c b/src/device/device_const.c index ec128e8..53a23ca 100644 --- a/src/device/device_const.c +++ b/src/device/device_const.c @@ -190,7 +190,22 @@ pci_domain = dev_find_path(NULL, DEVICE_PATH_DOMAIN); if (!pci_domain) return NULL; + +#if !IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) return pcidev_path_behind(pci_domain->link_list, devfn); +#else + DEVTREE_CONST struct device *rootnode, *dev; + DEVTREE_CONST struct bus *bus; + + rootnode = pcidev_path_behind(pci_domain->link_list, PCI_DEVFN(0x18, 0)); + + for (bus = rootnode->link_list; bus; bus = bus->next) { + dev = pcidev_path_behind(bus, devfn); + if (dev) + return dev; + } + return NULL; +#endif } DEVTREE_CONST struct device *pcidev_on_root(uint8_t dev, uint8_t fn) -- To view, visit https://review.coreboot.org/c/coreboot/+/30695 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19745c3070c12e562ffab2f0243c9d91dd051c72 Gerrit-Change-Number: 30695 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: TESTONLY: Find where the SMBUS device is
by Arthur Heymans (Code Review) 06 Jan '19

06 Jan '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30694 Change subject: TESTONLY: Find where the SMBUS device is ...................................................................... TESTONLY: Find where the SMBUS device is Change-Id: I88a8e81ab305f621b65ed04d98257fa16e309b38 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/amd/sb700/early_setup.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/30694/1 diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index 70cf340..64ff7ff 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -83,6 +83,8 @@ /* if (rev != 0) return rev; */ dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); + printk(BIOS_DEBUG, "found SMBUS controller on %02x:%02x.%d\n", + (dev >> 20) & 0xfff, (dev >> 3) & 0x1f, dev & 0x7); if (dev == PCI_DEV_INVALID) { die("SMBUS controller not found\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/30694 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88a8e81ab305f621b65ed04d98257fa16e309b38 Gerrit-Change-Number: 30694 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: usbdebug: Sanity check PCI EHCI location
by Kyösti Mälkki (Code Review) 06 Jan '19

06 Jan '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30692 Change subject: usbdebug: Sanity check PCI EHCI location ...................................................................... usbdebug: Sanity check PCI EHCI location If requested EHCI function is not on bus 0, we would need to open MMIO windows and configuration register space for the connected upstream PCI bridge for it to work. We don't plan to do so. Change-Id: I7c1c60f9d9890dedfedc9d977faf5152ba362692 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/usb/pci_ehci.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/30692/1 diff --git a/src/drivers/usb/pci_ehci.c b/src/drivers/usb/pci_ehci.c index e0f88ec..c051291 100644 --- a/src/drivers/usb/pci_ehci.c +++ b/src/drivers/usb/pci_ehci.c @@ -34,6 +34,10 @@ { pci_devfn_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX); + /* We only support controllers on bus 0. */ + if (PCI_DEV2SEGBUS(dbg_dev) != 0) + return -1; + #ifdef __SIMPLE_DEVICE__ pci_devfn_t dev = dbg_dev; #else -- To view, visit https://review.coreboot.org/c/coreboot/+/30692 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c1c60f9d9890dedfedc9d977faf5152ba362692 Gerrit-Change-Number: 30692 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Doc/mb/asrock/h81m-hds: Link to the Haswell documentation
by Tristan Corrick (Code Review) 06 Jan '19

06 Jan '19

Tristan Corrick has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30690 Change subject: Doc/mb/asrock/h81m-hds: Link to the Haswell documentation ...................................................................... Doc/mb/asrock/h81m-hds: Link to the Haswell documentation Change-Id: I50da6da6c1321f8d9d94b11d19187a8c22709705 Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> --- M Documentation/mainboard/asrock/h81m-hds.md 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/30690/1 diff --git a/Documentation/mainboard/asrock/h81m-hds.md b/Documentation/mainboard/asrock/h81m-hds.md index fe7b080..df00abd 100644 --- a/Documentation/mainboard/asrock/h81m-hds.md +++ b/Documentation/mainboard/asrock/h81m-hds.md @@ -113,7 +113,7 @@ ```eval_rst +------------------+--------------------------------------------------+ -| Northbridge | Intel Haswell | +| Northbridge | :doc:`../../northbridge/intel/haswell/index` | +------------------+--------------------------------------------------+ | Southbridge | Intel Lynx Point (H81) | +------------------+--------------------------------------------------+ -- To view, visit https://review.coreboot.org/c/coreboot/+/30690 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50da6da6c1321f8d9d94b11d19187a8c22709705 Gerrit-Change-Number: 30690 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Doc/mb/supermicro/x10slm-f: Remove PCIe issue that has been fixed
by Tristan Corrick (Code Review) 06 Jan '19

06 Jan '19

Tristan Corrick has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30689 Change subject: Doc/mb/supermicro/x10slm-f: Remove PCIe issue that has been fixed ...................................................................... Doc/mb/supermicro/x10slm-f: Remove PCIe issue that has been fixed The issue in question was resolved with commit 334be3289d6c ("nb/intel/haswell: Add support for PEG"). Change-Id: Icc3061b60893394e3d537d3b86f4ac748cec2eb4 Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> --- M Documentation/mainboard/supermicro/x10slm-f.md 1 file changed, 1 insertion(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/30689/1 diff --git a/Documentation/mainboard/supermicro/x10slm-f.md b/Documentation/mainboard/supermicro/x10slm-f.md index 8d03429..19abf00 100644 --- a/Documentation/mainboard/supermicro/x10slm-f.md +++ b/Documentation/mainboard/supermicro/x10slm-f.md @@ -128,10 +128,6 @@ ## Known issues -- The x8 PCIe slots do not work, as the Haswell code is missing support. - The code to support it has been written, but it still needs to be - reviewed and merged. - - Broadwell CPUs are not supported. They might work with minimal changes to the code, but this has not been tested. @@ -147,7 +143,7 @@ ## Untested - TPM -- PCIe x4 slot (it will almost certainly work) +- PCIe (it will almost certainly work) - BMC (IPMI) functionality - internal serial port - chassis intrusion header -- To view, visit https://review.coreboot.org/c/coreboot/+/30689 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc3061b60893394e3d537d3b86f4ac748cec2eb4 Gerrit-Change-Number: 30689 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: intel/lynxpoint: Fix spelling
by Kyösti Mälkki (Code Review) 06 Jan '19

06 Jan '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30687 Change subject: intel/lynxpoint: Fix spelling ...................................................................... intel/lynxpoint: Fix spelling Change-Id: I684e1962a9d4312ee9fad4ada70323b02ca3ae48 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/intel/lynxpoint/bootblock.c M src/southbridge/intel/lynxpoint/lpc.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/30687/1 diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index 20d0ee3..1a9e7bb 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c @@ -54,7 +54,7 @@ static void enable_port80_on_lpc(void) { - /* Enable port 80 POST on LPC. The chipset does this by deafult, + /* Enable port 80 POST on LPC. The chipset does this by default, * but it doesn't appear to hurt anything. */ u32 gcs = RCBA32(GCS); gcs = gcs & ~0x4; diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 5b48da0..2738f3a 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -660,7 +660,7 @@ { /* * Check if the register is enabled. If so and the base exceeds the - * device's deafult claim range add the resoure. + * device's default, claim range and add the resource. */ if (reg_value & 1) { u16 base = reg_value & 0xfffc; -- To view, visit https://review.coreboot.org/c/coreboot/+/30687 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I684e1962a9d4312ee9fad4ada70323b02ca3ae48 Gerrit-Change-Number: 30687 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/skylake: Remove SKIP_FSP_CAR Kconfig
by Arthur Heymans (Code Review) 06 Jan '19

06 Jan '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30685 Change subject: soc/intel/skylake: Remove SKIP_FSP_CAR Kconfig ...................................................................... soc/intel/skylake: Remove SKIP_FSP_CAR Kconfig This option seems unused. Change-Id: Ifd4a4242b652673c71a0f0ffab8844f274d19011 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/intel/fsp1_1/Kconfig M src/soc/intel/skylake/Kconfig 2 files changed, 0 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/30685/1 diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index af6ed42..69fa8df 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -94,9 +94,4 @@ bool "Reset the system on S3 wake when ramstage cache invalid." default n -config SKIP_FSP_CAR - def_bool n - help - Selected by platforms that implement their own CAR setup. - endif #PLATFORM_USES_FSP1_1 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 547b165..34e8436 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -99,7 +99,6 @@ depends on !MAINBOARD_USES_FSP2_0 select PLATFORM_USES_FSP1_1 select DISPLAY_FSP_ENTRY_POINTS - select SKIP_FSP_CAR config CHROMEOS select CHROMEOS_RAMOOPS_DYNAMIC -- To view, visit https://review.coreboot.org/c/coreboot/+/30685 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd4a4242b652673c71a0f0ffab8844f274d19011 Gerrit-Change-Number: 30685 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/gm45: Fix GMA init on the libgfxinit path
by Arthur Heymans (Code Review) 06 Jan '19

06 Jan '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30683 Change subject: nb/intel/gm45: Fix GMA init on the libgfxinit path ...................................................................... nb/intel/gm45: Fix GMA init on the libgfxinit path This does the following: - Don't run the VBIOS on the libgfxinit path - Generate a fake option rom containing the VBT on the libgfxinit path Change-Id: Id4145d2d721c6cab6dd4db40e4a1f92ae7402d08 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/gm45/gma.c 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/30683/1 diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 8acec29..ecd4be6 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -599,7 +599,6 @@ struct edid edid_vga; int vga_edid_status; u8 *mmio; - struct northbridge_intel_gm45_config *conf = dev->chip_info; mmio = res2mmio(gtt_res, 0, 0); printk(BIOS_DEBUG, "VGA EDID\n"); @@ -632,9 +631,6 @@ gma_init_lvds(conf, mmio, physbase, pio_res->base, lfb_res->base, edid_lvds); } - - /* Linux relies on VBT for panel info. */ - generate_fake_intel_oprom(&conf->gfx, dev, "$VBT CANTIGA"); } static u32 get_cdclk(struct device *const dev) @@ -756,6 +752,7 @@ u8 *mmio; u8 edid_data_lvds[128]; struct edid edid_lvds; + const struct northbridge_intel_gm45_config *const conf = dev->chip_info; /* IGD needs to be Bus Master */ reg32 = pci_read_config32(dev, PCI_COMMAND); @@ -767,7 +764,8 @@ return; mmio = res2mmio(gtt_res, 0, 0); - if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { + if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) && + !IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) { /* PCI Init, will run VBIOS */ printk(BIOS_DEBUG, "Initialising IGD using VBIOS\n"); pci_dev_init(dev); @@ -794,6 +792,8 @@ int lightup_ok; gma_gfxinit(&lightup_ok); } + /* Linux relies on VBT for panel info. */ + generate_fake_intel_oprom(&conf->gfx, dev, "$VBT CANTIGA"); } intel_gma_restore_opregion(); -- To view, visit https://review.coreboot.org/c/coreboot/+/30683 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4145d2d721c6cab6dd4db40e4a1f92ae7402d08 Gerrit-Change-Number: 30683 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: cpu/intel/microcode_asm.S: Fix reading cpuid(1) and checking PF
by Arthur Heymans (Code Review) 05 Jan '19

05 Jan '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30680 Change subject: cpu/intel/microcode_asm.S: Fix reading cpuid(1) and checking PF ...................................................................... cpu/intel/microcode_asm.S: Fix reading cpuid(1) and checking PF The value of %ebx was clobber later on by a cpuid call. A bitwise and needs to be used to check processor flags. Change-Id: I29f1fddfe3cc2cbfc7c843b6aff7425f32e12317 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/microcode/microcode_asm.S 1 file changed, 5 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/30680/1 diff --git a/src/cpu/intel/microcode/microcode_asm.S b/src/cpu/intel/microcode/microcode_asm.S index ef85760..e158e61 100644 --- a/src/cpu/intel/microcode/microcode_asm.S +++ b/src/cpu/intel/microcode/microcode_asm.S @@ -83,11 +83,6 @@ * Current installed microcode revision -> %edx */ - /* Processor family+model signature=cpuid_eax(1) */ - movl $1, %eax - cpuid - movl %eax, %ebx - /* Processor flags * rdmsr 0x17 * pf = 1 << ((msr.hi >> 18) & 7) */ @@ -108,6 +103,10 @@ wrmsr movl $0x1, %eax cpuid + + /* Processor family+model signature=cpuid_eax(1) */ + movl %eax, %ebx + movl $IA32_BIOS_SIGN_ID, %ecx rdmsr @@ -121,7 +120,7 @@ jne next_entry /* Processor flags */ - cmpl PROCESSOR_FLAG(%esi), %ebp + test PROCESSOR_FLAG(%esi), %ebp jne next_entry /* Check if revision is higher than current */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29f1fddfe3cc2cbfc7c843b6aff7425f32e12317 Gerrit-Change-Number: 30680 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: 3rdparty/chromeec: Update to latest master
by HAOUAS Elyes (Code Review) 05 Jan '19

05 Jan '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30677 Change subject: 3rdparty/chromeec: Update to latest master ...................................................................... 3rdparty/chromeec: Update to latest master Change-Id: I745d96363513ac179201124bcc00e5867c25ec50 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M 3rdparty/chromeec 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/30677/1 diff --git a/3rdparty/chromeec b/3rdparty/chromeec index 11bd4c0..860fe29 160000 --- a/3rdparty/chromeec +++ b/3rdparty/chromeec @@ -1 +1 @@ -Subproject commit 11bd4c0f4d11357ab830982d7dec164813c886dd +Subproject commit 860fe2962d40ee901369d1dc67f4aa7a7a42ba4d -- To view, visit https://review.coreboot.org/c/coreboot/+/30677 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I745d96363513ac179201124bcc00e5867c25ec50 Gerrit-Change-Number: 30677 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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coreboot-gerrit January 2019