coreboot-gerrit January 2019

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Change in ...coreboot[master]: aopen/dxplplusu: Move timestamps to common code
by Kyösti Mälkki (Code Review) 09 Jan '19

09 Jan '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30779 Change subject: aopen/dxplplusu: Move timestamps to common code ...................................................................... aopen/dxplplusu: Move timestamps to common code First initialisation is already in cpu/intel/car/romstage.c. Change-Id: If3e5068b4a9981354f0fca5fc12b6b81de1c8f4b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/aopen/dxplplusu/romstage.c M src/northbridge/intel/e7505/raminit.c 2 files changed, 5 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/30779/1 diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c index 75aad28..f95c7f9 100644 --- a/src/mainboard/aopen/dxplplusu/romstage.c +++ b/src/mainboard/aopen/dxplplusu/romstage.c @@ -21,7 +21,6 @@ #include <console/console.h> #include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> -#include <timestamp.h> #include <southbridge/intel/i82801dx/i82801dx.h> #include <northbridge/intel/e7505/raminit.h> @@ -47,9 +46,6 @@ }, }; - timestamp_init(timestamp_get()); - timestamp_add_now(TS_START_ROMSTAGE); - /* Get the serial port running and print a welcome banner */ lpc47m10x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); @@ -61,15 +57,11 @@ if (!e7505_mch_is_ready()) { enable_smbus(); - timestamp_add_now(TS_BEFORE_INITRAM); - /* The real MCH initialisation. */ e7505_mch_init(memctrl); /* Hook for post ECC scrub settings and debug. */ e7505_mch_done(memctrl); - - timestamp_add_now(TS_AFTER_INITRAM); } printk(BIOS_DEBUG, "SDRAM is up.\n"); diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index 6550bb5..70a0d66 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -37,6 +37,7 @@ #include <assert.h> #include <spd.h> #include <sdram_mode.h> +#include <timestamp.h> #include "raminit.h" #include "e7505.h" @@ -1768,6 +1769,8 @@ RAM_DEBUG_MESSAGE("Northbridge prior to SDRAM init:\n"); DUMPNORTH(); + timestamp_add_now(TS_BEFORE_INITRAM); + sdram_set_registers(memctrl); sdram_set_spd_registers(memctrl); sdram_enable(memctrl); @@ -1777,6 +1780,8 @@ { sdram_post_ecc(memctrl); + timestamp_add_now(TS_AFTER_INITRAM); + RAM_DEBUG_MESSAGE("Northbridge following SDRAM init:\n"); DUMPNORTH(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/30779 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3e5068b4a9981354f0fca5fc12b6b81de1c8f4b Gerrit-Change-Number: 30779 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: crossgcc: Update acpica to version 20190108
by HAOUAS Elyes (Code Review) 09 Jan '19

09 Jan '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30773 Change subject: crossgcc: Update acpica to version 20190108 ...................................................................... crossgcc: Update acpica to version 20190108 changes in this version: https://acpica.org/node/164 Change-Id: Iff7fb6990f69f658c41ec115a3383ec902d8300f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/sum/acpica-unix2-20181213.tar.gz.cksum A util/crossgcc/sum/acpica-unix2-20190108.tar.gz.cksum 3 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/30773/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index d5d68c7..81bda2d 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -54,7 +54,7 @@ GCC_AUTOCONF_VERSION=2.69 BINUTILS_VERSION=2.30 GDB_VERSION=8.2.1 -IASL_VERSION=20181213 +IASL_VERSION=20190108 PYTHON_VERSION=3.7.2 EXPAT_VERSION=2.2.6 # CLANG version number diff --git a/util/crossgcc/sum/acpica-unix2-20181213.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20181213.tar.gz.cksum deleted file mode 100644 index 536362e..0000000 --- a/util/crossgcc/sum/acpica-unix2-20181213.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -38231d2673b494c4b4d04bdadb7e48aba11593a5 tarballs/acpica-unix2-20181213.tar.gz diff --git a/util/crossgcc/sum/acpica-unix2-20190108.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20190108.tar.gz.cksum new file mode 100644 index 0000000..c5cfb4c --- /dev/null +++ b/util/crossgcc/sum/acpica-unix2-20190108.tar.gz.cksum @@ -0,0 +1 @@ +50d96dd38b89c69260ad209cf61035cda1fcdd67 tarballs/acpica-unix2-20190108.tar.gz -- To view, visit https://review.coreboot.org/c/coreboot/+/30773 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff7fb6990f69f658c41ec115a3383ec902d8300f Gerrit-Change-Number: 30773 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [WIP] device/pci_device: Do not break tree topology
by Kyösti Mälkki (Code Review) 09 Jan '19

09 Jan '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30772 Change subject: [WIP] device/pci_device: Do not break tree topology ...................................................................... [WIP] device/pci_device: Do not break tree topology Function pci_scan_bus() breaks bus->children link in the devicetree topology while scanning a bus. While the scan is in progress, accessing PCI devices with number higher than what is being probed was not possible. Change-Id: I7bb497f7390628dd2f0310b380f199783a888c4c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/device/pci_device.c 1 file changed, 23 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/30772/1 diff --git a/src/device/pci_device.c b/src/device/pci_device.c index e35c22c..5aedeb6 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -998,24 +998,23 @@ * @return Pointer to the device structure found or NULL if we have not * allocated a device for this devfn yet. */ -static struct device *pci_scan_get_dev(struct device **list, unsigned int devfn) +static struct device *pci_scan_get_dev(struct bus *bus, unsigned int devfn) { - struct device *dev; + struct device *dev, **prev; - dev = 0; - for (; *list; list = &(*list)->sibling) { - if ((*list)->path.type != DEVICE_PATH_PCI) { - printk(BIOS_ERR, "child %s not a PCI device\n", - dev_path(*list)); - continue; - } - if ((*list)->path.pci.devfn == devfn) { + prev = &bus->children; + for (dev = bus->children; dev; dev = dev->sibling) { + if ((dev->path.type == DEVICE_PATH_PCI) && + (dev->path.pci.devfn == devfn)) { /* Unlink from the list. */ - dev = *list; - *list = (*list)->sibling; + *prev = dev->sibling; dev->sibling = NULL; break; + } else { + printk(BIOS_ERR, "child %s not a PCI device\n", + dev_path(dev)); } + prev = &dev->sibling; } /* @@ -1027,15 +1026,15 @@ if (dev) { struct device *child; - /* Find the last child of our parent. */ - for (child = dev->bus->children; child && child->sibling;) + /* Find the last child on the bus. */ + for (child = bus->children; child && child->sibling;) child = child->sibling; - /* Place the device on the list of children of its parent. */ + /* Place the device as last on the bus. */ if (child) child->sibling = dev; else - dev->bus->children = dev; + bus->children = dev; } return dev; @@ -1180,7 +1179,7 @@ unsigned max_devfn) { unsigned int devfn; - struct device *old_devices; + struct device *left; printk(BIOS_DEBUG, "PCI: pci_scan_bus for bus %02x\n", bus->secondary); @@ -1193,9 +1192,6 @@ max_devfn=0xff; } - old_devices = bus->children; - bus->children = NULL; - post_code(0x24); /* @@ -1206,7 +1202,7 @@ struct device *dev; /* First thing setup the device structure. */ - dev = pci_scan_get_dev(&old_devices, devfn); + dev = pci_scan_get_dev(bus, devfn); /* See if a device is present and setup the device structure. */ dev = pci_probe_dev(dev, bus, devfn); @@ -1228,13 +1224,13 @@ * Warn if any leftover static devices are are found. * There's probably a problem in devicetree.cb. */ - if (old_devices) { - struct device *left; - printk(BIOS_WARNING, "PCI: Left over static devices:\n"); - for (left = old_devices; left; left = left->sibling) - printk(BIOS_WARNING, "%s\n", dev_path(left)); - printk(BIOS_WARNING, "PCI: Check your devicetree.cb.\n"); + printk(BIOS_WARNING, "PCI: Left over static devices:\n"); + for (left = bus->children; left; left = left->sibling) { + if (left->vendor == 0x0) { + printk(BIOS_WARNING, "%s\n", dev_path(left)); + printk(BIOS_WARNING, "PCI: Check your devicetree.cb.\n"); + } } /* -- To view, visit https://review.coreboot.org/c/coreboot/+/30772 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7bb497f7390628dd2f0310b380f199783a888c4c Gerrit-Change-Number: 30772 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb: Move timestamp_add_now to northbridge/amd/amdfam10
by HAOUAS Elyes (Code Review) 09 Jan '19

09 Jan '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30771 Change subject: mb: Move timestamp_add_now to northbridge/amd/amdfam10 ...................................................................... mb: Move timestamp_add_now to northbridge/amd/amdfam10 Also remove some commented code. Change-Id: If2e91ad871b14b305e2181194d77b100e72f5763 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/advansus/a785e-i/romstage.c M src/mainboard/amd/bimini_fam10/romstage.c M src/mainboard/amd/mahogany_fam10/romstage.c M src/mainboard/amd/serengeti_cheetah_fam10/romstage.c M src/mainboard/amd/tilapia_fam10/romstage.c M src/mainboard/asus/kcma-d8/romstage.c M src/mainboard/asus/kfsn4-dre/romstage.c M src/mainboard/asus/kgpe-d16/romstage.c M src/mainboard/asus/m4a78-em/romstage.c M src/mainboard/asus/m4a785-m/romstage.c M src/mainboard/asus/m5a88-v/romstage.c M src/mainboard/avalue/eax-785e/romstage.c M src/mainboard/gigabyte/ma785gm/romstage.c M src/mainboard/gigabyte/ma785gmt/romstage.c M src/mainboard/gigabyte/ma78gm/romstage.c M src/mainboard/iei/kino-780am2-fam10/romstage.c M src/mainboard/jetway/pa78vm5/romstage.c M src/mainboard/msi/ms9652_fam10/romstage.c M src/mainboard/supermicro/h8dmr_fam10/romstage.c M src/mainboard/supermicro/h8qme_fam10/romstage.c M src/mainboard/supermicro/h8scm_fam10/romstage.c M src/mainboard/tyan/s2912_fam10/romstage.c M src/northbridge/amd/amdfam10/raminit_amdmct.c 23 files changed, 4 insertions(+), 181 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/30771/1 diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index f9ea822..907c8ed 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -193,10 +193,7 @@ post_code(0x40); - timestamp_add_now(TS_BEFORE_INITRAM); - printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); - timestamp_add_now(TS_AFTER_INITRAM); cbmem_initialize_empty(); post_code(0x41); diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index 3d86b60..602a433 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -189,10 +189,7 @@ post_code(0x40); - timestamp_add_now(TS_BEFORE_INITRAM); - printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); - timestamp_add_now(TS_AFTER_INITRAM); cbmem_initialize_empty(); post_code(0x41); diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index b0d23b2..c9fc9ec 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -194,27 +194,13 @@ post_code(0x40); -// die("Die Before MCT init."); - - timestamp_add_now(TS_BEFORE_INITRAM); - printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); - timestamp_add_now(TS_AFTER_INITRAM); cbmem_initialize_empty(); post_code(0x41); amdmct_cbmem_store_info(sysinfo); -/* - dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); -*/ - -// die("After MCT init before CAR disabled."); - sb7xx_51xx_before_pci_init(); post_code(0x42); diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index 03d3484..567a60a 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -300,10 +300,7 @@ memreset_setup(); post_code(0x40); - timestamp_add_now(TS_BEFORE_INITRAM); - printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); - timestamp_add_now(TS_AFTER_INITRAM); cbmem_initialize_empty(); post_code(0x41); diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index 50c7a00..b027e49 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -190,10 +190,7 @@ post_code(0x40); - timestamp_add_now(TS_BEFORE_INITRAM); - printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); - timestamp_add_now(TS_AFTER_INITRAM); cbmem_initialize_empty(); post_code(0x41); diff --git a/src/mainboard/asus/kcma-d8/romstage.c b/src/mainboard/asus/kcma-d8/romstage.c index caff4df..24117a5 100644 --- a/src/mainboard/asus/kcma-d8/romstage.c +++ b/src/mainboard/asus/kcma-d8/romstage.c @@ -550,10 +550,7 @@ post_code(0x40); - timestamp_add_now(TS_BEFORE_INITRAM); - printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); - timestamp_add_now(TS_AFTER_INITRAM); #ifdef TEST_MEMORY execute_memory_test(); diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c index 99d437f..62a12d1 100644 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -324,10 +324,7 @@ post_code(0x40); - timestamp_add_now(TS_BEFORE_INITRAM); - printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); - timestamp_add_now(TS_AFTER_INITRAM); cbmem_initialize_empty(); post_code(0x41); diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index 59ad026..e9c6e07 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -660,10 +660,7 @@ post_code(0x40); - timestamp_add_now(TS_BEFORE_INITRAM); - printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); - timestamp_add_now(TS_AFTER_INITRAM); #ifdef TEST_MEMORY execute_memory_test(); diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index 87a5d77..788907a 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -194,27 +194,13 @@ post_code(0x40); -// die("Die Before MCT init."); - - timestamp_add_now(TS_BEFORE_INITRAM); - printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); - timestamp_add_now(TS_AFTER_INITRAM); cbmem_initialize_empty(); post_code(0x41); amdmct_cbmem_store_info(sysinfo); -/* - dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); -*/ - -// die("After MCT init before CAR disabled."); - sb7xx_51xx_before_pci_init(); post_code(0x42); diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index 02c396f..5cc9707 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -195,27 +195,13 @@ post_code(0x40); -// die("Die Before MCT init."); - - timestamp_add_now(TS_BEFORE_INITRAM); - printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); - timestamp_add_now(TS_AFTER_INITRAM); cbmem_initialize_empty(); post_code(0x41); amdmct_cbmem_store_info(sysinfo); -/* - dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); -*/ - -// die("After MCT init before CAR disabled."); - sb7xx_51xx_before_pci_init(); post_code(0x42); diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index 4c2687f..6b03ffd 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -195,30 +195,13 @@ post_code(0x40); -// die("Die Before MCT init."); - - timestamp_add_now(TS_BEFORE_INITRAM); - printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); - timestamp_add_now(TS_AFTER_INITRAM); cbmem_initialize_empty(); post_code(0x41); amdmct_cbmem_store_info(sysinfo); -/* - dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); -*/ - -// ram_check(0x00200000, 0x00200000 + (640 * 1024)); -// ram_check(0x40200000, 0x40200000 + (640 * 1024)); - -// die("After MCT init before CAR disabled."); - sb800_before_pci_init(); post_code(0x42); diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index 88cb784..d4c5ed1 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -193,10 +193,7 @@ post_code(0x40); - timestamp_add_now(TS_BEFORE_INITRAM); - printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); - timestamp_add_now(TS_AFTER_INITRAM); cbmem_initialize_empty(); post_code(0x41); diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index 2a0a54b..1bb3c64 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -190,27 +190,13 @@ post_code(0x40); -// die("Die Before MCT init."); - - timestamp_add_now(TS_BEFORE_INITRAM); - printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); - timestamp_add_now(TS_AFTER_INITRAM); cbmem_initialize_empty(); post_code(0x41); amdmct_cbmem_store_info(sysinfo); -/* - dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); -*/ - -// die("After MCT init before CAR disabled."); - sb7xx_51xx_before_pci_init(); post_code(0x42); diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index 67cd4a8..11dd190 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -190,27 +190,13 @@ post_code(0x40); -// die("Die Before MCT init."); - - timestamp_add_now(TS_BEFORE_INITRAM); - printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); - timestamp_add_now(TS_AFTER_INITRAM); cbmem_initialize_empty(); post_code(0x41); amdmct_cbmem_store_info(sysinfo); -/* - dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); -*/ - -// die("After MCT init before CAR disabled."); - sb7xx_51xx_before_pci_init(); post_code(0x42); diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index 191a391..1f294b6 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -192,27 +192,13 @@ post_code(0x40); -// die("Die Before MCT init."); - - timestamp_add_now(TS_BEFORE_INITRAM); - printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); - timestamp_add_now(TS_AFTER_INITRAM); cbmem_initialize_empty(); post_code(0x41); amdmct_cbmem_store_info(sysinfo); -/* - dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); -*/ - -// die("After MCT init before CAR disabled."); - sb7xx_51xx_before_pci_init(); post_code(0x42); diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index 1a89343..d42e90b 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -192,27 +192,13 @@ post_code(0x40); -// die("Die Before MCT init."); - - timestamp_add_now(TS_BEFORE_INITRAM); - printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); - timestamp_add_now(TS_AFTER_INITRAM); cbmem_initialize_empty(); post_code(0x41); amdmct_cbmem_store_info(sysinfo); -/* - dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); -*/ - -// die("After MCT init before CAR disabled."); - sb7xx_51xx_before_pci_init(); post_code(0x42); diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index 0b2d164..9c4183e 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -197,27 +197,13 @@ post_code(0x40); -// die("Die Before MCT init."); - - timestamp_add_now(TS_BEFORE_INITRAM); - printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); - timestamp_add_now(TS_AFTER_INITRAM); cbmem_initialize_empty(); post_code(0x41); amdmct_cbmem_store_info(sysinfo); -/* - dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); -*/ - -// die("After MCT init before CAR disabled."); - sb7xx_51xx_before_pci_init(); post_code(0x42); diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 8b43504..b4988bd 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -237,10 +237,7 @@ post_code(0x40); - timestamp_add_now(TS_BEFORE_INITRAM); - printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); - timestamp_add_now(TS_AFTER_INITRAM); cbmem_initialize_empty(); post_code(0x41); diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index 838d7e2..1834d5d 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -235,10 +235,7 @@ post_code(0x40); - timestamp_add_now(TS_BEFORE_INITRAM); - printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); - timestamp_add_now(TS_AFTER_INITRAM); cbmem_initialize_empty(); post_code(0x41); diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index 660610e..1c049d1 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -285,10 +285,8 @@ post_code(0x40); - timestamp_add_now(TS_BEFORE_INITRAM); - printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); - timestamp_add_now(TS_AFTER_INITRAM); + cbmem_initialize_empty(); post_code(0x41); diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c index 23d47b4..8508189 100644 --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c @@ -206,29 +206,13 @@ post_code(0x40); - - timestamp_add_now(TS_BEFORE_INITRAM); - printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); - timestamp_add_now(TS_AFTER_INITRAM); cbmem_initialize_empty(); post_code(0x41); amdmct_cbmem_store_info(sysinfo); -/* - dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); -*/ - -// ram_check(0x00200000, 0x00200000 + (640 * 1024)); -// ram_check(0x40200000, 0x40200000 + (640 * 1024)); - -// die("After MCT init before CAR disabled."); - sr5650_before_pci_init(); sb7xx_51xx_before_pci_init(); diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index 126724f..93fe493 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -233,10 +233,7 @@ post_code(0x40); - timestamp_add_now(TS_BEFORE_INITRAM); - printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); - timestamp_add_now(TS_AFTER_INITRAM); cbmem_initialize_empty(); post_code(0x41); diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c index 3a2dccc..7a9a6d8 100644 --- a/src/northbridge/amd/amdfam10/raminit_amdmct.c +++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c @@ -26,6 +26,7 @@ #include <northbridge/amd/amdfam10/debug.h> #include <northbridge/amd/amdfam10/raminit.h> #include <northbridge/amd/amdfam10/amdfam10.h> +#include <timestamp.h> /* Global allocation of sysinfo_car */ #include <arch/early_variables.h> @@ -562,9 +563,11 @@ struct DCTStatStruc *pDCTstatA = sysinfo->DCTstatA; printk(BIOS_DEBUG, "raminit_amdmct begin:\n"); + timestamp_add_now(TS_BEFORE_INITRAM); mctAutoInitMCT_D(pMCTstat, pDCTstatA); + timestamp_add_now(TS_AFTER_INITRAM); printk(BIOS_DEBUG, "raminit_amdmct end:\n"); } -- To view, visit https://review.coreboot.org/c/coreboot/+/30771 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2e91ad871b14b305e2181194d77b100e72f5763 Gerrit-Change-Number: 30771 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/asus/h61m-cs: fix more lint errors
by DevMaster64 (Code Review) 09 Jan '19

09 Jan '19

DevMaster64 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30770 Change subject: mb/asus/h61m-cs: fix more lint errors ...................................................................... mb/asus/h61m-cs: fix more lint errors Change-Id: I7ab2a427158cb30a77cfc7f87010d6e9827566ed --- M src/mainboard/asus/h61m-cs/mainboard.c M src/mainboard/asus/h61m-cs/romstage.c 2 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/30770/1 diff --git a/src/mainboard/asus/h61m-cs/mainboard.c b/src/mainboard/asus/h61m-cs/mainboard.c index bd6b387..64225ba 100644 --- a/src/mainboard/asus/h61m-cs/mainboard.c +++ b/src/mainboard/asus/h61m-cs/mainboard.c @@ -23,12 +23,12 @@ { /* FIXME: fix those values*/ install_intel_vga_int15_handler( - GMA_INT15_ACTIVE_LFP_INT_LVDS, - GMA_INT15_PANEL_FIT_DEFAULT, - GMA_INT15_BOOT_DISPLAY_DEFAULT, + GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, -}; +}; \ No newline at end of file diff --git a/src/mainboard/asus/h61m-cs/romstage.c b/src/mainboard/asus/h61m-cs/romstage.c index 8f49e53..eaf18af 100644 --- a/src/mainboard/asus/h61m-cs/romstage.c +++ b/src/mainboard/asus/h61m-cs/romstage.c @@ -138,4 +138,4 @@ { read_spd(&spd[0], 0x50, id_only); //My slot 0 is short so assuming 0x50 read_spd(&spd[2], 0x52, id_only); -} +} \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/30770 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ab2a427158cb30a77cfc7f87010d6e9827566ed Gerrit-Change-Number: 30770 Gerrit-PatchSet: 1 Gerrit-Owner: DevMaster64 <realdevmaster64(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/asus/h61m-cs: fix lint errors
by DevMaster64 (Code Review) 09 Jan '19

09 Jan '19

DevMaster64 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30769 Change subject: mb/asus/h61m-cs: fix lint errors ...................................................................... mb/asus/h61m-cs: fix lint errors Change-Id: Ifce33b61d33adbffb3d499d6f608d8700e4a6b25 --- M src/mainboard/asus/h61m-cs/mainboard.c M src/mainboard/asus/h61m-cs/romstage.c 2 files changed, 6 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/30769/1 diff --git a/src/mainboard/asus/h61m-cs/mainboard.c b/src/mainboard/asus/h61m-cs/mainboard.c index 17b2cec..bd6b387 100644 --- a/src/mainboard/asus/h61m-cs/mainboard.c +++ b/src/mainboard/asus/h61m-cs/mainboard.c @@ -22,7 +22,11 @@ static void mainboard_enable(struct device *dev) { /* FIXME: fix those values*/ - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); + install_intel_vga_int15_handler( + GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, + 0); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/asus/h61m-cs/romstage.c b/src/mainboard/asus/h61m-cs/romstage.c index 2d430ca..8f49e53 100644 --- a/src/mainboard/asus/h61m-cs/romstage.c +++ b/src/mainboard/asus/h61m-cs/romstage.c @@ -135,7 +135,7 @@ } void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ +{ read_spd(&spd[0], 0x50, id_only); //My slot 0 is short so assuming 0x50 read_spd(&spd[2], 0x52, id_only); } -- To view, visit https://review.coreboot.org/c/coreboot/+/30769 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifce33b61d33adbffb3d499d6f608d8700e4a6b25 Gerrit-Change-Number: 30769 Gerrit-PatchSet: 1 Gerrit-Owner: DevMaster64 <realdevmaster64(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/asus/h61m-cs: Add missing licenses
by DevMaster64 (Code Review) 09 Jan '19

09 Jan '19

DevMaster64 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30768 Change subject: mb/asus/h61m-cs: Add missing licenses ...................................................................... mb/asus/h61m-cs: Add missing licenses Change-Id: I9e3207b4ba1df424bb8f9c810a21f92de94a687e --- M src/mainboard/asus/h61m-cs/acpi/platform.asl M src/mainboard/asus/h61m-cs/dsdt.asl 2 files changed, 32 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/30768/1 diff --git a/src/mainboard/asus/h61m-cs/acpi/platform.asl b/src/mainboard/asus/h61m-cs/acpi/platform.asl index 0222986..f701deb 100644 --- a/src/mainboard/asus/h61m-cs/acpi/platform.asl +++ b/src/mainboard/asus/h61m-cs/acpi/platform.asl @@ -1,3 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 DevMaster64 <realdevmaster64(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + Method(_WAK,1) { Return(Package(){0,0}) diff --git a/src/mainboard/asus/h61m-cs/dsdt.asl b/src/mainboard/asus/h61m-cs/dsdt.asl index 02a5e32..135f8a0 100644 --- a/src/mainboard/asus/h61m-cs/dsdt.asl +++ b/src/mainboard/asus/h61m-cs/dsdt.asl @@ -1,3 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 DevMaster64 <realdevmaster64(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 -- To view, visit https://review.coreboot.org/c/coreboot/+/30768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e3207b4ba1df424bb8f9c810a21f92de94a687e Gerrit-Change-Number: 30768 Gerrit-PatchSet: 1 Gerrit-Owner: DevMaster64 <realdevmaster64(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/denverton_ns: Fix missing tsc_freq_mhz()
by Kyösti Mälkki (Code Review) 09 Jan '19

09 Jan '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30763 Change subject: soc/intel/denverton_ns: Fix missing tsc_freq_mhz() ...................................................................... soc/intel/denverton_ns: Fix missing tsc_freq_mhz() It was relying on bad weak implementation for postcar and verstage. Change-Id: I5a520e0166198c0565349c164f143f4a43649861 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/denverton_ns/Makefile.inc 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/30763/1 diff --git a/src/soc/intel/denverton_ns/Makefile.inc b/src/soc/intel/denverton_ns/Makefile.inc index c024c3a..e9d5022 100644 --- a/src/soc/intel/denverton_ns/Makefile.inc +++ b/src/soc/intel/denverton_ns/Makefile.inc @@ -31,6 +31,7 @@ postcar-y += memmap.c postcar-y += spi.c +postcar-y += tsc_freq.c postcar-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c romstage-y += memmap.c @@ -80,6 +81,7 @@ verstage-y += memmap.c verstage-y += reset.c verstage-y += spi.c +verstage-y += tsc_freq.c verstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c CPPFLAGS_common += -I$(src)/soc/intel/denverton_ns/include -- To view, visit https://review.coreboot.org/c/coreboot/+/30763 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a520e0166198c0565349c164f143f4a43649861 Gerrit-Change-Number: 30763 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Veyron: fix sdram config for Hynix H9CCNNNBKTMLBR-NTD
by Loop Wu (Code Review) 09 Jan '19

09 Jan '19

Loop Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30761 Change subject: Veyron: fix sdram config for Hynix H9CCNNNBKTMLBR-NTD ...................................................................... Veyron: fix sdram config for Hynix H9CCNNNBKTMLBR-NTD Sdram config sdram-lpddr3-hynix-4GB.inc for H9CCNNNBKTMLBR-NTD can't boot on Mickey. It's confirmed that the right config for Hynix H9CCNNNBKTMLBR-NTD is sdram-lpddr3-hynix-2GB-BK.inc. BUG=b:122239609 BRANCH=master TEST=boot on mickey Change-Id: Ifeaadda50d939e0c118cb7fe3964dcd08b709c2a Signed-off-by: Loop_Wu <Loop_Wu(a)asus.com> --- M src/mainboard/google/veyron/sdram_configs.c M src/mainboard/google/veyron_mickey/sdram_configs.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/30761/1 diff --git a/src/mainboard/google/veyron/sdram_configs.c b/src/mainboard/google/veyron/sdram_configs.c index ee8d4c1..d8748c1 100644 --- a/src/mainboard/google/veyron/sdram_configs.c +++ b/src/mainboard/google/veyron/sdram_configs.c @@ -40,7 +40,7 @@ #include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 000Z */ #include "sdram_inf/sdram-lpddr3-micron-2GB-D2.inc" /* ram_code = 001Z */ #include "sdram_inf/sdram-lpddr3-hynix-2GB-BK.inc" /* ram_code = 00Z0 */ -#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 00Z1 */ +#include "sdram_inf/sdram-lpddr3-hynix-2GB-BK.inc" /* ram_code = 00Z1 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 00ZZ */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 010Z */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 011Z */ diff --git a/src/mainboard/google/veyron_mickey/sdram_configs.c b/src/mainboard/google/veyron_mickey/sdram_configs.c index ee8d4c1..d8748c1 100644 --- a/src/mainboard/google/veyron_mickey/sdram_configs.c +++ b/src/mainboard/google/veyron_mickey/sdram_configs.c @@ -40,7 +40,7 @@ #include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 000Z */ #include "sdram_inf/sdram-lpddr3-micron-2GB-D2.inc" /* ram_code = 001Z */ #include "sdram_inf/sdram-lpddr3-hynix-2GB-BK.inc" /* ram_code = 00Z0 */ -#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 00Z1 */ +#include "sdram_inf/sdram-lpddr3-hynix-2GB-BK.inc" /* ram_code = 00Z1 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 00ZZ */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 010Z */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 011Z */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30761 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifeaadda50d939e0c118cb7fe3964dcd08b709c2a Gerrit-Change-Number: 30761 Gerrit-PatchSet: 1 Gerrit-Owner: Loop Wu <Loop_Wu(a)asus.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: gizmosphere/gizmo2/Kconfig: select HUDSON_IMC_ENABLE
by mikeb mikeb (Code Review) 09 Jan '19

09 Jan '19

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30759 to review the following change. Change subject: gizmosphere/gizmo2/Kconfig: select HUDSON_IMC_ENABLE ...................................................................... gizmosphere/gizmo2/Kconfig: select HUDSON_IMC_ENABLE Gizmo 2 could use IMC for the onboard fan control. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I448620ab4e0329c759b3f924b08c2dfe904d08e8 --- M src/mainboard/gizmosphere/gizmo2/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/30759/1 diff --git a/src/mainboard/gizmosphere/gizmo2/Kconfig b/src/mainboard/gizmosphere/gizmo2/Kconfig index f5c9481..94158ba 100644 --- a/src/mainboard/gizmosphere/gizmo2/Kconfig +++ b/src/mainboard/gizmosphere/gizmo2/Kconfig @@ -28,6 +28,7 @@ select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 select GFXUMA + select HUDSON_IMC_ENABLE config MAINBOARD_DIR string -- To view, visit https://review.coreboot.org/c/coreboot/+/30759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I448620ab4e0329c759b3f924b08c2dfe904d08e8 Gerrit-Change-Number: 30759 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit January 2019