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Change in ...coreboot[master]: soc/intel/baytrail: Use non-evict CAR setup
by Arthur Heymans (Code Review) 11 Feb '19

11 Feb '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30814 Change subject: soc/intel/baytrail: Use non-evict CAR setup ...................................................................... soc/intel/baytrail: Use non-evict CAR setup The CAR setup is almost identical to the cpu/intel/non-evict CAR setup, with the only difference that L2 cache needs to be separately enabled. Currently this assumes that it is possible to use a static Kconfig option to cover all CPU's requiring this. Change-Id: Iae9b584bc0d32a56be2e6e2b2e893897eb448aa5 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/Kconfig A src/cpu/intel/car/non-evict/Kconfig M src/cpu/intel/car/non-evict/cache_as_ram.S M src/soc/intel/baytrail/Kconfig M src/soc/intel/baytrail/romstage/Makefile.inc D src/soc/intel/baytrail/romstage/cache_as_ram.inc 6 files changed, 21 insertions(+), 218 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/30814/1 diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig index f5d0ab9..18f73b4 100644 --- a/src/cpu/intel/Kconfig +++ b/src/cpu/intel/Kconfig @@ -36,3 +36,4 @@ source src/cpu/intel/turbo/Kconfig source src/cpu/intel/common/Kconfig source src/cpu/intel/microcode/Kconfig +source src/cpu/intel/car/non-evict/Kconfig diff --git a/src/cpu/intel/car/non-evict/Kconfig b/src/cpu/intel/car/non-evict/Kconfig new file mode 100644 index 0000000..faf13e7 --- /dev/null +++ b/src/cpu/intel/car/non-evict/Kconfig @@ -0,0 +1,5 @@ +config CPU_HAS_L2_ENABLE_MSR + bool + help + Select this in Kconfig of CPU sockets/SOC where the CPU + has an MSR to enable the L2 CPU cache diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index d2beaa7..3203159 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -24,6 +24,7 @@ #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE #define NoEvictMod_MSR 0x2e0 +#define BBL_CR_CTL3_MSR 0x11e .global bootblock_pre_c_entry @@ -133,6 +134,18 @@ orl $MTRR_DEF_TYPE_EN, %eax wrmsr +#if IS_ENABLED(CONFIG_CPU_HAS_L2_ENABLE_MSR) + /* + * Enable the L2 cache. Currently this assumes that this + * only affect socketed CPU's for which this is always valid, + * hence the static preprocesser. + */ + movl $BBL_CR_CTL3_MSR, %ecx + rdmsr + orl $0x100, %eax + wrmsr +#endif + /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index ade908f..e824ee4 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -40,6 +40,7 @@ select POSTCAR_STAGE select POSTCAR_CONSOLE select CPU_INTEL_COMMON + select CPU_HAS_L2_ENABLE_MSR config VBOOT select VBOOT_STARTS_IN_ROMSTAGE diff --git a/src/soc/intel/baytrail/romstage/Makefile.inc b/src/soc/intel/baytrail/romstage/Makefile.inc index aa10ba6..f1a3463 100644 --- a/src/soc/intel/baytrail/romstage/Makefile.inc +++ b/src/soc/intel/baytrail/romstage/Makefile.inc @@ -1,4 +1,4 @@ -cpu_incs-y += $(src)/soc/intel/baytrail/romstage/cache_as_ram.inc +cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S cpu_incs-y += $(obj)/fmap_config.h romstage-y += romstage.c romstage-y += raminit.c diff --git a/src/soc/intel/baytrail/romstage/cache_as_ram.inc b/src/soc/intel/baytrail/romstage/cache_as_ram.inc deleted file mode 100644 index 4326636..0000000 --- a/src/soc/intel/baytrail/romstage/cache_as_ram.inc +++ /dev/null @@ -1,217 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com> - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cpu/x86/mtrr.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/post_code.h> -#include <cpu/x86/msr.h> - -#include "fmap_config.h" - -/* The full cache-as-ram size includes the cache-as-ram portion from coreboot - * and the space used by the reference code. These 2 values combined should - * be a power of 2 because the MTRR setup assumes that. */ -#define CACHE_AS_RAM_SIZE \ - (CONFIG_DCACHE_RAM_SIZE + CONFIG_DCACHE_RAM_MRC_VAR_SIZE) -#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE - -/* Cache all of CBFS just below 4GiB as Write-Protect type. */ -#define CODE_CACHE_SIZE _ALIGN_UP_POW2(___FMAP__COREBOOT_SIZE) -#define CODE_CACHE_BASE (-CODE_CACHE_SIZE) -#define CODE_CACHE_MASK (~(CODE_CACHE_SIZE - 1)) - -#define NoEvictMod_MSR 0x2e0 -#define BBL_CR_CTL3_MSR 0x11e - -cache_as_ram: - post_code(0x20) - - /* Send INIT IPI to all excluding ourself. */ - movl $0x000C4500, %eax - movl $0xFEE00300, %esi - movl %eax, (%esi) - - /* All CPUs need to be in Wait for SIPI state */ -wait_for_sipi: - movl (%esi), %eax - bt $12, %eax - jc wait_for_sipi - - post_code(0x21) - /* Configure the default memory type to uncacheable as well as disable - * fixed and variable range mtrrs. */ - movl $MTRR_DEF_TYPE_MSR, %ecx - rdmsr - andl $(~0x00000cff), %eax - wrmsr - - post_code(0x22) - /* Zero the variable MTRRs. */ - movl $IA32_MCG_CAP, %ecx - rdmsr - movzx %al, %ebx - /* First variable MTRR. */ - movl $MTRR_PHYS_BASE(0), %ecx - xorl %eax, %eax - xorl %edx, %edx -1: - wrmsr - inc %ecx - dec %ebx - jnz 1b - - /* Clear/disable fixed MTRRs */ - mov $fixed_mtrr_list_size, %ebx - xor %eax, %eax - xor %edx, %edx - -clear_fixed_mtrr: - add $-2, %ebx - movzwl fixed_mtrr_list(%ebx), %ecx - wrmsr - jnz clear_fixed_mtrr - - /* Determine CPU_ADDR_BITS and load PHYSMASK high word to %edx. */ - movl $0x80000008, %eax - cpuid - movb %al, %cl - sub $32, %cl - movl $1, %edx - shl %cl, %edx - subl $1, %edx - - /* Preload high word of address mask (in %edx) for Variable - * MTRRs 0 and 1. - */ -addrsize_set_high: - xorl %eax, %eax - movl $MTRR_PHYS_MASK(0), %ecx - wrmsr - movl $MTRR_PHYS_MASK(1), %ecx - wrmsr - - - post_code(0x23) - /* Set Cache-as-RAM base address. */ - movl $(MTRR_PHYS_BASE(0)), %ecx - movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax - xorl %edx, %edx - wrmsr - - post_code(0x24) - /* Set Cache-as-RAM mask. */ - movl $(MTRR_PHYS_MASK(0)), %ecx - rdmsr - movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax - wrmsr - - post_code(0x25) - /* Set code caching up for romstage. */ - movl $(MTRR_PHYS_BASE(1)), %ecx - movl $(CODE_CACHE_BASE | MTRR_TYPE_WRPROT), %eax - xorl %edx, %edx - wrmsr - - movl $MTRR_PHYS_MASK(1), %ecx - rdmsr - movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax - wrmsr - - /* Enable MTRR. */ - movl $MTRR_DEF_TYPE_MSR, %ecx - rdmsr - orl $MTRR_DEF_TYPE_EN, %eax - wrmsr - - post_code(0x26) - - /* Enable the L2 cache. */ - movl $BBL_CR_CTL3_MSR, %ecx - rdmsr - orl $0x100, %eax - wrmsr - - post_code(0x27) - - /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ - movl %cr0, %eax - andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax - invd - movl %eax, %cr0 - - /* enable the 'no eviction' mode */ - movl $NoEvictMod_MSR, %ecx - rdmsr - orl $1, %eax - wrmsr - - post_code(0x28) - - /* Clear the cache memory region. This will also fill up the cache */ - movl $CACHE_AS_RAM_BASE, %esi - movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE >> 2), %ecx - xorl %eax, %eax - rep stosl - - /* enable no evict mode */ - movl $NoEvictMod_MSR, %ecx - rdmsr - orl $2, %eax - wrmsr - - post_code(0x29) - - /* Setup the stack. */ - mov $_car_stack_end, %esp - - /* Need to align stack to 16 bytes at call instruction. Account for - the pushes below. */ - andl $0xfffffff0, %esp - subl $4, %esp - - /* push TSC and BIST to stack */ - movd %mm0, %eax - pushl %eax /* BIST */ - movd %mm2, %eax - pushl %eax /* tsc[63:32] */ - movd %mm1, %eax - pushl %eax /* tsc[31:0] */ - -before_c_entry: - post_code(0x2a) - call bootblock_c_entry_bist - - /* Should never see this postcode */ - post_code(POST_DEAD_CODE) - -.Lhlt: - hlt - jmp .Lhlt - -fixed_mtrr_list: - .word MTRR_FIX_64K_00000 - .word MTRR_FIX_16K_80000 - .word MTRR_FIX_16K_A0000 - .word MTRR_FIX_4K_C0000 - .word MTRR_FIX_4K_C8000 - .word MTRR_FIX_4K_D0000 - .word MTRR_FIX_4K_D8000 - .word MTRR_FIX_4K_E0000 - .word MTRR_FIX_4K_E8000 - .word MTRR_FIX_4K_F0000 - .word MTRR_FIX_4K_F8000 -fixed_mtrr_list_size = . - fixed_mtrr_list -- To view, visit https://review.coreboot.org/c/coreboot/+/30814 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae9b584bc0d32a56be2e6e2b2e893897eb448aa5 Gerrit-Change-Number: 30814 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: Add support to disable PCIe WLAN dynamically
by Maulik V Vaghela (Code Review) 08 Feb '19

08 Feb '19

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30611 Change subject: soc/intel/cannonlake: Add support to disable PCIe WLAN dynamically ...................................................................... soc/intel/cannonlake: Add support to disable PCIe WLAN dynamically Ideally we should disable PCIe WLAN if CNVi is enabled and out of reset. This code adds support to achieve this. SoC code will check if CNVi is up or not and if is enabled, it'll disable PCIe WLAN. PCI WLAN device and function are board dependent and mainboard must implement function which returns PCI_DEVFN for WLAN. BUG=none BRANCH=none TEST=none Change-Id: Ief1896b3d915018edca136c26f4e834e0c9003ac Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/soc/intel/cannonlake/fsp_params.c 1 file changed, 44 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/30611/1 diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 8166dea..4225471 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -17,6 +17,8 @@ #include <console/console.h> #include <device/device.h> #include <device/pci.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> #include <fsp/api.h> #include <fsp/util.h> #include <intelblocks/xdci.h> @@ -25,6 +27,42 @@ #include <soc/ramstage.h> #include <string.h> +static bool is_cnvi_held_in_reset(void) +{ + struct device *dev = dev_find_slot(0, PCH_DEVFN_CNVI); + uint32_t reg = pci_read_config32(dev, PCI_VENDOR_ID); + + /* + * If vendor/device ID for CNVi reads as 0xffffffff, then it is safe to + * assume that it is being held in reset. + */ + if (reg == 0xffffffff) + return true; + + return false; +} + +/* + * Check if CNVi PCI device is released from reset. If yes, then the system is + * booting with CNVi module. In this case, the PCIe device for WiFi needs to + * be disabled. If CNVi device is held in reset, then disable it. + */ +static void wifi_device_update(void) +{ + struct device *dev; + unsigned int devfn; + + if (is_cnvi_held_in_reset()) + devfn = PCH_DEVFN_CNVI; + else + devfn = mainboard_get_wifi_device(); + + if (devfn != 0) { + dev = dev_find_slot(0, devfn); + dev->enabled = 0; + } +} + static void parse_devicetree(FSP_S_CONFIG *params) { struct device *dev = SA_DEV_ROOT; @@ -86,6 +124,7 @@ } mainboard_silicon_init_params(params); + wifi_device_update (); /* Unlock upper 8 bytes of RTC RAM */ params->PchLockDownRtcMemoryLock = 0; @@ -236,3 +275,8 @@ { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } + +__weak uint32_t mainboard_get_wifi_device(void) +{ + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/30611 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief1896b3d915018edca136c26f4e834e0c9003ac Gerrit-Change-Number: 30611 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Makefile.inc: Create a default SMMSTORE region
by Arthur Heymans (Code Review) 06 Feb '19

06 Feb '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30421 Change subject: Makefile.inc: Create a default SMMSTORE region ...................................................................... Makefile.inc: Create a default SMMSTORE region Change-Id: I7b7b75050e0139ea9a0a4f2ad3c0d69a482fb38b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Makefile.inc M src/drivers/smmstore/Kconfig M util/cbfstool/default-x86.fmd 3 files changed, 26 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/30421/1 diff --git a/Makefile.inc b/Makefile.inc index 8af291f..7dee1d2 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -869,11 +869,27 @@ endif # ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y) # +# X86 SMMSTORE FMAP region +# +# position, size and entry line of SMMSTORE relative to BIOS_BASE, if enabled +ifeq ($(CONFIG_SMMSTORE),y) +FMAP_SMMSTORE_BASE := $(call int-align, $(call int-add, $(FMAP_CONSOLE_BASE) \ + $(FMAP_CONSOLE_SIZE) $(FMAP_MRC_CACHE_SIZE)), 0x10000) +FMAP_SMMSTORE_SIZE := $(CONFIG_SMMSTORE_SIZE) +FMAP_SMMSTORE_ENTRY := SMMSTORE@$(FMAP_SMMSTORE_BASE) $(FMAP_SMMSTORE_SIZE) +else # ifeq ($(CONFIG_SMMSTORE),y) +FMAP_SMMSTORE_BASE := 0 +FMAP_SMMSTORE_SIZE := 0 +FMAP_SMMSTORE_ENTRY := +endif # ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y) + +# # X86 FMAP region # # # position, size -FMAP_FMAP_BASE := $(call int-add, $(FMAP_CONSOLE_SIZE) $(FMAP_MRC_CACHE_SIZE)) +FMAP_FMAP_BASE := $(call int-add, $(FMAP_CONSOLE_BASE) $(FMAP_CONSOLE_SIZE) \ + $(FMAP_MRC_CACHE_SIZE) $(FMAP_SMMSTORE_SIZE)) FMAP_FMAP_SIZE := 0x200 # @@ -947,6 +963,7 @@ -e "s,##FMAP_SIZE##,$(FMAP_FMAP_SIZE)," \ -e "s,##CONSOLE_ENTRY##,$(FMAP_CONSOLE_ENTRY)," \ -e "s,##MRC_CACHE_ENTRY##,$(FMAP_MRC_CACHE_ENTRY)," \ + -e "s,##SMMSTORE_ENTRY##,$(FMAP_SMMSTORE_ENTRY)," \ -e "s,##CBFS_BASE##,$(FMAP_CBFS_BASE)," \ -e "s,##CBFS_SIZE##,$(FMAP_CBFS_SIZE)," \ $(DEFAULT_FLASHMAP) > $@.tmp diff --git a/src/drivers/smmstore/Kconfig b/src/drivers/smmstore/Kconfig index 1ab3a5e..f2c97ab 100644 --- a/src/drivers/smmstore/Kconfig +++ b/src/drivers/smmstore/Kconfig @@ -37,4 +37,11 @@ string "SMM store file name" if SMMSTORE_IN_CBFS default "smm_store" +config SMMSTORE_SIZE + hex "size of the SMMSTORE FMAP region" + depends on !SMMSTORE_IN_CBFS + default 0x40000 + help + Set the size of the default SMMSTORE FMAP region. + endif diff --git a/util/cbfstool/default-x86.fmd b/util/cbfstool/default-x86.fmd index 174db1f..f0143e9 100644 --- a/util/cbfstool/default-x86.fmd +++ b/util/cbfstool/default-x86.fmd @@ -11,6 +11,7 @@ BIOS@##BIOS_BASE## ##BIOS_SIZE## { ##CONSOLE_ENTRY## ##MRC_CACHE_ENTRY## + ##SMMSTORE_ENTRY## FMAP@##FMAP_BASE## ##FMAP_SIZE## COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE## } -- To view, visit https://review.coreboot.org/c/coreboot/+/30421 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b7b75050e0139ea9a0a4f2ad3c0d69a482fb38b Gerrit-Change-Number: 30421 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Makefile.inc: Make sure the BIOS region is 64K aligned
by Arthur Heymans (Code Review) 06 Feb '19

06 Feb '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30420 Change subject: Makefile.inc: Make sure the BIOS region is 64K aligned ...................................................................... Makefile.inc: Make sure the BIOS region is 64K aligned If a non aligned CONFIG_CBFS_SIZE is used the region RW_MRC_CACHE and CONSOLE could end up non aligned. Currently this is only possible if the user messes with CONFIG_CBFS_SIZE in menuconfig, but better be safe than sorry. Change-Id: Ieb7e3c7112bd4b3f9733c36af21b1d59b3836811 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Makefile.inc 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/30420/1 diff --git a/Makefile.inc b/Makefile.inc index 85aa19e..8af291f 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -146,6 +146,7 @@ int-gt=$(if $(filter 1,$(words $1)),$(strip $1),$(shell expr $(call _toint,$(word 1,$1)) \> $(call _toint,$(word 2,$1)))) int-eq=$(if $(filter 1,$(words $1)),$(strip $1),$(shell expr $(call _toint,$(word 1,$1)) = $(call _toint,$(word 2,$1)))) int-align=$(shell A=$(call _toint,$1) B=$(call _toint,$2); expr $$A + $ \( $$B - \( $$A % $$B $ \) % $$B \) ) +int-align-down=$(shell A=$(call _toint,$1) B=$(call _toint,$2); expr $$A - $ $$A % $$B $ ) file-size=$(strip $(shell cat $1 | wc -c)) tolower=$(shell echo '$1' | tr '[:upper:]' '[:lower:]') toupper=$(shell echo '$1' | tr '[:lower:]' '[:upper:]') @@ -835,8 +836,8 @@ FMAP_ROM_SIZE := $(CONFIG_ROM_SIZE) # entire "BIOS" region (everything directly of concern to the host system) # relative to ROM_BASE -FMAP_BIOS_BASE := $(call int-subtract, $(CONFIG_ROM_SIZE) $(CONFIG_CBFS_SIZE)) -FMAP_BIOS_SIZE := $(shell echo $(CONFIG_CBFS_SIZE) | tr A-F a-f) +FMAP_BIOS_BASE := $(call int-align, $(call int-subtract, $(CONFIG_ROM_SIZE) $(CONFIG_CBFS_SIZE)), 0x10000) +FMAP_BIOS_SIZE := $(call int-align-down, $(shell echo $(CONFIG_CBFS_SIZE) | tr A-F a-f), 0x10000) # position and size of flashmap, relative to BIOS_BASE # -- To view, visit https://review.coreboot.org/c/coreboot/+/30420 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb7e3c7112bd4b3f9733c36af21b1d59b3836811 Gerrit-Change-Number: 30420 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Makefile.inc: Optimize generating the default x86 fmap
by Arthur Heymans (Code Review) 06 Feb '19

06 Feb '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30419 Change subject: Makefile.inc: Optimize generating the default x86 fmap ...................................................................... Makefile.inc: Optimize generating the default x86 fmap Put the FMAP FMAP region right above the coreboot region. The other regions like RW_MRC_CACHE and CONSOLE might have alignment requirements so it makes sense to put those on top. This also simplifies the generation code a little. Change-Id: I24fa6c89ecf85fb9002c0357f14aa970ee51b1df Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Makefile.inc M util/cbfstool/default-x86.fmd 2 files changed, 12 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/30419/1 diff --git a/Makefile.inc b/Makefile.inc index b25ac6b..85aa19e 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -838,19 +838,16 @@ FMAP_BIOS_BASE := $(call int-subtract, $(CONFIG_ROM_SIZE) $(CONFIG_CBFS_SIZE)) FMAP_BIOS_SIZE := $(shell echo $(CONFIG_CBFS_SIZE) | tr A-F a-f) # position and size of flashmap, relative to BIOS_BASE -FMAP_FMAP_BASE := 0 -FMAP_FMAP_SIZE := 0x200 # # X86 CONSOLE FMAP region # # position, size and entry line of CONSOLE relative to BIOS_BASE, if enabled +FMAP_CONSOLE_BASE := 0 ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y) -FMAP_CONSOLE_BASE := $(call int-add, $(FMAP_FMAP_BASE) $(FMAP_FMAP_SIZE)) FMAP_CONSOLE_SIZE := $(CONFIG_CONSOLE_SPI_FLASH_BUFFER_SIZE) FMAP_CONSOLE_ENTRY := CONSOLE@$(FMAP_CONSOLE_BASE) $(FMAP_CONSOLE_SIZE) else # ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y) -FMAP_CONSOLE_BASE := 0 FMAP_CONSOLE_SIZE := 0 FMAP_CONSOLE_ENTRY := endif # ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y) @@ -860,13 +857,8 @@ # # position, size and entry line of MRC_CACHE relative to BIOS_BASE, if enabled ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y) -ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y) -FMAP_MRC_CACHE_BASE := $(call int-align, $(call int-add, $(FMAP_CONSOLE_BASE) \ +FMAP_MRC_CACHE_BASE := $(call int-align, $(call int-add, $(FMAP_CONSOLE_BASE) \ $(FMAP_CONSOLE_SIZE)), 0x10000) -else -FMAP_MRC_CACHE_BASE := $(call int-align, $(call int-add, $(FMAP_FMAP_BASE) \ - $(FMAP_FMAP_SIZE)), 0x10000) -endif FMAP_MRC_CACHE_SIZE := $(CONFIG_MRC_SETTINGS_CACHE_SIZE) FMAP_MRC_CACHE_ENTRY := RW_MRC_CACHE@$(FMAP_MRC_CACHE_BASE) $(FMAP_MRC_CACHE_SIZE) else # ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y) @@ -876,14 +868,18 @@ endif # ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y) # +# X86 FMAP region +# +# +# position, size +FMAP_FMAP_BASE := $(call int-add, $(FMAP_CONSOLE_SIZE) $(FMAP_MRC_CACHE_SIZE)) +FMAP_FMAP_SIZE := 0x200 + +# # X86 COREBOOT default cbfs FMAP region # # position and size of CBFS, relative to BIOS_BASE -ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y) -FMAP_CBFS_BASE := $(call int-add, $(FMAP_MRC_CACHE_BASE) $(FMAP_MRC_CACHE_SIZE)) -else -FMAP_CBFS_BASE := $(call int-add, $(FMAP_CONSOLE_SIZE) $(FMAP_FMAP_SIZE)) -endif +FMAP_CBFS_BASE := $(call int-add, $(FMAP_FMAP_BASE) $(FMAP_FMAP_SIZE)) FMAP_CBFS_SIZE := $(call int-subtract, $(FMAP_BIOS_SIZE) $(FMAP_CBFS_BASE)) else # ifeq ($(CONFIG_ARCH_X86),y) DEFAULT_FLASHMAP:=$(top)/util/cbfstool/default.fmd diff --git a/util/cbfstool/default-x86.fmd b/util/cbfstool/default-x86.fmd index 1f1aa43..174db1f 100644 --- a/util/cbfstool/default-x86.fmd +++ b/util/cbfstool/default-x86.fmd @@ -9,9 +9,9 @@ FLASH@##ROM_BASE## ##ROM_SIZE## { BIOS@##BIOS_BASE## ##BIOS_SIZE## { - FMAP@##FMAP_BASE## ##FMAP_SIZE## ##CONSOLE_ENTRY## ##MRC_CACHE_ENTRY## + FMAP@##FMAP_BASE## ##FMAP_SIZE## COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE## } } -- To view, visit https://review.coreboot.org/c/coreboot/+/30419 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24fa6c89ecf85fb9002c0357f14aa970ee51b1df Gerrit-Change-Number: 30419 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

2 2

Change in ...coreboot[master]: libgfxinit: Add options to limit framebuffer size
by Nico Huber (Code Review) 06 Feb '19

06 Feb '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30585 Change subject: libgfxinit: Add options to limit framebuffer size ...................................................................... libgfxinit: Add options to limit framebuffer size Change-Id: I47fba063629260c3a2854caf7a73f1a1e933d063 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/device/Kconfig M src/drivers/intel/gma/hires_fb/gma.adb 2 files changed, 16 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/30585/1 diff --git a/src/device/Kconfig b/src/device/Kconfig index 85f1d65..f868d2f 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -445,6 +445,16 @@ def_bool y depends on VBE_LINEAR_FRAMEBUFFER || GENERIC_LINEAR_FRAMEBUFFER +config LINEAR_FRAMEBUFFER_MAX_WIDTH + int "Maximum width in pixels" + depends on MAINBOARD_USE_LIBGFXINIT && LINEAR_FRAMEBUFFER + default 4096 + +config LINEAR_FRAMEBUFFER_MAX_HEIGHT + int "Maximum height in pixels" + depends on MAINBOARD_USE_LIBGFXINIT && LINEAR_FRAMEBUFFER + default 4096 + endmenu # "Display" config SMBUS_HAS_AUX_CHANNELS diff --git a/src/drivers/intel/gma/hires_fb/gma.adb b/src/drivers/intel/gma/hires_fb/gma.adb index bd14132..1437ce2 100644 --- a/src/drivers/intel/gma/hires_fb/gma.adb +++ b/src/drivers/intel/gma/hires_fb/gma.adb @@ -1,3 +1,7 @@ +with CB.Config; + +use CB.Config; + with HW.GFX; with HW.GFX.Framebuffer_Filler; with HW.GFX.GMA; @@ -60,8 +64,8 @@ success : boolean; - min_h : pos32 := pos32'last; - min_v : pos32 := pos32'last; + min_h : pos32 := LINEAR_FRAMEBUFFER_MAX_WIDTH; + min_v : pos32 := LINEAR_FRAMEBUFFER_MAX_HEIGHT; begin lightup_ok := 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/30585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47fba063629260c3a2854caf7a73f1a1e933d063 Gerrit-Change-Number: 30585 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 7

Change in ...coreboot[master]: Hook up Kconfig Ada spec file
by Nico Huber (Code Review) 06 Feb '19

06 Feb '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30584 Change subject: Hook up Kconfig Ada spec file ...................................................................... Hook up Kconfig Ada spec file We generate a $(obj)/cb-config.ads once and copy it per stage that uses it to $(obj)/<stage>/cb-config.ads (to simplify the gnat-bind step). The Ada package is called `CB.Config`. As there was no `CB` package yet, add that too. Change-Id: I963a6517ef4bcf84f2c8e9ae8d24a0d6b971d2b0 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M Makefile M Makefile.inc M src/lib/Makefile.inc A src/lib/cb.ads 4 files changed, 22 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/30584/1 diff --git a/Makefile b/Makefile index f12b616..3acb97d 100644 --- a/Makefile +++ b/Makefile @@ -44,6 +44,7 @@ DOTCONFIG ?= $(top)/.config KCONFIG_CONFIG = $(DOTCONFIG) +KCONFIG_AUTOADS := $(obj)/cb-config.ads KCONFIG_AUTOHEADER := $(obj)/config.h KCONFIG_AUTOCONFIG := $(obj)/auto.conf KCONFIG_DEPENDENCIES := $(obj)/auto.conf.cmd @@ -51,10 +52,12 @@ KCONFIG_TRISTATE := $(obj)/tristate.conf KCONFIG_NEGATIVES := 1 KCONFIG_STRICT := 1 +KCONFIG_PACKAGE := CB.Config COREBOOT_EXPORTS += KCONFIG_CONFIG KCONFIG_AUTOHEADER KCONFIG_AUTOCONFIG COREBOOT_EXPORTS += KCONFIG_DEPENDENCIES KCONFIG_SPLITCONFIG KCONFIG_TRISTATE COREBOOT_EXPORTS += KCONFIG_NEGATIVES KCONFIG_STRICT +COREBOOT_EXPORTS += KCONFIG_AUTOADS KCONFIG_PACKAGE # directory containing the toplevel Makefile.inc TOPLEVEL := . @@ -179,6 +182,12 @@ $(KCONFIG_AUTOHEADER): $(KCONFIG_CONFIG) $(objutil)/kconfig/conf +$(MAKE) oldconfig +$(KCONFIG_AUTOADS): $(KCONFIG_AUTOHEADER) + true + +$(obj)/%/$(notdir $(KCONFIG_AUTOADS)): $(KCONFIG_AUTOADS) + cp $< $@ + # Add a new class of source/object files to the build system add-class= \ $(eval $(1)-srcs:=) \ @@ -263,6 +272,11 @@ # Eliminate duplicate mentions of source files in a class $(foreach class,$(classes),$(eval $(class)-srcs:=$(sort $($(class)-srcs)))) +# Build Kconfig .ads if necessary +ifeq ($(CONFIG_RAMSTAGE_ADA),y) +ramstage-srcs += $(obj)/ramstage/$(notdir $(KCONFIG_AUTOADS)) +endif + # To track dependencies, we need all Ada specification (.ads) files in # *-srcs. Extract / filter all specification files that have a matching # body (.adb) file here (specifications without a body are valid sources @@ -311,7 +325,7 @@ ifn$(EMPTY)def $(1)-objs_$(2)_template de$(EMPTY)fine $(1)-objs_$(2)_template ifn$(EMPTY)eq ($(filter ads adb,$(2)),) -$$(call src-to-obj,$1,$$(1).$2): $$(1).$2 $$(call create_ada_deps,$1,$$(call src-to-ali,$1,$$(1).$2)) $(KCONFIG_AUTOHEADER) $(4) +$$(call src-to-obj,$1,$$(1).$2): $$(1).$2 $$(call create_ada_deps,$1,$$(call src-to-ali,$1,$$(1).$2)) $(4) @printf " GCC $$$$(subst $$$$(obj)/,,$$$$(@))\n" $(GCC_$(1)) \ $$$$(ADAFLAGS_$(1)) $$$$(addprefix -I,$$$$($(1)-ada-dirs)) \ diff --git a/Makefile.inc b/Makefile.inc index b25ac6b..4292e79 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -210,7 +210,9 @@ bootblock-c-deps:=$$(OPTION_TABLE_H) $(foreach type,ads adb, \ $(foreach stage,$(COREBOOT_STANDARD_STAGES), \ - $(eval $(stage)-$(type)-deps := $(obj)/libgnat-$(ARCH-$(stage)-y)/libgnat.a))) + $(eval $(stage)-$(type)-deps := \ + $(obj)/$(stage)/$(notdir $(KCONFIG_AUTOADS)) \ + $(obj)/libgnat-$(ARCH-$(stage)-y)/libgnat.a))) # Add handler to copy linker scripts define generic-objs_ld_template_gen diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 2fd4e4c..1bfe9cd 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -295,6 +295,8 @@ $(obj)/%.elf.rmod: $(obj)/%.elf | $(RMODTOOL) $(RMODTOOL) -i $< -o $@ +ramstage-$(CONFIG_RAMSTAGE_ADA) += cb.ads + ifeq ($(CONFIG_RAMSTAGE_LIBHWBASE),y) to-ada-hex = $(eval $(1) := 16\\\#$(patsubst 0x%,%,$($(1)))\\\#) diff --git a/src/lib/cb.ads b/src/lib/cb.ads new file mode 100644 index 0000000..41a2a42 --- /dev/null +++ b/src/lib/cb.ads @@ -0,0 +1,2 @@ +package CB is +end CB; -- To view, visit https://review.coreboot.org/c/coreboot/+/30584 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I963a6517ef4bcf84f2c8e9ae8d24a0d6b971d2b0 Gerrit-Change-Number: 30584 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 6

Change in ...coreboot[master]: mb/lenovo/x200/gpio.c: Unclutter the code
by Arthur Heymans (Code Review) 06 Feb '19

06 Feb '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31187 Change subject: mb/lenovo/x200/gpio.c: Unclutter the code ...................................................................... mb/lenovo/x200/gpio.c: Unclutter the code Some settings don't make sense like specifying input/output on native ports or direction on input ports. Change-Id: Ib37837b9cdb8bb05e2523e0c43cc71fe4fbf243b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/x200/gpio.c 1 file changed, 5 insertions(+), 186 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/31187/1 diff --git a/src/mainboard/lenovo/x200/gpio.c b/src/mainboard/lenovo/x200/gpio.c index 5906fc3..2da4097 100644 --- a/src/mainboard/lenovo/x200/gpio.c +++ b/src/mainboard/lenovo/x200/gpio.c @@ -14,7 +14,6 @@ #include <southbridge/intel/common/gpio.h> const struct pch_gpio_set1 pch_gpio_set1_mode = { - .gpio0 = GPIO_MODE_NATIVE, .gpio1 = GPIO_MODE_GPIO, .gpio2 = GPIO_MODE_GPIO, .gpio3 = GPIO_MODE_GPIO, @@ -24,32 +23,19 @@ .gpio7 = GPIO_MODE_GPIO, .gpio8 = GPIO_MODE_GPIO, .gpio9 = GPIO_MODE_GPIO, - .gpio10 = GPIO_MODE_NATIVE, - .gpio11 = GPIO_MODE_NATIVE, - .gpio12 = GPIO_MODE_NATIVE, .gpio13 = GPIO_MODE_GPIO, - .gpio14 = GPIO_MODE_NATIVE, - .gpio15 = GPIO_MODE_NATIVE, - .gpio16 = GPIO_MODE_NATIVE, .gpio17 = GPIO_MODE_GPIO, .gpio18 = GPIO_MODE_GPIO, .gpio19 = GPIO_MODE_GPIO, .gpio20 = GPIO_MODE_GPIO, .gpio21 = GPIO_MODE_GPIO, .gpio22 = GPIO_MODE_GPIO, - .gpio23 = GPIO_MODE_NATIVE, .gpio24 = GPIO_MODE_GPIO, - .gpio25 = GPIO_MODE_NATIVE, - .gpio26 = GPIO_MODE_NATIVE, .gpio27 = GPIO_MODE_GPIO, .gpio28 = GPIO_MODE_GPIO, - .gpio29 = GPIO_MODE_NATIVE, - .gpio30 = GPIO_MODE_NATIVE, - .gpio31 = GPIO_MODE_NATIVE, }; const struct pch_gpio_set1 pch_gpio_set1_direction = { - .gpio0 = GPIO_DIR_OUTPUT, .gpio1 = GPIO_DIR_INPUT, .gpio2 = GPIO_DIR_INPUT, .gpio3 = GPIO_DIR_INPUT, @@ -59,238 +45,71 @@ .gpio7 = GPIO_DIR_INPUT, .gpio8 = GPIO_DIR_INPUT, .gpio9 = GPIO_DIR_OUTPUT, - .gpio10 = GPIO_DIR_INPUT, - .gpio11 = GPIO_DIR_INPUT, - .gpio12 = GPIO_DIR_OUTPUT, .gpio13 = GPIO_DIR_INPUT, - .gpio14 = GPIO_DIR_INPUT, - .gpio15 = GPIO_DIR_OUTPUT, - .gpio16 = GPIO_DIR_OUTPUT, .gpio17 = GPIO_DIR_INPUT, .gpio18 = GPIO_DIR_INPUT, .gpio19 = GPIO_DIR_OUTPUT, .gpio20 = GPIO_DIR_OUTPUT, .gpio21 = GPIO_DIR_INPUT, .gpio22 = GPIO_DIR_OUTPUT, - .gpio23 = GPIO_DIR_INPUT, .gpio24 = GPIO_DIR_INPUT, - .gpio25 = GPIO_DIR_OUTPUT, - .gpio26 = GPIO_DIR_OUTPUT, .gpio27 = GPIO_DIR_OUTPUT, .gpio28 = GPIO_DIR_OUTPUT, - .gpio29 = GPIO_DIR_INPUT, - .gpio30 = GPIO_DIR_INPUT, - .gpio31 = GPIO_DIR_INPUT, }; const struct pch_gpio_set1 pch_gpio_set1_level = { - .gpio0 = GPIO_LEVEL_HIGH, - .gpio1 = GPIO_LEVEL_HIGH, - .gpio2 = GPIO_LEVEL_HIGH, - .gpio3 = GPIO_LEVEL_HIGH, - .gpio4 = GPIO_LEVEL_HIGH, - .gpio5 = GPIO_LEVEL_HIGH, - .gpio6 = GPIO_LEVEL_LOW, - .gpio7 = GPIO_LEVEL_LOW, - .gpio8 = GPIO_LEVEL_HIGH, .gpio9 = GPIO_LEVEL_HIGH, - .gpio10 = GPIO_LEVEL_HIGH, - .gpio11 = GPIO_LEVEL_HIGH, - .gpio12 = GPIO_LEVEL_LOW, - .gpio13 = GPIO_LEVEL_HIGH, - .gpio14 = GPIO_LEVEL_HIGH, - .gpio15 = GPIO_LEVEL_HIGH, - .gpio16 = GPIO_LEVEL_LOW, - .gpio17 = GPIO_LEVEL_HIGH, - .gpio18 = GPIO_LEVEL_LOW, .gpio19 = GPIO_LEVEL_HIGH, .gpio20 = GPIO_LEVEL_HIGH, - .gpio21 = GPIO_LEVEL_HIGH, .gpio22 = GPIO_LEVEL_HIGH, - .gpio23 = GPIO_LEVEL_HIGH, - .gpio24 = GPIO_LEVEL_HIGH, - .gpio25 = GPIO_LEVEL_HIGH, - .gpio26 = GPIO_LEVEL_LOW, .gpio27 = GPIO_LEVEL_LOW, .gpio28 = GPIO_LEVEL_LOW, - .gpio29 = GPIO_LEVEL_HIGH, - .gpio30 = GPIO_LEVEL_HIGH, - .gpio31 = GPIO_LEVEL_HIGH, -}; - -const struct pch_gpio_set1 pch_gpio_set1_blink = { - .gpio0 = GPIO_NO_BLINK, - .gpio1 = GPIO_NO_BLINK, - .gpio2 = GPIO_NO_BLINK, - .gpio3 = GPIO_NO_BLINK, - .gpio4 = GPIO_NO_BLINK, - .gpio5 = GPIO_NO_BLINK, - .gpio6 = GPIO_NO_BLINK, - .gpio7 = GPIO_NO_BLINK, - .gpio8 = GPIO_NO_BLINK, - .gpio9 = GPIO_NO_BLINK, - .gpio10 = GPIO_NO_BLINK, - .gpio11 = GPIO_NO_BLINK, - .gpio12 = GPIO_NO_BLINK, - .gpio13 = GPIO_NO_BLINK, - .gpio14 = GPIO_NO_BLINK, - .gpio15 = GPIO_NO_BLINK, - .gpio16 = GPIO_NO_BLINK, - .gpio17 = GPIO_NO_BLINK, - .gpio18 = GPIO_NO_BLINK, - .gpio19 = GPIO_NO_BLINK, - .gpio20 = GPIO_NO_BLINK, - .gpio21 = GPIO_NO_BLINK, - .gpio22 = GPIO_NO_BLINK, - .gpio23 = GPIO_NO_BLINK, - .gpio24 = GPIO_NO_BLINK, - .gpio25 = GPIO_NO_BLINK, - .gpio26 = GPIO_NO_BLINK, - .gpio27 = GPIO_NO_BLINK, - .gpio28 = GPIO_NO_BLINK, - .gpio29 = GPIO_NO_BLINK, - .gpio30 = GPIO_NO_BLINK, - .gpio31 = GPIO_NO_BLINK, }; const struct pch_gpio_set1 pch_gpio_set1_invert = { - .gpio0 = GPIO_NO_INVERT, - .gpio1 = GPIO_INVERT, - .gpio2 = GPIO_NO_INVERT, - .gpio3 = GPIO_NO_INVERT, - .gpio4 = GPIO_NO_INVERT, - .gpio5 = GPIO_NO_INVERT, - .gpio6 = GPIO_NO_INVERT, - .gpio7 = GPIO_NO_INVERT, - .gpio8 = GPIO_INVERT, - .gpio9 = GPIO_NO_INVERT, - .gpio10 = GPIO_NO_INVERT, - .gpio11 = GPIO_NO_INVERT, - .gpio12 = GPIO_NO_INVERT, - .gpio13 = GPIO_NO_INVERT, - .gpio14 = GPIO_NO_INVERT, - .gpio15 = GPIO_NO_INVERT, - .gpio16 = GPIO_NO_INVERT, - .gpio17 = GPIO_NO_INVERT, - .gpio18 = GPIO_NO_INVERT, - .gpio19 = GPIO_NO_INVERT, - .gpio20 = GPIO_NO_INVERT, - .gpio21 = GPIO_NO_INVERT, - .gpio22 = GPIO_NO_INVERT, - .gpio23 = GPIO_NO_INVERT, - .gpio24 = GPIO_NO_INVERT, - .gpio25 = GPIO_NO_INVERT, - .gpio26 = GPIO_NO_INVERT, - .gpio27 = GPIO_NO_INVERT, - .gpio28 = GPIO_NO_INVERT, - .gpio29 = GPIO_NO_INVERT, - .gpio30 = GPIO_NO_INVERT, - .gpio31 = GPIO_NO_INVERT, + .gpio1 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_blink = { }; const struct pch_gpio_set2 pch_gpio_set2_mode = { - .gpio32 = GPIO_MODE_NATIVE, .gpio33 = GPIO_MODE_GPIO, .gpio34 = GPIO_MODE_GPIO, - .gpio35 = GPIO_MODE_NATIVE, .gpio36 = GPIO_MODE_GPIO, .gpio37 = GPIO_MODE_GPIO, .gpio38 = GPIO_MODE_GPIO, .gpio39 = GPIO_MODE_GPIO, - .gpio40 = GPIO_MODE_NATIVE, .gpio41 = GPIO_MODE_GPIO, .gpio42 = GPIO_MODE_GPIO, - .gpio43 = GPIO_MODE_NATIVE, - .gpio44 = GPIO_MODE_NATIVE, - .gpio45 = GPIO_MODE_NATIVE, - .gpio46 = GPIO_MODE_NATIVE, - .gpio47 = GPIO_MODE_NATIVE, .gpio48 = GPIO_MODE_GPIO, .gpio49 = GPIO_MODE_GPIO, - .gpio50 = GPIO_MODE_NATIVE, - .gpio51 = GPIO_MODE_NATIVE, - .gpio52 = GPIO_MODE_NATIVE, - .gpio53 = GPIO_MODE_NATIVE, - .gpio54 = GPIO_MODE_NATIVE, - .gpio55 = GPIO_MODE_NATIVE, .gpio56 = GPIO_MODE_GPIO, .gpio57 = GPIO_MODE_GPIO, - .gpio58 = GPIO_MODE_NATIVE, - .gpio59 = GPIO_MODE_NATIVE, - .gpio60 = GPIO_MODE_NATIVE, - .gpio61 = GPIO_MODE_NATIVE, - .gpio62 = GPIO_MODE_NATIVE, - .gpio63 = GPIO_MODE_NATIVE, }; const struct pch_gpio_set2 pch_gpio_set2_direction = { - .gpio32 = GPIO_DIR_INPUT, .gpio33 = GPIO_DIR_OUTPUT, .gpio34 = GPIO_DIR_OUTPUT, - .gpio35 = GPIO_DIR_OUTPUT, .gpio36 = GPIO_DIR_INPUT, .gpio37 = GPIO_DIR_INPUT, .gpio38 = GPIO_DIR_INPUT, .gpio39 = GPIO_DIR_INPUT, - .gpio40 = GPIO_DIR_INPUT, .gpio41 = GPIO_DIR_OUTPUT, .gpio42 = GPIO_DIR_OUTPUT, - .gpio43 = GPIO_DIR_INPUT, - .gpio44 = GPIO_DIR_INPUT, - .gpio45 = GPIO_DIR_INPUT, - .gpio46 = GPIO_DIR_INPUT, - .gpio47 = GPIO_DIR_INPUT, .gpio48 = GPIO_DIR_INPUT, .gpio49 = GPIO_DIR_OUTPUT, - .gpio50 = GPIO_DIR_INPUT, - .gpio51 = GPIO_DIR_OUTPUT, - .gpio52 = GPIO_DIR_INPUT, - .gpio53 = GPIO_DIR_OUTPUT, - .gpio54 = GPIO_DIR_INPUT, - .gpio55 = GPIO_DIR_OUTPUT, .gpio56 = GPIO_DIR_INPUT, .gpio57 = GPIO_DIR_INPUT, - .gpio58 = GPIO_DIR_INPUT, - .gpio59 = GPIO_DIR_INPUT, - .gpio60 = GPIO_DIR_INPUT, - .gpio61 = GPIO_DIR_OUTPUT, - .gpio62 = GPIO_DIR_OUTPUT, - .gpio63 = GPIO_DIR_OUTPUT, }; const struct pch_gpio_set2 pch_gpio_set2_level = { - .gpio32 = GPIO_LEVEL_HIGH, .gpio33 = GPIO_LEVEL_HIGH, .gpio34 = GPIO_LEVEL_LOW, - .gpio35 = GPIO_LEVEL_LOW, - .gpio36 = GPIO_LEVEL_HIGH, - .gpio37 = GPIO_LEVEL_LOW, - .gpio38 = GPIO_LEVEL_HIGH, - .gpio39 = GPIO_LEVEL_LOW, - .gpio40 = GPIO_LEVEL_HIGH, .gpio41 = GPIO_LEVEL_HIGH, .gpio42 = GPIO_LEVEL_HIGH, - .gpio43 = GPIO_LEVEL_HIGH, - .gpio44 = GPIO_LEVEL_HIGH, - .gpio45 = GPIO_LEVEL_HIGH, - .gpio46 = GPIO_LEVEL_HIGH, - .gpio47 = GPIO_LEVEL_HIGH, - .gpio48 = GPIO_LEVEL_HIGH, .gpio49 = GPIO_LEVEL_HIGH, - .gpio50 = GPIO_LEVEL_HIGH, - .gpio51 = GPIO_LEVEL_HIGH, - .gpio52 = GPIO_LEVEL_HIGH, - .gpio53 = GPIO_LEVEL_HIGH, - .gpio54 = GPIO_LEVEL_HIGH, - .gpio55 = GPIO_LEVEL_HIGH, - .gpio56 = GPIO_LEVEL_HIGH, - .gpio57 = GPIO_LEVEL_LOW, - .gpio58 = GPIO_LEVEL_HIGH, - .gpio59 = GPIO_LEVEL_HIGH, - .gpio60 = GPIO_LEVEL_HIGH, - .gpio61 = GPIO_LEVEL_LOW, - .gpio62 = GPIO_LEVEL_LOW, - .gpio63 = GPIO_LEVEL_LOW, }; const struct pch_gpio_map mainboard_gpio_map = { -- To view, visit https://review.coreboot.org/c/coreboot/+/31187 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib37837b9cdb8bb05e2523e0c43cc71fe4fbf243b Gerrit-Change-Number: 31187 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 5

Change in ...coreboot[master]: mb/roda/rk9: Use common code to set up southbridge GPIO's
by Arthur Heymans (Code Review) 06 Feb '19

06 Feb '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31186 Change subject: mb/roda/rk9: Use common code to set up southbridge GPIO's ...................................................................... mb/roda/rk9: Use common code to set up southbridge GPIO's Change-Id: I2057bf66435fd9113cdb1eef4c273f66b07a5a79 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/roda/rk9/Makefile.inc A src/mainboard/roda/rk9/gpio.c M src/mainboard/roda/rk9/romstage.c 3 files changed, 144 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/31186/1 diff --git a/src/mainboard/roda/rk9/Makefile.inc b/src/mainboard/roda/rk9/Makefile.inc index f92382ee..7ff1588 100644 --- a/src/mainboard/roda/rk9/Makefile.inc +++ b/src/mainboard/roda/rk9/Makefile.inc @@ -13,6 +13,8 @@ ## GNU General Public License for more details. ## +romstage-y = gpio.c + ramstage-$(CONFIG_CARDBUS_PLUGIN_SUPPORT) += ti_pci7xx1.c ramstage-y += cstates.c ramstage-y += blc.c diff --git a/src/mainboard/roda/rk9/gpio.c b/src/mainboard/roda/rk9/gpio.c new file mode 100644 index 0000000..4e1ebe3 --- /dev/null +++ b/src/mainboard/roda/rk9/gpio.c @@ -0,0 +1,140 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_OUTPUT, + .gpio11 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_OUTPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_OUTPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio10 = GPIO_LEVEL_LOW, + .gpio11 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_LOW, + .gpio13 = GPIO_LEVEL_LOW, + .gpio18 = GPIO_LEVEL_LOW, + .gpio20 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio60 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_OUTPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_HIGH, + .gpio56 = GPIO_LEVEL_LOW, + .gpio60 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, +}; diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c index b88671c..ff8bc87 100644 --- a/src/mainboard/roda/rk9/romstage.c +++ b/src/mainboard/roda/rk9/romstage.c @@ -27,6 +27,7 @@ #include <cbmem.h> #include <romstage_handoff.h> #include <console/console.h> +#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/i82801ix/i82801ix.h> #include <northbridge/intel/gm45/gm45.h> #include <superio/smsc/lpc47n227/lpc47n227.h> @@ -34,32 +35,6 @@ #define LPC_DEV PCI_DEV(0, 0x1f, 0) #define SERIAL_DEV PNP_DEV(0x2e, LPC47N227_SP1) -static void default_southbridge_gpio_setup(void) -{ - /* Enable GPIOs [31:0]. */ - outl(0x197e7dfe, DEFAULT_GPIOBASE + 0x00); - /* Set input/output mode [31:0] (0 == out, 1 == in). */ - outl(0xe0ea43fe, DEFAULT_GPIOBASE + 0x04); - /* Set gpio levels [31:0]. orig: 0x01140800 (~SATA0, ~SATA1, GSM, BT, - WLAN, ~ANTMUX, ~GPIO12, - ~SUSPWR, SMBALERT) */ - outl(0x00000800, DEFAULT_GPIOBASE + 0x0c); - - /* Disable blink [31:0]. */ - outl(0x00000000, DEFAULT_GPIOBASE + 0x18); - /* Set input inversion [31:0]. */ - outl(0x00000182, DEFAULT_GPIOBASE + 0x2c); - - /* Enable GPIOs [60:32]. */ - outl(0x130300fe, DEFAULT_GPIOBASE + 0x30); - /* Set input/output mode [60:32] (0 == out, 1 == in). */ - outl(0x0e55ffb0, DEFAULT_GPIOBASE + 0x34); - /* Set gpio levels [60:32]. orig: 0x10020046 (LNKALERT, ~ATAIO, - DMITERM, TXT, ~CLKSATA, - GPS, AUDIO) */ - outl(0x10020042, DEFAULT_GPIOBASE + 0x38); -} - static void early_lpc_setup(void) { /* Set up SuperIO LPC forwards */ @@ -142,7 +117,7 @@ gm45_early_reset(); } - default_southbridge_gpio_setup(); + setup_pch_gpios(&mainboard_gpio_map); /* ASPM related setting, set early by original BIOS. */ DMIBAR16(0x204) &= ~(3 << 10); -- To view, visit https://review.coreboot.org/c/coreboot/+/31186 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2057bf66435fd9113cdb1eef4c273f66b07a5a79 Gerrit-Change-Number: 31186 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/lenovo/t400: Remove RCBA replay
by Arthur Heymans (Code Review) 06 Feb '19

06 Feb '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31188 Change subject: mb/lenovo/t400: Remove RCBA replay ...................................................................... mb/lenovo/t400: Remove RCBA replay his either sets unwanted or unnecessary settings. Also this RCBA replay did not even originate from the T400 as this code was copied from the Thinkpad x200 code on which this replay was already removed in 7bcd062 'mb/lenovo/x200: Remove RCBA replay' Change-Id: Iac6846d43395e342897e03c1ad31387638bcac64 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/t400/romstage.c 1 file changed, 0 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/31188/1 diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index 1a708ae..5020c85 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -143,39 +143,6 @@ i82801ix_dmi_poll_vc1(); MCHBAR16(SSKPD_MCHBAR) = 0xCAFE; - /* Enable ethernet. */ - RCBA32(0x3414) &= ~0x20; - - RCBA32(0x0238) = 0x00543210; - RCBA32(0x0240) = 0x009c0b02; - RCBA32(0x0244) = 0x00a20b1a; - RCBA32(0x0248) = 0x005402cb; - RCBA32(0x0254) = 0x00470966; - RCBA32(0x0258) = 0x00470473; - RCBA32(0x0260) = 0x00e90825; - RCBA32(0x0278) = 0x00bc0efb; - RCBA32(0x027c) = 0x00c00f0b; - RCBA32(0x0280) = 0x00670000; - RCBA32(0x0284) = 0x006d0000; - RCBA32(0x0288) = 0x00600b4e; - RCBA32(0x1e10) = 0x00020800; - RCBA32(0x1e18) = 0x36ea00a0; - RCBA32(0x1e80) = 0x000c0801; - RCBA32(0x1e84) = 0x000200f0; - RCBA32(0x2028) = 0x04c8f95e; - RCBA32(0x202c) = 0x055c095e; - RCBA32(0x204c) = 0x001ffc00; - RCBA32(0x2050) = 0x00100fff; - RCBA32(0x2090) = 0x37000000; - RCBA32(0x20b0) = 0x0c000000; - RCBA32(0x20d0) = 0x09000000; - RCBA32(0x20f0) = 0x05000000; - RCBA32(0x3400) = 0x0000001c; - RCBA32(0x3410) = 0x00100461; - RCBA32(0x3414) = 0x00000000; - RCBA32(0x341c) = 0xbf4f001f; - RCBA32(0x3420) = 0x00000000; - RCBA32(0x3430) = 0x00000001; init_iommu(); -- To view, visit https://review.coreboot.org/c/coreboot/+/31188 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac6846d43395e342897e03c1ad31387638bcac64 Gerrit-Change-Number: 31188 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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coreboot-gerrit January 2019