coreboot-gerrit January 2019

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Change in ...coreboot[master]: mb/emulation/qemu-i440fx: use car for e820
by Thomas Heijligen (Code Review) 05 Feb '19

05 Feb '19

Thomas Heijligen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30849 Change subject: mb/emulation/qemu-i440fx: use car for e820 ...................................................................... mb/emulation/qemu-i440fx: use car for e820 Use cache as ram to store e820 table size and read index Change-Id: I98f1c97e3ca33a12620cdd073c76fd4e271f1fcc Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com> --- M src/mainboard/emulation/qemu-i440fx/fw_cfg.c 1 file changed, 13 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/30849/1 diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c index 1890e66..e261bba 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c @@ -17,6 +17,7 @@ #include <console/console.h> #include <arch/io.h> #include <arch/acpigen.h> +#include <arch/early_variables.h> #include <commonlib/endian.h> #include "fw_cfg.h" @@ -25,21 +26,22 @@ #define FW_CFG_PORT_CTL 0x0510 #define FW_CFG_PORT_DATA 0x0511 -static unsigned char fw_cfg_detected = 0xff; -//static FWCfgFiles *fw_files; +static int fw_cfg_detected CAR_GLOBAL; static int fw_cfg_present(void) { static const char qsig[] = "QEMU"; unsigned char sig[4]; + int detected = 0; - if (fw_cfg_detected == 0xff) { + if (car_get_var(fw_cfg_detected) == 0) { fw_cfg_get(FW_CFG_SIGNATURE, sig, sizeof(sig)); - fw_cfg_detected = (memcmp(sig, qsig, 4) == 0) ? 1 : 0; + detected = memcmp(sig, qsig, 4) == 0; printk(BIOS_INFO, "QEMU: firmware config interface %s\n", - fw_cfg_detected ? "detected" : "not found"); + detected ? "detected" : "not found"); + car_set_var(fw_cfg_detected, detected + 1); } - return fw_cfg_detected; + return car_get_var(fw_cfg_detected) - 1; } static void fw_cfg_select(int entry) @@ -83,8 +85,8 @@ return fw_cfg_find_file(file, name); } -static uint32_t fw_cfg_e820_size; -static uint32_t fw_cfg_e820_pos; +static uint32_t fw_cfg_e820_size CAR_GLOBAL; +static uint32_t fw_cfg_e820_pos CAR_GLOBAL; int fw_cfg_e820_select(void) { @@ -99,11 +101,12 @@ int fw_cfg_e820_read(FwCfgE820Entry *entry) { - if (fw_cfg_e820_pos + sizeof(*entry) > fw_cfg_e820_size) + if (car_get_var(fw_cfg_e820_pos) + sizeof(*entry) + > car_get_var(fw_cfg_e820_size)) return -1; fw_cfg_read(entry, sizeof(*entry)); - fw_cfg_e820_pos += sizeof(*entry); + car_get_var(fw_cfg_e820_pos) += sizeof(*entry); return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/30849 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I98f1c97e3ca33a12620cdd073c76fd4e271f1fcc Gerrit-Change-Number: 30849 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/emulation/qemu-i440fx: add e820 interface
by Thomas Heijligen (Code Review) 05 Feb '19

05 Feb '19

Thomas Heijligen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30848 Change subject: mb/emulation/qemu-i440fx: add e820 interface ...................................................................... mb/emulation/qemu-i440fx: add e820 interface Qemu provides e820 table at fw_cfg interface. Add functions to access it. Change-Id: I547bc7fef09999baa28149a6325cbca91e31e99b Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com> --- M src/mainboard/emulation/qemu-i440fx/fw_cfg.c M src/mainboard/emulation/qemu-i440fx/fw_cfg.h 2 files changed, 30 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/30848/1 diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c index c5d6253..1890e66 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c @@ -83,6 +83,30 @@ return fw_cfg_find_file(file, name); } +static uint32_t fw_cfg_e820_size; +static uint32_t fw_cfg_e820_pos; + +int fw_cfg_e820_select(void) +{ + FWCfgFile file; + + if (!fw_cfg_present() || fw_cfg_find_file(&file, "etc/e820")) + return -1; + fw_cfg_select(file.select); + fw_cfg_e820_size = file.size; + return 0; +} + +int fw_cfg_e820_read(FwCfgE820Entry *entry) +{ + if (fw_cfg_e820_pos + sizeof(*entry) > fw_cfg_e820_size) + return -1; + + fw_cfg_read(entry, sizeof(*entry)); + fw_cfg_e820_pos += sizeof(*entry); + return 0; +} + int fw_cfg_max_cpus(void) { unsigned short max_cpus; diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg.h b/src/mainboard/emulation/qemu-i440fx/fw_cfg.h index b5cdb92..eb07847 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg.h +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg.h @@ -18,5 +18,11 @@ int fw_cfg_check_file(FWCfgFile *file, const char *name); int fw_cfg_max_cpus(void); unsigned long fw_cfg_smbios_tables(int *handle, unsigned long *current); +/* + * Do not call any other fw_cfg_ function between fw_cfg_e820_select and + * fw_cfg_e820_read. This causes undefind behavior. + */ +int fw_cfg_e820_select(void); +int fw_cfg_e820_read(FwCfgE820Entry *entry); #endif /* FW_CFG_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30848 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I547bc7fef09999baa28149a6325cbca91e31e99b Gerrit-Change-Number: 30848 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/emulation/qemu-440fx: remove mm file listing
by Thomas Heijligen (Code Review) 05 Feb '19

05 Feb '19

Thomas Heijligen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30847 Change subject: mb/emulation/qemu-440fx: remove mm file listing ...................................................................... mb/emulation/qemu-440fx: remove mm file listing Remove memory maped copy of the file list to use it also in romstage. fw_cfg_find_file search directly for the file on data port. Change-Id: Ie97ed3f0c98a5bb18a35ab0eaf8c4777a53e5779 Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com> --- M src/mainboard/emulation/qemu-i440fx/fw_cfg.c 1 file changed, 14 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/30847/1 diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c index 957e9d2..c5d6253 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c @@ -26,7 +26,7 @@ #define FW_CFG_PORT_DATA 0x0511 static unsigned char fw_cfg_detected = 0xff; -static FWCfgFiles *fw_files; +//static FWCfgFiles *fw_files; static int fw_cfg_present(void) { @@ -58,49 +58,29 @@ fw_cfg_read(dst, dstlen); } -static void fw_cfg_init_file(void) +static int fw_cfg_find_file(FWCfgFile *file, const char *name) { - u32 i, size, count = 0; + uint32_t count = 0; - if (fw_files != NULL) - return; + fw_cfg_select(FW_CFG_FILE_DIR); + fw_cfg_read(&count, sizeof(count)); - fw_cfg_get(FW_CFG_FILE_DIR, &count, sizeof(count)); - count = swab32(count); - size = count * sizeof(FWCfgFile) + sizeof(count); - printk(BIOS_DEBUG, "QEMU: %d files in fw_cfg\n", count); - fw_files = malloc(size); - fw_cfg_get(FW_CFG_FILE_DIR, fw_files, size); - fw_files->count = swab32(fw_files->count); - for (i = 0; i < count; i++) { - fw_files->f[i].size = swab32(fw_files->f[i].size); - fw_files->f[i].select = swab16(fw_files->f[i].select); - printk(BIOS_DEBUG, "QEMU: %s [size=%d]\n", - fw_files->f[i].name, fw_files->f[i].size); + for (int i = 0; i < count; i++) { + fw_cfg_read(file, sizeof(*file)); + if (strcmp(file->name, name) == 0) { + file->size = be32_to_cpu(file->size); + file->select = be16_to_cpu(file->select); + return 0; + } } -} - -static FWCfgFile *fw_cfg_find_file(const char *name) -{ - int i; - - fw_cfg_init_file(); - for (i = 0; i < fw_files->count; i++) - if (strcmp(fw_files->f[i].name, name) == 0) - return fw_files->f + i; - return NULL; + return -1; } int fw_cfg_check_file(FWCfgFile *file, const char *name) { - FWCfgFile *f; if (!fw_cfg_present()) return -1; - f = fw_cfg_find_file(name); - if (!f) - return -1; - *file = *f; - return 0; + return fw_cfg_find_file(file, name); } int fw_cfg_max_cpus(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/30847 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie97ed3f0c98a5bb18a35ab0eaf8c4777a53e5779 Gerrit-Change-Number: 30847 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/octopus: Add USB ACPI configuration for CNVi BT module
by Karthik Ramasubramanian (Code Review) 05 Feb '19

05 Feb '19

Hello Karthikeyan Ramasubramanian, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31183 to review the following change. Change subject: mb/google/octopus: Add USB ACPI configuration for CNVi BT module ...................................................................... mb/google/octopus: Add USB ACPI configuration for CNVi BT module This change enables exporting the reset GPIO for CNVi Bluetooth module to the kernel for use in an rf-kill operation. BUG=b:123296264 BRANCH=octopus TEST=Boots to ChromeOS. Checked the SSDT table to ensure that the reset gpio is exported under the device \_SB_.PCI0.XHCI.RHUB.HS09. Ensured that the kernel btusb driver is able to find the exported GPIO in the devices with CNVi BT module. Change-Id: I10f28bfe705da5104d709ae2ed91a8ae003fa639 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/octopus/variants/baseboard/devicetree.cb 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/31183/1 diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index bbaa312..1d36b53 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -154,6 +154,12 @@ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_109)" device usb 2.2 on end end + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_109)" + device usb 2.9 on end + end end end end # - XHCI -- To view, visit https://review.coreboot.org/c/coreboot/+/31183 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10f28bfe705da5104d709ae2ed91a8ae003fa639 Gerrit-Change-Number: 31183 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/apollolake: Update XHCI ports for GLK in ACPI tables
by Furquan Shaikh (Code Review) 05 Feb '19

05 Feb '19

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31172 Change subject: soc/intel/apollolake: Update XHCI ports for GLK in ACPI tables ...................................................................... soc/intel/apollolake: Update XHCI ports for GLK in ACPI tables GLK has a dedicated USB2 port that is used specifically for CNVi BT. This requires that the ACPI tables define an additional USB 2 port which results in _ADR for USB 3 ports being different for GLK than APL. This change splits the ports in xhci.asl into APL and GLK specific ports.asl and selects the appropriate file based on CONFIG_SOC_INTEL_GLK. It also adds support for returning HS09 for GLK if ACPI name is requested for that port. BUG=b:123670712 BRANCH=octopus TEST=Verified that generated DSDT for octopus(GLK) includes HS09 and for reef(APL) does not include HS09 definition. Change-Id: I2d3d3690ec9ea1f6e35c38c3b3cbb82e961b7950 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/apollolake/acpi/xhci.asl A src/soc/intel/apollolake/acpi/xhci_apl_ports.asl A src/soc/intel/apollolake/acpi/xhci_glk_ports.asl M src/soc/intel/apollolake/chip.c 4 files changed, 77 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/31172/1 diff --git a/src/soc/intel/apollolake/acpi/xhci.asl b/src/soc/intel/apollolake/acpi/xhci.asl index 8222cb5..7632af6 100644 --- a/src/soc/intel/apollolake/acpi/xhci.asl +++ b/src/soc/intel/apollolake/acpi/xhci.asl @@ -34,22 +34,10 @@ /* Root Hub */ Name (_ADR, Zero) - /* USB2 */ - Device (HS01) { Name (_ADR, 1) } - Device (HS02) { Name (_ADR, 2) } - Device (HS03) { Name (_ADR, 3) } - Device (HS04) { Name (_ADR, 4) } - Device (HS05) { Name (_ADR, 5) } - Device (HS06) { Name (_ADR, 6) } - Device (HS07) { Name (_ADR, 7) } - Device (HS08) { Name (_ADR, 8) } - - /* USB3 */ - Device (SS01) { Name (_ADR, 9) } - Device (SS02) { Name (_ADR, 10) } - Device (SS03) { Name (_ADR, 11) } - Device (SS04) { Name (_ADR, 12) } - Device (SS05) { Name (_ADR, 13) } - Device (SS06) { Name (_ADR, 14) } +#if IS_ENABLED(CONFIG_SOC_INTEL_GLK) +#include "xhci_glk_ports.asl" +#else +#include "xhci_apl_ports.asl" +#endif } } diff --git a/src/soc/intel/apollolake/acpi/xhci_apl_ports.asl b/src/soc/intel/apollolake/acpi/xhci_apl_ports.asl new file mode 100644 index 0000000..ebb3e8c --- /dev/null +++ b/src/soc/intel/apollolake/acpi/xhci_apl_ports.asl @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC. + * Copyright 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* USB2 */ +Device (HS01) { Name (_ADR, 1) } +Device (HS02) { Name (_ADR, 2) } +Device (HS03) { Name (_ADR, 3) } +Device (HS04) { Name (_ADR, 4) } +Device (HS05) { Name (_ADR, 5) } +Device (HS06) { Name (_ADR, 6) } +Device (HS07) { Name (_ADR, 7) } +Device (HS08) { Name (_ADR, 8) } + +/* USB3 */ +Device (SS01) { Name (_ADR, 9) } +Device (SS02) { Name (_ADR, 10) } +Device (SS03) { Name (_ADR, 11) } +Device (SS04) { Name (_ADR, 12) } +Device (SS05) { Name (_ADR, 13) } +Device (SS06) { Name (_ADR, 14) } diff --git a/src/soc/intel/apollolake/acpi/xhci_glk_ports.asl b/src/soc/intel/apollolake/acpi/xhci_glk_ports.asl new file mode 100644 index 0000000..e3b045c --- /dev/null +++ b/src/soc/intel/apollolake/acpi/xhci_glk_ports.asl @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC. + * Copyright 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* USB2 */ +Device (HS01) { Name (_ADR, 1) } +Device (HS02) { Name (_ADR, 2) } +Device (HS03) { Name (_ADR, 3) } +Device (HS04) { Name (_ADR, 4) } +Device (HS05) { Name (_ADR, 5) } +Device (HS06) { Name (_ADR, 6) } +Device (HS07) { Name (_ADR, 7) } +Device (HS08) { Name (_ADR, 8) } +Device (HS09) { Name (_ADR, 9) } + +/* USB3 */ +Device (SS01) { Name (_ADR, 10) } +Device (SS02) { Name (_ADR, 11) } +Device (SS03) { Name (_ADR, 12) } +Device (SS04) { Name (_ADR, 13) } +Device (SS05) { Name (_ADR, 14) } +Device (SS06) { Name (_ADR, 15) } diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index cddfe44..de33e82 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -121,6 +121,9 @@ case 5: return "HS06"; case 6: return "HS07"; case 7: return "HS08"; + case 8: + if (IS_ENABLED(CONFIG_SOC_INTEL_GLK)) + return "HS09"; } break; case 3: -- To view, visit https://review.coreboot.org/c/coreboot/+/31172 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d3d3690ec9ea1f6e35c38c3b3cbb82e961b7950 Gerrit-Change-Number: 31172 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/amd/stoneyridge: Reboot if missing MRC cache info
by Marshall Dawson (Code Review) 04 Feb '19

04 Feb '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31160 Change subject: soc/amd/stoneyridge: Reboot if missing MRC cache info ...................................................................... soc/amd/stoneyridge: Reboot if missing MRC cache info AGESA doesn't detect invalid NV data during AmdInitResume(). In cases where the data has been erased, or cannot be found, reboot the system. Otherwise the user will experience a hang when cbmem isn't recovered and the postcar frame cannot be initialized. BUG=b:122725586 TEST=Write S3 NV save data with 0xff and force reboot Change-Id: Ib3cf2515f300decd3de198f7741660d95ee4c744 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/s3/s3_resume.c 1 file changed, 21 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/31160/1 diff --git a/src/soc/amd/common/block/s3/s3_resume.c b/src/soc/amd/common/block/s3/s3_resume.c index 04414e8..adbda64 100644 --- a/src/soc/amd/common/block/s3/s3_resume.c +++ b/src/soc/amd/common/block/s3/s3_resume.c @@ -16,7 +16,9 @@ #include <stage_cache.h> #include <mrc_cache.h> +#include <reset.h> #include <console/console.h> +#include <soc/southbridge.h> #include <amdblocks/s3_resume.h> /* Training data versioning is not supported or tracked. */ @@ -33,11 +35,25 @@ } *base = rdev_mmap_full(&rdev); *size = region_device_sz(&rdev); - if (!*base || !*size) - printk(BIOS_ERR, "Error: S3 NV data not found\n"); - else - printk(BIOS_SPEW, "S3 NV data @0x%p 0x%0zx total bytes\n", - *base, *size); + if (!*base || !*size) { + printk(BIOS_ERR, "Error: S3 NV data not found, rebooting...\n"); + set_pm1cnt_s5(); + board_reset(); + } + + int i; + uint8_t erased = 0xff; + uint8_t *s3nv = *base; + for (i = 0 ; i < *size ; i++) + erased &= *(s3nv + i); + + if (erased == 0xff) { + printk(BIOS_ERR, "Error: S3 NV data invalid, rebooting...\n"); + set_pm1cnt_s5(); + board_reset(); + } + + printk(BIOS_SPEW, "S3 NV data @0x%p, 0x%0zx bytes\n", *base, *size); } void get_s3vol_info(void **base, size_t *size) -- To view, visit https://review.coreboot.org/c/coreboot/+/31160 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3cf2515f300decd3de198f7741660d95ee4c744 Gerrit-Change-Number: 31160 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: usbdebug: Fix reserve in CAR
by Kyösti Mälkki (Code Review) 04 Feb '19

04 Feb '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31174 Change subject: usbdebug: Fix reserve in CAR ...................................................................... usbdebug: Fix reserve in CAR We need sizeof(struct ehci_dbg_info) of 88 but only reserved 64 bytes. If usbdebug_hw_init() was called late in romstage, for some builds it would corrupt CAR_GLOBALs like console_inited variable and stop logging anything. Also change pointer initialisation such that glob_dbg_info will hit garbage collection for PRE_RAM stages. Change-Id: Ib49fca781e55619179aa8888e2d859560e050876 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/car.ld M src/drivers/usb/ehci_debug.c 2 files changed, 9 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/31174/1 diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 7b10f43..3f33702 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -67,7 +67,7 @@ _car_drivers_storage_end = .; #endif _car_ehci_dbg_info_start = .; - . += 64; + . += 0x60; _car_ehci_dbg_info_end = .; /* _car_global_start and _car_global_end provide symbols to per-stage * variables that are not shared like the timestamp and the pre-ram diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index 18d0491..04272e6 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -66,13 +66,14 @@ static inline struct ehci_debug_info *dbgp_ehci_info(void) { - if (IS_ENABLED(CONFIG_USBDEBUG_IN_PRE_RAM) - && (ENV_ROMSTAGE || ENV_BOOTBLOCK || ENV_VERSTAGE)) - glob_dbg_info_p = - (struct ehci_debug_info *)_car_ehci_dbg_info_start; - if (car_get_var(glob_dbg_info_p) == NULL) - car_set_var(glob_dbg_info_p, &glob_dbg_info); - + if (car_get_var(glob_dbg_info_p) == NULL) { + struct ehci_debug_info *info; + if (ENV_BOOTBLOCK || ENV_VERSTAGE || ENV_ROMSTAGE) + info = (void *)_car_ehci_dbg_info_start; + else + info = &glob_dbg_info; + car_set_var(glob_dbg_info_p, info); + } return car_get_var(glob_dbg_info_p); } -- To view, visit https://review.coreboot.org/c/coreboot/+/31174 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib49fca781e55619179aa8888e2d859560e050876 Gerrit-Change-Number: 31174 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: ec/google/wilco: Add S0ix support handlers
by Duncan Laurie (Code Review) 04 Feb '19

04 Feb '19

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31094 Change subject: ec/google/wilco: Add S0ix support handlers ...................................................................... ec/google/wilco: Add S0ix support handlers 1) In the EC _REG method set the flag indicating S0ix support in the OS. 2) Add a function that can be called by the LPI _DSM method to indicate to the EC that the OS is entering or exiting S0ix. BUG=b:73137291 Change-Id: Iddc33a08542a6657694c47a9fda1b02dd39d89f7 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/ec/google/wilco/acpi/ec.asl M src/ec/google/wilco/acpi/ec_ram.asl 2 files changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/31094/1 diff --git a/src/ec/google/wilco/acpi/ec.asl b/src/ec/google/wilco/acpi/ec.asl index f9b16b5..db4acd4 100644 --- a/src/ec/google/wilco/acpi/ec.asl +++ b/src/ec/google/wilco/acpi/ec.asl @@ -47,6 +47,9 @@ /* Indicate to EC that OS is ready for queries */ W (ERDY, Arg1) + /* Indicate that the OS supports S0ix */ + W (CSOS, One) + /* Tell EC to stop emulating PS/2 mouse */ W (PS2M, Zero) @@ -140,6 +143,17 @@ Return (ECRW (Arg0, Arg1)) } + /* + * Tell EC that the OS is entering or exiting S0ix + Method (S0IX, 1, Serialized) + { + If (Arg0) { + W (CSEX, One) + } Else { + W (CSEX, Zero) + } + } + #include "ec_dev.asl" #include "ec_ram.asl" #include "ac.asl" diff --git a/src/ec/google/wilco/acpi/ec_ram.asl b/src/ec/google/wilco/acpi/ec_ram.asl index 1563a3c..1e5d7cb 100644 --- a/src/ec/google/wilco/acpi/ec_ram.asl +++ b/src/ec/google/wilco/acpi/ec_ram.asl @@ -142,3 +142,5 @@ Name (DWTH, Package () { 0x36, 0xff, WR }) /* DPTF: Write Trip High */ Name (DWHY, Package () { 0x37, 0xff, WR }) /* DPTF: Write Hysteresis */ Name (DWTQ, Package () { 0x38, 0xff, WR }) /* DPTF: Write Trip Query */ +Name (CSOS, Package () { 0xb8, 0xff, WR }) /* OS support for S0ix */ +Name (CSEX, Package () { 0xb9, 0xff, WR }) /* OS enter(1)/exit(0) S0ix */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31094 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iddc33a08542a6657694c47a9fda1b02dd39d89f7 Gerrit-Change-Number: 31094 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: superio/winbond/w83627ehg: Correct CR 0x2a comment
by HAOUAS Elyes (Code Review) 04 Feb '19

04 Feb '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31185 Change subject: superio/winbond/w83627ehg: Correct CR 0x2a comment ...................................................................... superio/winbond/w83627ehg: Correct CR 0x2a comment Register 0x2a [Bit 1] is a PIN89, PIN90 function select for i2c Change-Id: I9231a68ec7e9a3130a6b6975544bf89ab09cb3e6 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/superio/winbond/w83627ehg/superio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/31185/1 diff --git a/src/superio/winbond/w83627ehg/superio.c b/src/superio/winbond/w83627ehg/superio.c index 04dda6e..736d660 100644 --- a/src/superio/winbond/w83627ehg/superio.c +++ b/src/superio/winbond/w83627ehg/superio.c @@ -32,7 +32,7 @@ { u8 reg8; - /* Configure pins 91/92 as SDA/SCL (I2C bus). */ + /* Configure pins 89/90 as SDA/SCL (I2C bus). */ reg8 = pnp_read_config(dev, 0x2a); reg8 |= (1 << 1); pnp_write_config(dev, 0x2a, reg8); -- To view, visit https://review.coreboot.org/c/coreboot/+/31185 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9231a68ec7e9a3130a6b6975544bf89ab09cb3e6 Gerrit-Change-Number: 31185 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 2

Change in ...coreboot[master]: arcada: disable TP for test
by Li1 Feng (Code Review) 03 Feb '19

03 Feb '19

Li1 Feng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31184 Change subject: arcada: disable TP for test ...................................................................... arcada: disable TP for test WIP Change-Id: Ie024ba44047f3bb3714c1c5fc1e87f111c209d40 Signed-off-by: li feng <li1.feng(a)intel.com> --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/31184/1 diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index a47a53d..229e9e6 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -214,7 +214,7 @@ device i2c 0A on end end end # I2C #0 - device pci 15.1 on + device pci 15.1 off chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" -- To view, visit https://review.coreboot.org/c/coreboot/+/31184 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie024ba44047f3bb3714c1c5fc1e87f111c209d40 Gerrit-Change-Number: 31184 Gerrit-PatchSet: 1 Gerrit-Owner: Li1 Feng <li1.feng(a)intel.com> Gerrit-MessageType: newchange

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