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Change in ...coreboot[master]: usbdebug: Use fixed size field
by Kyösti Mälkki (Code Review) 03 Feb '19

03 Feb '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31182 Change subject: usbdebug: Use fixed size field ...................................................................... usbdebug: Use fixed size field The structure is placed inside CBMEM, one should use types with fixed size. Change-Id: I60382664a53650b225abc1f77c87ed4e121d429e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/usb/ehci_debug.c 1 file changed, 17 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/31182/1 diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index cf3976c..3532466 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -28,8 +28,8 @@ #include "ehci.h" struct ehci_debug_info { - void *ehci_base; - void *ehci_debug; + u64 ehci_base; + u64 ehci_debug; struct dbgp_pipe ep_pipe[DBGP_MAX_ENDPOINTS]; }; @@ -262,7 +262,9 @@ int dbgp_bulk_write_x(struct dbgp_pipe *pipe, const char *bytes, int size) { struct ehci_debug_info *dbg_info = dbgp_ehci_info(); - return dbgp_bulk_write(dbg_info->ehci_debug, pipe, bytes, size); + struct ehci_dbg_port *port; + port = (void *)(uintptr_t)dbg_info->ehci_debug; + return dbgp_bulk_write(port, pipe, bytes, size); } static int dbgp_bulk_read(struct ehci_dbg_port *ehci_debug, struct dbgp_pipe *pipe, @@ -296,7 +298,9 @@ int dbgp_bulk_read_x(struct dbgp_pipe *pipe, void *data, int size) { struct ehci_debug_info *dbg_info = dbgp_ehci_info(); - return dbgp_bulk_read(dbg_info->ehci_debug, pipe, data, size); + struct ehci_dbg_port *port; + port = (void *)(uintptr_t)dbg_info->ehci_debug; + return dbgp_bulk_read(port, pipe, data, size); } void dbgp_mdelay(int ms) @@ -446,8 +450,8 @@ /* Keep all endpoints disabled before any printk() call. */ memset(info, 0, sizeof (*info)); - info->ehci_base = (void *)ehci_bar; - info->ehci_debug = (void *)(ehci_bar + offset); + info->ehci_base = ehci_bar; + info->ehci_debug = ehci_bar + offset; info->ep_pipe[0].status |= DBGP_EP_NOT_PRESENT; dprintk(BIOS_INFO, "ehci_bar: 0x%x debug_offset 0x%x\n", ehci_bar, offset); @@ -456,7 +460,7 @@ ehci_regs = (struct ehci_regs *)(ehci_bar + HC_LENGTH(read32(&ehci_caps->hc_capbase))); - struct ehci_dbg_port *ehci_debug = info->ehci_debug; + struct ehci_dbg_port *ehci_debug = (void *)(uintptr_t)info->ehci_debug; if (CONFIG_USBDEBUG_DEFAULT_PORT > 0) ehci_debug_select_port(CONFIG_USBDEBUG_DEFAULT_PORT); @@ -581,7 +585,8 @@ dbgp_mdelay(100); - ret = dbgp_probe_gadget(info->ehci_debug, &info->ep_pipe[0]); + struct ehci_dbg_port *port = (void *)(uintptr_t)info->ehci_debug; + ret = dbgp_probe_gadget(port, &info->ep_pipe[0]); if (ret < 0) { dprintk(BIOS_INFO, "Could not probe gadget on debug port.\n"); ret = -6; @@ -653,12 +658,12 @@ void usbdebug_re_enable(unsigned ehci_base) { struct ehci_debug_info *dbg_info = dbgp_ehci_info(); - unsigned diff; + u64 diff; int i; - diff = (unsigned)dbg_info->ehci_base - ehci_base; + diff = dbg_info->ehci_base - ehci_base; dbg_info->ehci_debug -= diff; - dbg_info->ehci_base = (void *)ehci_base; + dbg_info->ehci_base = ehci_base; for (i=0; i<DBGP_MAX_ENDPOINTS; i++) if (dbg_info->ep_pipe[i].status & DBGP_EP_VALID) @@ -678,7 +683,7 @@ int usbdebug_hw_init(bool force) { struct ehci_debug_info *dbg_info = dbgp_ehci_info(); - unsigned int ehci_base, dbg_offset; + u32 ehci_base, dbg_offset; if (dbgp_enabled() && !force) return 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/31182 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60382664a53650b225abc1f77c87ed4e121d429e Gerrit-Change-Number: 31182 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

2 4

Change in ...coreboot[master]: WIP: mb/qemu-riscv: update to match current qemu version
by Philipp Hug (Code Review) 02 Feb '19

02 Feb '19

Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30554 Change subject: WIP: mb/qemu-riscv: update to match current qemu version ...................................................................... WIP: mb/qemu-riscv: update to match current qemu version Boots again to payload not found on qemu. Change-Id: Ie107eb882cbaac5a5a06c1ff990e7b9364377640 Signed-off-by: Philipp Hug <philipp(a)hug.cx> --- M src/mainboard/emulation/qemu-riscv/Kconfig M src/mainboard/emulation/qemu-riscv/Makefile.inc M src/mainboard/emulation/qemu-riscv/mainboard.c M src/mainboard/emulation/qemu-riscv/memlayout.ld D src/mainboard/emulation/qemu-riscv/mtime.c M src/mainboard/emulation/qemu-riscv/rom_media.c M src/mainboard/emulation/qemu-riscv/uart.c 7 files changed, 23 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/30554/1 diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig b/src/mainboard/emulation/qemu-riscv/Kconfig index 528b21e..ecaa764 100644 --- a/src/mainboard/emulation/qemu-riscv/Kconfig +++ b/src/mainboard/emulation/qemu-riscv/Kconfig @@ -13,7 +13,8 @@ ## GNU General Public License for more details. # To execute, do: -# qemu-system-arm -M vexpress-a9 -m 1024M -nographic -kernel build/coreboot.rom +# util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf +# qemu-system-riscv64 -M virt -m 1024M -nographic -kernel build/coreboot.elf if BOARD_EMULATION_QEMU_RISCV diff --git a/src/mainboard/emulation/qemu-riscv/Makefile.inc b/src/mainboard/emulation/qemu-riscv/Makefile.inc index 1d882ac..eb99544 100644 --- a/src/mainboard/emulation/qemu-riscv/Makefile.inc +++ b/src/mainboard/emulation/qemu-riscv/Makefile.inc @@ -14,7 +14,7 @@ bootblock-y += uart.c bootblock-y += rom_media.c -bootblock-y += mtime.c +bootblock-y += clint.c romstage-y += romstage.c romstage-y += uart.c @@ -22,8 +22,10 @@ ramstage-y += uart.c ramstage-y += rom_media.c -ramstage-y += mtime.c +ramstage-y += clint.c bootblock-y += memlayout.ld romstage-y += memlayout.ld ramstage-y += memlayout.ld + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include diff --git a/src/mainboard/emulation/qemu-riscv/mainboard.c b/src/mainboard/emulation/qemu-riscv/mainboard.c index 7061bcf..4b428aa 100644 --- a/src/mainboard/emulation/qemu-riscv/mainboard.c +++ b/src/mainboard/emulation/qemu-riscv/mainboard.c @@ -16,6 +16,7 @@ #include <console/console.h> #include <device/device.h> #include <cbmem.h> +#include <symbols.h> static void mainboard_enable(struct device *dev) { @@ -24,7 +25,7 @@ die("No dev0; die\n"); } - ram_resource(dev, 0, 2048, 32768); + ram_resource(dev, 0, (uintptr_t)_dram / KiB, CONFIG_DRAM_SIZE_MB * KiB); cbmem_recovery(0); } diff --git a/src/mainboard/emulation/qemu-riscv/memlayout.ld b/src/mainboard/emulation/qemu-riscv/memlayout.ld index 615d1f2..032fbdd 100644 --- a/src/mainboard/emulation/qemu-riscv/memlayout.ld +++ b/src/mainboard/emulation/qemu-riscv/memlayout.ld @@ -14,15 +14,16 @@ */ #include <memlayout.h> - #include <arch/header.ld> +#define START 0x80000000 + SECTIONS { - DRAM_START(0x0) - BOOTBLOCK(0x0, 64K) - ROMSTAGE(0x20000, 128K) - STACK(0x40000, 0x3ff00) - PRERAM_CBMEM_CONSOLE(0x80000, 8K) - RAMSTAGE(0x100000, 16M) + DRAM_START(START) + BOOTBLOCK(START, 64K) + STACK(START + 4M, 4K) + ROMSTAGE(START + 4M + 64K, 128K) + PRERAM_CBMEM_CONSOLE(START + 4M + 192K, 8K) + RAMSTAGE(START + 4M + 200K, 16M) } diff --git a/src/mainboard/emulation/qemu-riscv/mtime.c b/src/mainboard/emulation/qemu-riscv/mtime.c deleted file mode 100644 index f8c2717..0000000 --- a/src/mainboard/emulation/qemu-riscv/mtime.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 HardenedLinux - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <mcall.h> - -/* FIXME: This is an empty implementation, please improve */ -/* This function is used to initialize HLS()->time/HLS()->timecmp */ -void mtime_init(void) -{ -} diff --git a/src/mainboard/emulation/qemu-riscv/rom_media.c b/src/mainboard/emulation/qemu-riscv/rom_media.c index c171307..bac1984 100644 --- a/src/mainboard/emulation/qemu-riscv/rom_media.c +++ b/src/mainboard/emulation/qemu-riscv/rom_media.c @@ -14,11 +14,12 @@ * GNU General Public License for more details. */ #include <boot_device.h> +#include <symbols.h> -/* This assumes that the CBFS resides at 0x0, which is true for the default - * configuration. */ +/* This assumes that the CBFS resides at start of dram, which is true for the + * default configuration. */ static const struct mem_region_device boot_dev = - MEM_REGION_DEV_RO_INIT(NULL, CONFIG_ROM_SIZE); + MEM_REGION_DEV_RO_INIT(_dram, CONFIG_ROM_SIZE); const struct region_device *boot_device_ro(void) { diff --git a/src/mainboard/emulation/qemu-riscv/uart.c b/src/mainboard/emulation/qemu-riscv/uart.c index 730ef3e..084362a 100644 --- a/src/mainboard/emulation/qemu-riscv/uart.c +++ b/src/mainboard/emulation/qemu-riscv/uart.c @@ -17,8 +17,9 @@ #include <console/uart.h> #include <arch/io.h> #include <boot/coreboot_tables.h> +#include <mainboard/addressmap.h> -static uint8_t *buf = (void *)0x3f8; +static uint8_t *buf = (void *)QEMU_VIRT_UART0; uintptr_t uart_platform_base(int idx) { return (uintptr_t) buf; @@ -47,7 +48,7 @@ { struct lb_serial serial; serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial.baseaddr = 0x3f8; + serial.baseaddr = QEMU_VIRT_UART0; serial.baud = 115200; serial.regwidth = 1; lb_add_serial(&serial, data); -- To view, visit https://review.coreboot.org/c/coreboot/+/30554 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie107eb882cbaac5a5a06c1ff990e7b9364377640 Gerrit-Change-Number: 30554 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-MessageType: newchange

4 5

Change in ...coreboot[master]: riscv: Simplify payload handling
by Philipp Hug (Code Review) 02 Feb '19

02 Feb '19

Hello Xiang Wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31179 to review the following change. Change subject: riscv: Simplify payload handling ...................................................................... riscv: Simplify payload handling 1. Simplify payload code and convert it to C 2. Save the FDT pointer to HLS (hart-local storage). 3. Don't use mscratch to pass FDT pointer as it is used for exception handling. Change-Id: I32bf2a99e07a65358a7f19b899259f0816eb45e8 Signed-off-by: Xiang Wang <wxjstz(a)126.com> Signed-off-by: Philipp Hug <philipp(a)hug.cx> --- M src/arch/riscv/Makefile.inc M src/arch/riscv/boot.c M src/arch/riscv/bootblock.S M src/arch/riscv/include/arch/boot.h M src/arch/riscv/include/arch/stages.h M src/arch/riscv/include/mcall.h M src/arch/riscv/mcall.c D src/arch/riscv/payload.S A src/arch/riscv/payload.c M src/arch/riscv/stages.c 10 files changed, 87 insertions(+), 57 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/31179/1 diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index e4c8468..9d91f0c 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -137,7 +137,7 @@ ramstage-y += smp.c ramstage-y += boot.c ramstage-y += tables.c -ramstage-y += payload.S +ramstage-y += payload.c ramstage-$(ARCH_RISCV_PMP) += pmp.c ramstage-y += \ $(top)/src/lib/memchr.c \ diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c index 3d8d5d6..dab4e09 100644 --- a/src/arch/riscv/boot.c +++ b/src/arch/riscv/boot.c @@ -19,6 +19,7 @@ #include <arch/encoding.h> #include <console/console.h> #include <arch/smp/smp.h> +#include <mcall.h> /* * A pointer to the Flattened Device Tree passed to coreboot by the boot ROM. @@ -26,27 +27,27 @@ * * This pointer is only used in ramstage! */ -const void *rom_fdt; static void do_arch_prog_run(struct prog *prog) { - void (*doit)(void *) = prog_entry(prog); - void riscvpayload(const void *fdt, void *payload); + void (*doit)(int hart_id, void *fdt); + int hart_id; + void *fdt = prog_entry_arg(prog); if (ENV_RAMSTAGE && prog_type(prog) == PROG_PAYLOAD) { /* - * FIXME: This is wrong and will crash. Linux can't (in early - * boot) access memory that's before its own loading address. - * We need to copy the FDT to a place where Linux can access it. + * If prog_entry_arg is not set (e.g. by fit_payload), use fdt from HLS instead. */ - const void *fdt = rom_fdt; - - printk(BIOS_SPEW, "FDT is at %p\n", fdt); - printk(BIOS_SPEW, "OK, let's go\n"); - riscvpayload(fdt, doit); + if (fdt == NULL) + fdt = HLS()->fdt; + run_payload(prog, fdt, RISCV_PAYLOAD_MODE_S); + return; } - doit(prog_entry_arg(prog)); + doit = prog_entry(prog); + hart_id = HLS()->hart_id; + + doit(hart_id, fdt); } void arch_prog_run(struct prog *prog) diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S index 7f84215..d4b8be7 100644 --- a/src/arch/riscv/bootblock.S +++ b/src/arch/riscv/bootblock.S @@ -50,6 +50,7 @@ # initialize hart-local storage csrr a0, mhartid + csrrw a1, mscratch, zero call hls_init li a0, CONFIG_RISCV_WORKING_HARTID diff --git a/src/arch/riscv/include/arch/boot.h b/src/arch/riscv/include/arch/boot.h index 24c1bed..34a507e 100644 --- a/src/arch/riscv/include/arch/boot.h +++ b/src/arch/riscv/include/arch/boot.h @@ -16,6 +16,12 @@ #ifndef ARCH_RISCV_INCLUDE_ARCH_BOOT_H #define ARCH_RISCV_INCLUDE_ARCH_BOOT_H -extern const void *rom_fdt; +#include <program_loading.h> + +#define RISCV_PAYLOAD_MODE_U 0 +#define RISCV_PAYLOAD_MODE_S 1 +#define RISCV_PAYLOAD_MODE_M 3 + +void run_payload(struct prog *prog, void *fdt, int payload_mode); #endif diff --git a/src/arch/riscv/include/arch/stages.h b/src/arch/riscv/include/arch/stages.h index 90bd60b..138298f 100644 --- a/src/arch/riscv/include/arch/stages.h +++ b/src/arch/riscv/include/arch/stages.h @@ -18,6 +18,7 @@ #include <main_decl.h> -void stage_entry(void) __attribute__((section(".text.stage_entry"))); +void stage_entry(int hart_id, void *fdt) + __attribute__((section(".text.stage_entry"))); #endif diff --git a/src/arch/riscv/include/mcall.h b/src/arch/riscv/include/mcall.h index 29df736..cd1ed6d 100644 --- a/src/arch/riscv/include/mcall.h +++ b/src/arch/riscv/include/mcall.h @@ -52,9 +52,14 @@ int ipi_pending; uint64_t *timecmp; uint64_t *time; + void *fdt; struct blocker entry; } hls_t; +_Static_assert( + sizeof(hls_t) == HLS_SIZE, + "HLS_SIZE must equal to sizeof(hls_t)"); + #define MACHINE_STACK_TOP() ({ \ /* coverity[uninit_use] : FALSE */ \ register uintptr_t sp asm ("sp"); \ @@ -66,7 +71,8 @@ #define MACHINE_STACK_SIZE RISCV_PGSIZE -void hls_init(uint32_t hart_id); // need to call this before launching linux +// need to call this before launching linux +void hls_init(uint32_t hart_id, void *fdt); /* This function is used to initialize HLS()->time/HLS()->timecmp */ void mtime_init(void); diff --git a/src/arch/riscv/mcall.c b/src/arch/riscv/mcall.c index 47cdd88..eaef644 100644 --- a/src/arch/riscv/mcall.c +++ b/src/arch/riscv/mcall.c @@ -34,10 +34,11 @@ int mcalldebug; // set this interactively for copious debug. -void hls_init(uint32_t hart_id) +void hls_init(uint32_t hart_id, void *fdt) { printk(BIOS_SPEW, "hart %d: HLS is %p\n", hart_id, HLS()); memset(HLS(), 0, sizeof(*HLS())); + HLS()->fdt = fdt; HLS()->hart_id = hart_id; mtime_init(); diff --git a/src/arch/riscv/payload.S b/src/arch/riscv/payload.S deleted file mode 100644 index 1b8cb96..0000000 --- a/src/arch/riscv/payload.S +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Google Inc - * Copyright (C) 2018 Jonathan Neuschäfer - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// "return" to a payload. a0: FDT, a1: entry point - .global riscvpayload -riscvpayload: - /* Load the entry point */ - mv t0, a1 - csrw mepc, t0 - csrr t0, mstatus - - /* Set mstatus.MPP (the previous privilege mode) to supervisor mode */ - li t1, ~(3<<11) - and t0, t0, t1 - li t2, (1<<11) - or t0, t0, t2 - csrw mstatus, t0 - - /* Pass the right arguments and jump! */ - mv a1, a0 - csrr a0, mhartid - mret diff --git a/src/arch/riscv/payload.c b/src/arch/riscv/payload.c new file mode 100644 index 0000000..af2542f --- /dev/null +++ b/src/arch/riscv/payload.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc + * Copyright (C) 2018 HardenedLinux + * Copyright (C) 2018 Jonathan Neuschäfer + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <arch/boot.h> +#include <arch/encoding.h> +#include <console/console.h> + +void run_payload(struct prog *prog, void *fdt, int payload_mode) +{ + void (*doit)(int hart_id, void *fdt) = prog_entry(prog); + int hart_id = read_csr(mhartid); + uintptr_t status = read_csr(mstatus); + status &= ~MSTATUS_MPIE; + status &= ~MSTATUS_MPP; + switch (payload_mode) { + case RISCV_PAYLOAD_MODE_U: + break; + case RISCV_PAYLOAD_MODE_S: + status |= MSTATUS_SPP; + break; + case RISCV_PAYLOAD_MODE_M: + doit(hart_id, fdt); + return; + default: + die("wrong privilege level for payload"); + break; + } + write_csr(mstatus, status); + write_csr(mepc, doit); + asm volatile("mv a0, %0"::"r"(hart_id):"a0"); + asm volatile("mv a1, %0"::"r"(fdt):"a1"); + asm volatile("mret"); +} diff --git a/src/arch/riscv/stages.c b/src/arch/riscv/stages.c index 5e7fa4f..07b898f 100644 --- a/src/arch/riscv/stages.c +++ b/src/arch/riscv/stages.c @@ -28,18 +28,19 @@ #include <arch/encoding.h> #include <arch/stages.h> #include <arch/smp/smp.h> +#include <rules.h> +#include <mcall.h> -void stage_entry(void) +void stage_entry(int hart_id, void *fdt) { - smp_pause(CONFIG_RISCV_WORKING_HARTID); - /* * Save the FDT pointer before entering ramstage, because mscratch * might be overwritten in the trap handler, and there is code in * ramstage that generates misaligned access faults. */ - if (ENV_RAMSTAGE) - rom_fdt = (const void *)read_csr(mscratch); + HLS()->hart_id = hart_id; + HLS()->fdt = fdt; + smp_pause(CONFIG_RISCV_WORKING_HARTID); main(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/31179 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32bf2a99e07a65358a7f19b899259f0816eb45e8 Gerrit-Change-Number: 31179 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: vendorcode/google/chromeos: Add option for using ACPI GPIO pin
by Duncan Laurie (Code Review) 01 Feb '19

01 Feb '19

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31080 Change subject: vendorcode/google/chromeos: Add option for using ACPI GPIO pin ...................................................................... vendorcode/google/chromeos: Add option for using ACPI GPIO pin This new option will have the generated Chrome OS ACPI GPIO table provide the ACPI GPIO pin number instead of the raw GPIO number. This is necessary if the OS uses a different numbering for GPIOs that are reported in ACPI than the actual underlying GPIO number. For example, if the SOC OS driver declares more pins in an ACPI GPIO bank than there are actual pins in the hardware it will have gaps in the number space. This is a reworked version of 6217e9beff16d805ca833e79a2931bcdb3d02a44 which uses a new option instead of just relying on GENERIC_GPIO_LIB. BUG=b:120686247 TEST=pass firmware_WriteProtect test on Sarien Change-Id: I3ad5099b7f2f871c7e516988f60a54eb2a75bef7 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/vendorcode/google/chromeos/Kconfig M src/vendorcode/google/chromeos/acpi.c 2 files changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/31080/1 diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index 26ee31e..2edb46f 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -89,5 +89,17 @@ on normal boot as well as resume and coreboot is only involved in the resume piece w.r.t. the platform hierarchy. +config CHROMEOS_ACPI_GPIO_GENERATE_PIN + bool + default n + depends on HAVE_ACPI_TABLES && GENERIC_GPIO_LIB + help + This option will have the generated Chrome OS ACPI GPIO table + provide the ACPI GPIO pin number instead of the raw GPIO number. + This is necessary if the OS uses a different numbering for GPIOs + that are reported in ACPI. For example, if the SOC declares more + pins in an ACPI GPIO bank than there are actual pins in the hardware + it will have gaps in the number space. + endif # CHROMEOS endmenu diff --git a/src/vendorcode/google/chromeos/acpi.c b/src/vendorcode/google/chromeos/acpi.c index 6605809..849f4c3 100644 --- a/src/vendorcode/google/chromeos/acpi.c +++ b/src/vendorcode/google/chromeos/acpi.c @@ -15,6 +15,9 @@ #include <arch/acpigen.h> #include "chromeos.h" +#if IS_ENABLED(CONFIG_CHROMEOS_ACPI_GPIO_GENERATE_PIN) +#include <gpio.h> +#endif void chromeos_acpi_gpio_generate(const struct cros_gpio *gpios, size_t num) { @@ -28,7 +31,11 @@ acpigen_write_package(4); acpigen_write_integer(gpios[i].type); acpigen_write_integer(gpios[i].polarity); +#if IS_ENABLED(CONFIG_CHROMEOS_ACPI_GPIO_GENERATE_PIN) + acpigen_write_integer(gpio_acpi_pin(gpios[i].gpio_num)); +#else acpigen_write_integer(gpios[i].gpio_num); +#endif acpigen_write_string(gpios[i].device); acpigen_pop_len(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/31080 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ad5099b7f2f871c7e516988f60a54eb2a75bef7 Gerrit-Change-Number: 31080 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/intel/common: Rename i2c_block_read() to i2c_eeprom_read()
by Kyösti Mälkki (Code Review) 01 Feb '19

01 Feb '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31151 Change subject: sb/intel/common: Rename i2c_block_read() to i2c_eeprom_read() ...................................................................... sb/intel/common: Rename i2c_block_read() to i2c_eeprom_read() Datasheets describe the used command as 'I2C Read' but adding the word 'eeprom' in between should avoid further confusion with other block commands. Followups will add a symmetrical pair of commands i2c_block_read() and i2c_block_write() that operate via I2C_EN bit and have a 32 byte size restriction on block transfers. For some hardware revision these block commands are available, while 'I2C Read' was not. Change-Id: I4494ab2985afc7f737ddacc8d706a5d5395e35cf Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/northbridge/intel/i945/raminit.c M src/northbridge/intel/pineview/raminit.c M src/northbridge/intel/x4x/raminit.c M src/southbridge/intel/common/smbus.c M src/southbridge/intel/common/smbus.h M src/southbridge/intel/i82801gx/early_smbus.c M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/i82801jx/early_smbus.c M src/southbridge/intel/i82801jx/i82801jx.h 9 files changed, 25 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/31151/1 diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index f3c3df6..dece9bf 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -381,7 +381,7 @@ * only the first 64 bytes contain data needed for raminit. */ - bytes_read = i2c_block_read(device, 0, 64, raw_spd); + bytes_read = i2c_eeprom_read(device, 0, 64, raw_spd); printk(BIOS_DEBUG, "Reading SPD using i2c block operation.\n"); if (IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) && bytes_read > 0) hexdump(raw_spd, bytes_read); diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index ee19b61..ed633fd 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -273,7 +273,7 @@ u8 i, chan; s->dt0mode = 0; FOR_EACH_DIMM(i) { - if (i2c_block_read(s->spd_map[i], 0, 64, s->dimms[i].spd_data) != 64) + if (i2c_eeprom_read(s->spd_map[i], 0, 64, s->dimms[i].spd_data) != 64) s->dimms[i].card_type = 0; s->dimms[i].card_type = s->dimms[i].spd_data[62] & 0x1f; diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index d9fa49d..1fd6004 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -47,15 +47,15 @@ static u16 ddr2_get_crc(u8 device, u8 len) { u8 raw_spd[128] = {}; - i2c_block_read(device, 64, 9, &raw_spd[64]); - i2c_block_read(device, 93, 6, &raw_spd[93]); + i2c_eeprom_read(device, 64, 9, &raw_spd[64]); + i2c_eeprom_read(device, 93, 6, &raw_spd[93]); return spd_ddr2_calc_unique_crc(raw_spd, len); } static u16 ddr3_get_crc(u8 device, u8 len) { u8 raw_spd[256] = {}; - i2c_block_read(device, 117, 11, &raw_spd[117]); + i2c_eeprom_read(device, 117, 11, &raw_spd[117]); return spd_ddr3_calc_unique_crc(raw_spd, len); } @@ -531,7 +531,7 @@ die("Mixing up dimm types is not supported!\n"); printk(BIOS_DEBUG, "Decoding dimm %d\n", i); - if (i2c_block_read(device, 0, 128, raw_spd) != 128) { + if (i2c_eeprom_read(device, 0, 128, raw_spd) != 128) { printk(BIOS_DEBUG, "i2c block operation failed," " trying smbus byte operation.\n"); for (j = 0; j < 128; j++) diff --git a/src/southbridge/intel/common/smbus.c b/src/southbridge/intel/common/smbus.c index fd8b6aa..a842a61 100644 --- a/src/southbridge/intel/common/smbus.c +++ b/src/southbridge/intel/common/smbus.c @@ -363,11 +363,22 @@ } /* Only since ICH5 */ -int do_i2c_block_read(unsigned int smbus_base, u8 device, +static int has_i2c_read_command(void) +{ + if (IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82371EB) || + IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801DX)) + return 0; + return 1; +} + +int do_i2c_eeprom_read(unsigned int smbus_base, u8 device, unsigned int offset, const unsigned int bytes, u8 *buf) { int ret; + if (!has_i2c_read_command()) + return SMBUS_ERROR; + /* Set up for a i2c block data read. * * FIXME: Address parameter changes to XMIT_READ(device) with diff --git a/src/southbridge/intel/common/smbus.h b/src/southbridge/intel/common/smbus.h index be1aa76..ded31d0 100644 --- a/src/southbridge/intel/common/smbus.h +++ b/src/southbridge/intel/common/smbus.h @@ -41,6 +41,6 @@ int do_smbus_block_write(unsigned int smbus_base, u8 device, u8 cmd, unsigned int bytes, const u8 *buf); /* Only since ICH5 */ -int do_i2c_block_read(unsigned int smbus_base, u8 device, +int do_i2c_eeprom_read(unsigned int smbus_base, u8 device, unsigned int offset, unsigned int bytes, u8 *buf); #endif diff --git a/src/southbridge/intel/i82801gx/early_smbus.c b/src/southbridge/intel/i82801gx/early_smbus.c index 698458b..9dddcec 100644 --- a/src/southbridge/intel/i82801gx/early_smbus.c +++ b/src/southbridge/intel/i82801gx/early_smbus.c @@ -54,9 +54,9 @@ return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -int i2c_block_read(unsigned int device, unsigned int offset, u32 bytes, u8 *buf) +int i2c_eeprom_read(unsigned int device, unsigned int offset, u32 bytes, u8 *buf) { - return do_i2c_block_read(SMBUS_IO_BASE, device, offset, bytes, buf); + return do_i2c_eeprom_read(SMBUS_IO_BASE, device, offset, bytes, buf); } int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf) diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 66d47ae..12935c2 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -45,7 +45,7 @@ #else void enable_smbus(void); int smbus_read_byte(unsigned int device, unsigned int address); -int i2c_block_read(unsigned int device, unsigned int cmd, unsigned int bytes, +int i2c_eeprom_read(unsigned int device, unsigned int cmd, unsigned int bytes, u8 *buf); int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf); int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, diff --git a/src/southbridge/intel/i82801jx/early_smbus.c b/src/southbridge/intel/i82801jx/early_smbus.c index bd68955..8c87045 100644 --- a/src/southbridge/intel/i82801jx/early_smbus.c +++ b/src/southbridge/intel/i82801jx/early_smbus.c @@ -51,9 +51,9 @@ return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -int i2c_block_read(unsigned int device, unsigned int offset, u32 bytes, u8 *buf) +int i2c_eeprom_read(unsigned int device, unsigned int offset, u32 bytes, u8 *buf) { - return do_i2c_block_read(SMBUS_IO_BASE, device, offset, bytes, buf); + return do_i2c_eeprom_read(SMBUS_IO_BASE, device, offset, bytes, buf); } int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf) diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h index ad3b381..0014848 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.h +++ b/src/southbridge/intel/i82801jx/i82801jx.h @@ -233,7 +233,7 @@ #if defined(__PRE_RAM__) void enable_smbus(void); int smbus_read_byte(unsigned device, unsigned address); -int i2c_block_read(unsigned int device, unsigned int cmd, unsigned int bytes, +int i2c_eeprom_read(unsigned int device, unsigned int cmd, unsigned int bytes, u8 *buf); int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf); int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, -- To view, visit https://review.coreboot.org/c/coreboot/+/31151 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4494ab2985afc7f737ddacc8d706a5d5395e35cf Gerrit-Change-Number: 31151 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

5 5

Change in ...coreboot[master]: arch/x86: Remove weak tsc_freq_mhz() implementation
by Kyösti Mälkki (Code Review) 01 Feb '19

01 Feb '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30762 Change subject: arch/x86: Remove weak tsc_freq_mhz() implementation ...................................................................... arch/x86: Remove weak tsc_freq_mhz() implementation Build with TSC_CONSTANT_RATE must fail when this function is not implemented for the platform. Weak implementation causes division by zero in timer_monotonic_get() and turns udelay() into no delay. Change-Id: Id3b105ea3aac37cd0cba18ce2fb06d87a055486f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/timestamp.c 1 file changed, 3 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/30762/1 diff --git a/src/arch/x86/timestamp.c b/src/arch/x86/timestamp.c index 928d7d7..cbc7bac 100644 --- a/src/arch/x86/timestamp.c +++ b/src/arch/x86/timestamp.c @@ -21,15 +21,10 @@ return rdtscll(); } -unsigned long __weak tsc_freq_mhz(void) -{ - /* Default to not knowing TSC frequency. cbmem will have to fallback - * on trying to determine it in userspace. */ - return 0; -} - int timestamp_tick_freq_mhz(void) { /* Chipsets that have a constant TSC provide this value correctly. */ - return tsc_freq_mhz(); + if (IS_ENABLED(CONFIG_TSC_CONSTANT_RATE)) + return tsc_freq_mhz(); + return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/30762 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3b105ea3aac37cd0cba18ce2fb06d87a055486f Gerrit-Change-Number: 30762 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: hatch: Enable S0ix
by Shelley Chen (Code Review) 01 Feb '19

01 Feb '19

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31157 Change subject: hatch: Enable S0ix ...................................................................... hatch: Enable S0ix BUG=b:123540469 BRANCH=None TEST=None Change-Id: I713e6ad70efdd152895afa45aee44a5b53a8136b Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/31157/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index cea64e4..2bc4f78 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -55,6 +55,8 @@ register "HeciEnabled" = "1" # Enable Speed Shift Technology support register "speed_shift_enable" = "1" + # Enable S0ix + register "s0ix_enable" = "1" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 0 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/31157 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I713e6ad70efdd152895afa45aee44a5b53a8136b Gerrit-Change-Number: 31157 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/amd/stoneyridge: Add generic PM1 register clear function
by Marshall Dawson (Code Review) 01 Feb '19

01 Feb '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31159 Change subject: soc/amd/stoneyridge: Add generic PM1 register clear function ...................................................................... soc/amd/stoneyridge: Add generic PM1 register clear function Convert vboot_platform_prepare_reboot() to call a function in soc//stoneyridge. A subsequent patch will add another call to the new function, and this change removes any inference of a dependency on vboot. BUG=b:122725586 Change-Id: I634fcd030e206c790bda697a3dbef4e8cc21b3a8 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/pmutil.c 2 files changed, 14 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/31159/1 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 1652bbc..3ae6b4a 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -604,4 +604,10 @@ /* Initialize all the i2c buses that are not marked with early init. */ void i2c_soc_init(void); +/* + * If a system reset is about to be requested, modify the PM1 register so it + * will never be misinterpreted as an S3 resume. + */ +void set_pm1cnt_s5(void); + #endif /* __STONEYRIDGE_H__ */ diff --git a/src/soc/amd/stoneyridge/pmutil.c b/src/soc/amd/stoneyridge/pmutil.c index d2b3ac7..bfb5f42 100644 --- a/src/soc/amd/stoneyridge/pmutil.c +++ b/src/soc/amd/stoneyridge/pmutil.c @@ -34,9 +34,9 @@ return acpi_sleep_from_pm1(pm_cnt) == ACPI_S3; } -/* If vboot requests a system reset, modify the PM1 register so it will never be - * misinterpreted as an S3 resume. */ -void vboot_platform_prepare_reboot(void) +/* If a system reset is about to be requested, modify the PM1 register so it + * will never be misinterpreted as an S3 resume. */ +void set_pm1cnt_s5(void) { uint16_t pm1; @@ -45,3 +45,8 @@ pm1 |= SLP_TYP_S5 << SLP_TYP_SHIFT; acpi_write16(MMIO_ACPI_PM1_CNT_BLK, pm1); } + +void vboot_platform_prepare_reboot(void) +{ + set_pm1cnt_s5(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/31159 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I634fcd030e206c790bda697a3dbef4e8cc21b3a8 Gerrit-Change-Number: 31159 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: cbmem: use aligned_memcpy for reading cbmem address information
by Aaron Durbin (Code Review) 01 Feb '19

01 Feb '19

Aaron Durbin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31181 Change subject: cbmem: use aligned_memcpy for reading cbmem address information ...................................................................... cbmem: use aligned_memcpy for reading cbmem address information The coreboot table entry containing the memory entries can have fields unnaturally aligned in memory. Therefore one needs to perform an aligned_memcpy() so that it doesn't cause faults on certain architectures that assume naturally aligned accesses. chromium:925961 Change-Id: I28365b204962ac89d65d046076d862b6f9374c06 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- M util/cbmem/cbmem.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/31181/1 diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index 8e73d9c..fc2dcdc 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -302,7 +302,7 @@ continue; debug(" LB_MEM_TABLE found.\n"); /* The last one found is CBMEM */ - cbmem = mem->map[i]; + aligned_memcpy(&cbmem, &mem->map[i], sizeof(cbmem)); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/31181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28365b204962ac89d65d046076d862b6f9374c06 Gerrit-Change-Number: 31181 Gerrit-PatchSet: 1 Gerrit-Owner: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

4 5

Change in ...coreboot[master]: soc/intel/icelake: Make correct C-state entries for S0ix and non-S0ix
by Subrata Banik (Code Review) 01 Feb '19

01 Feb '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31153 Change subject: soc/intel/icelake: Make correct C-state entries for S0ix and non-S0ix ...................................................................... soc/intel/icelake: Make correct C-state entries for S0ix and non-S0ix TEST=Dump SSDT entries to verify _CST between S0ix enable and disable. Change-Id: I82d8bf9d143263a80a544f6e11186a3bc9c41052 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/icelake/acpi.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/31153/1 diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index 39ec58a..0e13d034 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -119,13 +119,13 @@ }, }; -static int cstate_set_s0ix[] = { +static int cstate_set_non_s0ix[] = { C_STATE_C1E, C_STATE_C6_LONG_LAT, C_STATE_C7S_LONG_LAT }; -static int cstate_set_non_s0ix[] = { +static int cstate_set_s0ix[] = { C_STATE_C1E, C_STATE_C7S_LONG_LAT, C_STATE_C10 -- To view, visit https://review.coreboot.org/c/coreboot/+/31153 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82d8bf9d143263a80a544f6e11186a3bc9c41052 Gerrit-Change-Number: 31153 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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