coreboot-gerrit January 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: WIP: enable ISH in arcada
by Li1 Feng (Code Review) 31 Jan '19

31 Jan '19

Li1 Feng has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29518 ) Change subject: WIP: enable ISH in arcada ...................................................................... Abandoned This is only apply to EV. for EVT, new patch is merged. https://review.coreboot.org/#/c/coreboot/+/30070/ -- To view, visit https://review.coreboot.org/c/coreboot/+/29518 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I83861e32dbeeb06005c9435ba460d28756080f2d Gerrit-Change-Number: 29518 Gerrit-PatchSet: 6 Gerrit-Owner: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jett Rink <jettrink(a)chromium.org> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: arch/x86/assembly_entry: Enable long mode in romstage
by HAOUAS Elyes (Code Review) 31 Jan '19

31 Jan '19

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30114 ) Change subject: arch/x86/assembly_entry: Enable long mode in romstage ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/30114/3//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/30114/3//COMMIT_MSG@15 PS3, Line 15: Tested on qemu using KVM. Do you need a test on real board? Do you need a test on an old CPU ? lol -- To view, visit https://review.coreboot.org/c/coreboot/+/30114 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I57974a55f3b778c90b3587f39e86e4eb8692ad48 Gerrit-Change-Number: 30114 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Comment-Date: Thu, 31 Jan 2019 14:05:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: util/docker: Update container for doc.coreboot.org
by Patrick Georgi (Code Review) 31 Jan '19

31 Jan '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31129 Change subject: util/docker: Update container for doc.coreboot.org ...................................................................... util/docker: Update container for doc.coreboot.org Now running 1.8.3, with a fix to the theme so search still works, and a recommonmark version that properly rewrites links to .md files. Change-Id: Ice25554c77a398a71782c8d1cb9e205debd80d67 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M util/docker/doc.coreboot.org/Dockerfile 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/31129/1 diff --git a/util/docker/doc.coreboot.org/Dockerfile b/util/docker/doc.coreboot.org/Dockerfile index 8de0d46..d05e8b5 100644 --- a/util/docker/doc.coreboot.org/Dockerfile +++ b/util/docker/doc.coreboot.org/Dockerfile @@ -5,9 +5,9 @@ RUN apk add --no-cache python3 make bash git \ && pip3 install --upgrade --no-cache-dir pip \ && pip3 install --no-cache-dir \ - sphinx===1.7.7 \ - sphinx_rtd_theme===0.4.1 \ - recommonmark===0.4.0 \ + sphinx===1.8.3 \ + sphinx_rtd_theme===0.4.2 \ + recommonmark===0.5.0 \ sphinx_autobuild===0.7.1 \ && chmod 755 /makeSphinx.sh -- To view, visit https://review.coreboot.org/c/coreboot/+/31129 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice25554c77a398a71782c8d1cb9e205debd80d67 Gerrit-Change-Number: 31129 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: cpu/x86/mtrr: Fix sign overflow
by Angel Pons (Code Review) 31 Jan '19

31 Jan '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30502 ) Change subject: cpu/x86/mtrr: Fix sign overflow ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71b61a45becc17bf60a619e4131864c82a16b0d1 Gerrit-Change-Number: 30502 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 31 Jan 2019 08:48:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/cannonlake: Make correct C-state entries for S0ix and non-S0ix
by Ronak Kanabar (Code Review) 31 Jan '19

31 Jan '19

Ronak Kanabar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31154 Change subject: soc/intel/cannonlake: Make correct C-state entries for S0ix and non-S0ix ...................................................................... soc/intel/cannonlake: Make correct C-state entries for S0ix and non-S0ix TEST=Dump SSDT entries to verify _CST between S0ix enable and disable. Change-Id: I25e8f8c13bb91c2645e8e9fdfdf9ba4d7022f1b1 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/soc/intel/cannonlake/acpi.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/31154/1 diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 4dab334..f9f3e96 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -121,13 +121,13 @@ }, }; -static int cstate_set_s0ix[] = { +static int cstate_set_non_s0ix[] = { C_STATE_C1E, C_STATE_C6_LONG_LAT, C_STATE_C7S_LONG_LAT }; -static int cstate_set_non_s0ix[] = { +static int cstate_set_s0ix[] = { C_STATE_C1E, C_STATE_C7S_LONG_LAT, C_STATE_C10 -- To view, visit https://review.coreboot.org/c/coreboot/+/31154 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25e8f8c13bb91c2645e8e9fdfdf9ba4d7022f1b1 Gerrit-Change-Number: 31154 Gerrit-PatchSet: 1 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/sarien: Turn on ASPM L1.2 for Card Reader
by Lijian Zhao (Code Review) 31 Jan '19

31 Jan '19

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31145 Change subject: mb/google/sarien: Turn on ASPM L1.2 for Card Reader ...................................................................... mb/google/sarien: Turn on ASPM L1.2 for Card Reader Enable ASPM L1.2 support for embedded realtek card reader, after change the power consumption for SD controller from 5mW to less than 2mW. BUG=N/A TEST=Build and boot up on Arcada platform, check the PCI configuration on pcie root port offset 0x208 is 0x0f, and offset 0x168 on card reader is also 0x0f. Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: I08d85ee332ceee8ed85cd816bc3e6c895528fdb0 --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb 2 files changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/31145/1 diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 2b0408e..478c97f 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -15,7 +15,6 @@ # FSP configuration register "SaGv" = "3" - register "HeciEnabled" = "1" register "SataSalpSupport" = "1" register "SataMode" = "Sata_AHCI" register "SataPortsEnable[2]" = "1" @@ -98,6 +97,7 @@ # PCIe port 11 for card reader register "PcieRpEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "1" register "PcieClkSrcUsage[1]" = "10" register "PcieClkSrcClkReq[1]" = "1" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 0bf7e98..51d8f34 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -99,6 +99,7 @@ # PCIe port 8 for Card Reader register "PcieRpEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "1" register "PcieClkSrcUsage[4]" = "7" register "PcieClkSrcClkReq[4]" = "4" -- To view, visit https://review.coreboot.org/c/coreboot/+/31145 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08d85ee332ceee8ed85cd816bc3e6c895528fdb0 Gerrit-Change-Number: 31145 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/octopus: Add Bluetooth USB ACPI configuration
by Patrick Georgi (Code Review) 31 Jan '19

31 Jan '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31130 ) Change subject: mb/google/octopus: Add Bluetooth USB ACPI configuration ...................................................................... mb/google/octopus: Add Bluetooth USB ACPI configuration Enable USB ACPI driver for octopus boards and add bluetooth USB ACPI configuration in devicetree. This change enables exporting the bluetooth reset GPIO to the kernel for use in an rf-kill operation. BUG=b:123296264 BRANCH=octopus TEST=Boots to ChromeOS Change-Id: Ie40f1ad70f21a6fd398ce23d060e0c588ba6ce41 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Reviewed-on: https://review.coreboot.org/c/31130 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- M src/mainboard/google/octopus/Kconfig M src/mainboard/google/octopus/variants/baseboard/devicetree.cb 2 files changed, 15 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index 50e96a6..8c13961 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -9,6 +9,7 @@ select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID select DRIVERS_SPI_ACPI + select DRIVERS_USB_ACPI select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_LPC diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index 1119882c..bbaa312 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -143,7 +143,20 @@ device pci 13.3 off end # - PCIe-A 3 device pci 14.0 off end # - PCIe-B 0 device pci 14.1 off end # - PCIe-B 1 - device pci 15.0 on end # - XHCI + device pci 15.0 on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_109)" + device usb 2.2 on end + end + end + end + end # - XHCI device pci 15.1 on end # - XDCI device pci 16.0 on end # - I2C 0 device pci 16.1 on end # - I2C 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/31130 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie40f1ad70f21a6fd398ce23d060e0c588ba6ce41 Gerrit-Change-Number: 31130 Gerrit-PatchSet: 6 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: mb/google/octopus: Add Bluetooth USB ACPI configuration
by Patrick Georgi (Code Review) 31 Jan '19

31 Jan '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31130 ) Change subject: mb/google/octopus: Add Bluetooth USB ACPI configuration ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31130 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie40f1ad70f21a6fd398ce23d060e0c588ba6ce41 Gerrit-Change-Number: 31130 Gerrit-PatchSet: 5 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 31 Jan 2019 08:41:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/apollolake: Fix XHCI device name in ACPI
by Karthik Ramasubramanian (Code Review) 31 Jan '19

31 Jan '19

Hello Karthikeyan Ramasubramanian, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31147 to review the following change. Change subject: soc/intel/apollolake: Fix XHCI device name in ACPI ...................................................................... soc/intel/apollolake: Fix XHCI device name in ACPI XHCI is currently named as XHC1. This leads to namespace lookup error in the kernel when children USB ACPI devices are added under the scope of XHCI device. BUG=b:123296264 BRANCH=octopus TEST=Boot to ChromeOS; Ensure that the below error is resolved in the kernel dmesg [ 0.001000] ACPI Error: [\_SB_.PCI0.XHCI.RHUB.HS03] Namespace lookup failure, AE_NOT_FOUND (20170728/dswload-210) Change-Id: Ia4921547fee6fb51333319b9e881501a7e75ebce Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/soc/intel/apollolake/acpi/xhci.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/31147/1 diff --git a/src/soc/intel/apollolake/acpi/xhci.asl b/src/soc/intel/apollolake/acpi/xhci.asl index 8222cb5..9f85033 100644 --- a/src/soc/intel/apollolake/acpi/xhci.asl +++ b/src/soc/intel/apollolake/acpi/xhci.asl @@ -14,7 +14,7 @@ */ /* XHCI Controller 0:15.0 */ -Device (XHC1) { +Device (XHCI) { Name (_ADR, 0x00150000) /* Device 21, Function 0 */ Name (_S3D, 3) /* D3 supported in S3 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31147 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4921547fee6fb51333319b9e881501a7e75ebce Gerrit-Change-Number: 31147 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/emulation/qemu-i449fx: prepare fw_cfg for romstage usage
by Thomas Heijligen (Code Review) 31 Jan '19

31 Jan '19

Thomas Heijligen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30846 Change subject: mb/emulation/qemu-i449fx: prepare fw_cfg for romstage usage ...................................................................... mb/emulation/qemu-i449fx: prepare fw_cfg for romstage usage Add separate functions for selecting the port and reading the port. Romstage can now read incremental from the data port. Change-Id: I0ffde3bc2a4415a8af99af2275d16f6609099e37 Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com> --- M src/mainboard/emulation/qemu-i440fx/fw_cfg.c 1 file changed, 11 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/30846/1 diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c index 9b394f2..957e9d2 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c @@ -42,12 +42,22 @@ return fw_cfg_detected; } -void fw_cfg_get(int entry, void *dst, int dstlen) +static void fw_cfg_select(int entry) { outw(entry, FW_CFG_PORT_CTL); +} + +static void fw_cfg_read(void *dst, int dstlen) +{ insb(FW_CFG_PORT_DATA, dst, dstlen); } +void fw_cfg_get(int entry, void *dst, int dstlen) +{ + fw_cfg_select(entry); + fw_cfg_read(dst, dstlen); +} + static void fw_cfg_init_file(void) { u32 i, size, count = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/30846 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ffde3bc2a4415a8af99af2275d16f6609099e37 Gerrit-Change-Number: 30846 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

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coreboot-gerrit January 2019