coreboot-gerrit January 2019

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Change in ...coreboot[master]: mb/emulation/qemu-i440fx: change file handling
by Thomas Heijligen (Code Review) 31 Jan '19

31 Jan '19

Thomas Heijligen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30845 Change subject: mb/emulation/qemu-i440fx: change file handling ...................................................................... mb/emulation/qemu-i440fx: change file handling Reduce the number of fw_find_file calls by returning the file structure at fw_cfg_check_file. The file structure can then be used to allocate memory and access the file content directly without recurrence searching. Remove now unnecessary function fw_cfg_load_file. Fixed breaking function calls and add include guard at fw_cfg_if.h. Change-Id: I48cc943aaa999e4323e9d7e5dd666c5316533dcc Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com> --- M src/mainboard/emulation/qemu-i440fx/fw_cfg.c M src/mainboard/emulation/qemu-i440fx/fw_cfg.h M src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h M src/mainboard/emulation/qemu-i440fx/northbridge.c 4 files changed, 39 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/30845/1 diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c index f6a3de7..9b394f2 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c @@ -81,28 +81,16 @@ return NULL; } -int fw_cfg_check_file(const char *name) +int fw_cfg_check_file(FWCfgFile *file, const char *name) { - FWCfgFile *file; - + FWCfgFile *f; if (!fw_cfg_present()) return -1; - file = fw_cfg_find_file(name); - if (!file) + f = fw_cfg_find_file(name); + if (!f) return -1; - return file->size; -} - -void fw_cfg_load_file(const char *name, void *dst) -{ - FWCfgFile *file; - - if (!fw_cfg_present()) - return; - file = fw_cfg_find_file(name); - if (!file) - return; - fw_cfg_get(file->select, dst, file->size); + *file = *f; + return 0; } int fw_cfg_max_cpus(void) @@ -202,21 +190,21 @@ unsigned long fw_cfg_acpi_tables(unsigned long start) { + FWCfgFile f; BiosLinkerLoaderEntry *s; unsigned long *addrs, current; uint8_t *ptr; - int rc, i, j, src, dst, max; + int i, j, src, dst, max; - rc = fw_cfg_check_file("etc/table-loader"); - if (rc < 0) + if (fw_cfg_check_file(&f, "etc/table-loader")) return 0; printk(BIOS_DEBUG, "QEMU: found ACPI tables in fw_cfg.\n"); - max = rc / sizeof(*s); - s = malloc(rc); + max = f.size / sizeof(*s); + s = malloc(f.size); addrs = malloc(max * sizeof(*addrs)); - fw_cfg_load_file("etc/table-loader", s); + fw_cfg_get(f.select, s, f.size); current = start; for (i = 0; i < max && s[i].command != 0; i++) { @@ -227,14 +215,14 @@ switch (s[i].command) { case BIOS_LINKER_LOADER_COMMAND_ALLOCATE: current = ALIGN(current, s[i].alloc.align); - rc = fw_cfg_check_file(s[i].alloc.file); - if (rc < 0) + if (fw_cfg_check_file(&f, s[i].alloc.file)) goto err; + printk(BIOS_DEBUG, "QEMU: loading \"%s\" to 0x%lx (len %d)\n", - s[i].alloc.file, current, rc); - fw_cfg_load_file(s[i].alloc.file, (void*)current); + s[i].alloc.file, current, f.size); + fw_cfg_get(f.select, (void *)current, sizeof(current)); addrs[i] = current; - current += rc; + current += f.size; break; case BIOS_LINKER_LOADER_COMMAND_ADD_POINTER: @@ -400,15 +388,16 @@ */ unsigned long fw_cfg_smbios_tables(int *handle, unsigned long *current) { + FWCfgFile f; struct smbios_type0 *t0; unsigned long start, end; - int len, ret, i, count = 1; + int ret, i, count = 1; char *str; - len = fw_cfg_check_file("etc/smbios/smbios-tables"); - if (len < 0) + if (fw_cfg_check_file(&f, "etc/smbios/smbios-tables")) return 0; - printk(BIOS_DEBUG, "QEMU: found smbios tables in fw_cfg (len %d).\n", len); + + printk(BIOS_DEBUG, "QEMU: found smbios tables in fw_cfg (len %d).\n", f.size); /* * Search backwards for "coreboot" (first string in type0 table, @@ -434,7 +423,7 @@ * We'll exclude the end marker as coreboot will add one. */ printk(BIOS_DEBUG, "QEMU: loading smbios tables to 0x%lx\n", start); - fw_cfg_load_file("etc/smbios/smbios-tables", (void*)start); + fw_cfg_get(f.select, (void *)start, sizeof(start)); end = start; do { t0 = (struct smbios_type0*)end; @@ -442,7 +431,7 @@ break; end = smbios_next(end); count++; - } while (end < start + len); + } while (end < start + f.size); /* final fixups. */ ret = end - *current; diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg.h b/src/mainboard/emulation/qemu-i440fx/fw_cfg.h index 5bf16af..b5cdb92 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg.h +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg.h @@ -10,9 +10,13 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ +#ifndef FW_CFG_H +#define FW_CFG_H +#include "fw_cfg_if.h" void fw_cfg_get(int entry, void *dst, int dstlen); -int fw_cfg_check_file(const char *name); -void fw_cfg_load_file(const char *name, void *dst); +int fw_cfg_check_file(FWCfgFile *file, const char *name); int fw_cfg_max_cpus(void); unsigned long fw_cfg_smbios_tables(int *handle, unsigned long *current); + +#endif /* FW_CFG_H */ diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h b/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h index 8f1e24c..46aee9b 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h @@ -16,6 +16,8 @@ * This are the qemu firmware config interface defines and structs. * Copyed over from qemu soure tree, include/hw/nvram/fw_cfg.h */ +#ifndef FW_CFG_IF_H +#define FW_CFG_IF_H #include <stdint.h> @@ -90,3 +92,5 @@ uint8_t tabletype; uint16_t fieldoffset; } FwCfgSmbios; + +#endif /* FW_CFG_IF_H */ diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index 764e8a0..0ff4c54 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -59,17 +59,16 @@ struct resource *res; unsigned long tomk = 0, high; int idx = 10; - int size; + FWCfgFile f; pci_domain_read_resources(dev); - size = fw_cfg_check_file("etc/e820"); - if (size > 0) { + if (!fw_cfg_check_file(&f, "etc/e820") && f.size > 0) { /* supported by qemu 1.7+ */ - FwCfgE820Entry *list = malloc(size); + FwCfgE820Entry *list = malloc(f.size); int i; - fw_cfg_load_file("etc/e820", list); - for (i = 0; i < size/sizeof(*list); i++) { + fw_cfg_get(f.select, list, f.size); + for (i = 0; i < f.size / sizeof(*list); i++) { switch (list[i].type) { case 1: /* RAM */ printk(BIOS_DEBUG, "QEMU: e820/ram: 0x%08llx +0x%08llx\n", -- To view, visit https://review.coreboot.org/c/coreboot/+/30845 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I48cc943aaa999e4323e9d7e5dd666c5316533dcc Gerrit-Change-Number: 30845 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

4 10

Change in ...coreboot[master]: google/kukui: Set GPIO_RESET to output mode
by Tristan Hsieh (Code Review) 31 Jan '19

31 Jan '19

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31148 Change subject: google/kukui: Set GPIO_RESET to output mode ...................................................................... google/kukui: Set GPIO_RESET to output mode In payloads, we didn't set GPIO modes. We have to set up GPIO mode in coreboot for payloads. BUG=b:80501386 BRANCH=none TEST=HW reboot works in depthcharge Change-Id: Ibd2c6c071871edc59497fbb245cdbec6a814f621 Signed-off-by: Tristan Shieh <tristan.shieh(a)mediatek.com> --- M src/mainboard/google/kukui/chromeos.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/31148/1 diff --git a/src/mainboard/google/kukui/chromeos.c b/src/mainboard/google/kukui/chromeos.c index 77c442f..132f0d3 100644 --- a/src/mainboard/google/kukui/chromeos.c +++ b/src/mainboard/google/kukui/chromeos.c @@ -24,6 +24,7 @@ { gpio_input_pullup(EC_IN_RW); gpio_input_pullup(EC_IRQ); + gpio_output(GPIO_RESET, 0); } void fill_lb_gpios(struct lb_gpios *gpios) -- To view, visit https://review.coreboot.org/c/coreboot/+/31148 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd2c6c071871edc59497fbb245cdbec6a814f621 Gerrit-Change-Number: 31148 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-MessageType: newchange

4 6

Change in ...coreboot[master]: soc/intel/cannonlake: Remove SOC_INTEL_CANNONLAKE_MEMCFG_INIT Kconfig
by Aamir Bohra (Code Review) 31 Jan '19

31 Jan '19

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31134 ) Change subject: soc/intel/cannonlake: Remove SOC_INTEL_CANNONLAKE_MEMCFG_INIT Kconfig ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31134 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib21ea305871dc859e7db0720c18a9479100346c3 Gerrit-Change-Number: 31134 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 31 Jan 2019 06:30:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: drivers/usb: Initialize the HW once in CAR stages
by Arthur Heymans (Code Review) 31 Jan '19

31 Jan '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30481 Change subject: drivers/usb: Initialize the HW once in CAR stages ...................................................................... drivers/usb: Initialize the HW once in CAR stages The EHCI hardware needs to be initialized only once during CAR stages. Some exception need to be made when a blob messes with the EHCI hardware. To achieve this add a fixed location in the car.ld linker script such that the ehci debug information can be shared across CAR stages. Currently this means only romstage and bootblock, but verstage can also be hooked up later on. Tested on google/peppy: Both the bootblock and the romstage properly output console. Change-Id: I78e20a172fd5cc81f366d580f3cce57b9545d7a2 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/car.ld M src/arch/x86/include/arch/symbols.h M src/drivers/usb/ehci_debug.c M src/include/console/usb.h M src/northbridge/intel/sandybridge/raminit_mrc.c M src/soc/intel/fsp_baytrail/romstage/romstage.c M src/soc/intel/fsp_broadwell_de/romstage/romstage.c M src/southbridge/intel/fsp_rangeley/romstage.c 8 files changed, 32 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/30481/1 diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 8665682..893b31f 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -40,9 +40,9 @@ _car_stack_end = .; #endif /* The pre-ram cbmem console as well as the timestamp region are fixed - * in size. Therefore place them at the beginning .car.data section - * so that multiple stages (romstage and verstage) have a consistent - * link address of these shared objects. */ + * in size. Therefore place them above the car global section so that + * multiple stages (romstage and verstage) have a consistent + * link address of these shared objects. */ PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE) #if IS_ENABLED(CONFIG_PAGING_IN_CACHE_AS_RAM) . = ALIGN(32); @@ -66,6 +66,9 @@ . += 256; _car_drivers_storage_end = .; #endif + _car_ehci_dbg_info_start = .; + . += 64; + _car_ehci_dbg_info_end = .; /* _car_global_start and _car_global_end provide symbols to per-stage * variables that are not shared like the timestamp and the pre-ram * cbmem console. This is useful for clearing this area on a per-stage diff --git a/src/arch/x86/include/arch/symbols.h b/src/arch/x86/include/arch/symbols.h index 704e3bb..9ef6a3b 100644 --- a/src/arch/x86/include/arch/symbols.h +++ b/src/arch/x86/include/arch/symbols.h @@ -34,6 +34,8 @@ extern char _car_stack_end[]; #define _car_stack_size (_car_stack_end - _car_stack_start) +extern char _car_ehci_dbg_info_start[]; + /* * The _car_relocatable_data_[start|end] symbols cover CAR data which is * relocatable once memory comes online. Variables with CAR_GLOBAL decoration diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index 23aa38c..c3713d9 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -18,6 +18,7 @@ #include <console/console.h> #include <console/usb.h> #include <arch/io.h> +#include <arch/symbols.h> #include <arch/early_variables.h> #include <string.h> #include <cbmem.h> @@ -27,6 +28,7 @@ #include "ehci.h" struct ehci_debug_info { + bool initialized; void *ehci_base; void *ehci_debug; @@ -61,6 +63,10 @@ static inline struct ehci_debug_info *dbgp_ehci_info(void) { + if (IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE) + && (ENV_ROMSTAGE || ENV_BOOTBLOCK || ENV_VERSTAGE)) + glob_dbg_info_p = + (struct ehci_debug_info *)_car_ehci_dbg_info_start; if (car_get_var(glob_dbg_info_p) == NULL) car_set_var(glob_dbg_info_p, &glob_dbg_info); @@ -569,6 +575,8 @@ goto err; } + info->initialized = true; + return 0; err: /* Things didn't work so remove my claim */ @@ -648,11 +656,14 @@ #endif -static int usbdebug_hw_init(void) +static int usbdebug_hw_init(bool force) { struct ehci_debug_info *dbg_info = dbgp_ehci_info(); unsigned int ehci_base, dbg_offset; + if (dbg_info->initialized && !force) + return -1; + if (ehci_debug_hw_enable(&ehci_base, &dbg_offset)) return -1; return usbdebug_init_(ehci_base, dbg_offset, dbg_info); @@ -686,7 +697,7 @@ * are still not enabled. Should never happen. */ rv = dbgp_enabled() ? 0 : -1; if (!ENV_POSTCAR && rv < 0) - rv = usbdebug_hw_init(); + rv = usbdebug_hw_init(true); if (rv < 0) printk(BIOS_DEBUG, "usbdebug: Failed hardware init\n"); @@ -713,7 +724,7 @@ return &dbgp_ehci_info()->ep_pipe[DBGP_CONSOLE_EPIN]; } -void usbdebug_init(void) +void usbdebug_init(bool force) { /* USB console init is done early in romstage, yet delayed to * CBMEM_INIT_HOOKs for postcar and ramstage as we recover state @@ -721,16 +732,16 @@ */ if (IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE) && (ENV_ROMSTAGE || ENV_BOOTBLOCK)) - usbdebug_hw_init(); + usbdebug_hw_init(force); /* USB console init is done early in ramstage if it was * not done in romstage, this does not require CBMEM. */ if (!IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE) && ENV_POSTCAR) - usbdebug_hw_init(); + usbdebug_hw_init(force); if (!IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE) && ENV_RAMSTAGE && !IS_ENABLED(CONFIG_POSTCAR_STAGE)) - usbdebug_hw_init(); + usbdebug_hw_init(force); } diff --git a/src/include/console/usb.h b/src/include/console/usb.h index d4429e6..ed91cce 100644 --- a/src/include/console/usb.h +++ b/src/include/console/usb.h @@ -20,7 +20,7 @@ #include <rules.h> #include <stdint.h> -void usbdebug_init(void); +void usbdebug_init(bool force); void usb_tx_byte(int idx, unsigned char data); void usb_tx_flush(int idx); @@ -36,7 +36,7 @@ #define USB_PIPE_FOR_GDB 0 #if __CONSOLE_USB_ENABLE__ -static inline void __usbdebug_init(void) { usbdebug_init(); } +static inline void __usbdebug_init(void) { usbdebug_init(false); } static inline void __usb_tx_byte(u8 data) { usb_tx_byte(USB_PIPE_FOR_CONSOLE, data); @@ -52,7 +52,7 @@ #if 0 && IS_ENABLED(CONFIG_GDB_STUB) && \ ((ENV_ROMSTAGE && IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE)) \ || ENV_RAMSTAGE) -static inline void __gdb_hw_init(void) { usbdebug_init(); } +static inline void __gdb_hw_init(void) { usbdebug_init(false); } static inline void __gdb_tx_byte(u8 data) { usb_tx_byte(USB_PIPE_FOR_GDB, data); diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 1975051..46cd201 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -238,10 +238,8 @@ die("UEFI PEI System Agent not found.\n"); } -#if IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE) /* mrc.bin reconfigures USB, so reinit it to have debug */ - usbdebug_init(); -#endif + usbdebug_init(true); /* For reference print the System Agent version * after executing the UEFI PEI stage. diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c index bc49a41..c71b637 100644 --- a/src/soc/intel/fsp_baytrail/romstage/romstage.c +++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c @@ -225,10 +225,8 @@ printk(BIOS_DEBUG, "%s status: %x hob_list_ptr: %x\n", __func__, (u32) status, (u32) hob_list_ptr); -#if IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE) /* FSP reconfigures USB, so reinit it to have debug */ - usbdebug_init(); -#endif /* IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE) */ + usbdebug_init(true); printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (u32)status); diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c index 801f9e0..8e837fc 100644 --- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c +++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c @@ -101,10 +101,8 @@ printk(BIOS_DEBUG, "%s status: %x hob_list_ptr: %x\n", __func__, (u32) status, (u32) hob_list_ptr); -#if IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE) /* FSP reconfigures USB, so reinit it to have debug */ - usbdebug_init(); -#endif /* IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE) */ + usbdebug_init(true); printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (u32)status); diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c index f986d79..d001656 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.c +++ b/src/southbridge/intel/fsp_rangeley/romstage.c @@ -99,10 +99,8 @@ printk(BIOS_DEBUG, "%s status: %x hob_list_ptr: %x\n", __func__, (u32) status, (u32) hob_list_ptr); -#if IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE) /* FSP reconfigures USB, so reinit it to have debug */ - usbdebug_init(); -#endif /* IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE) */ + usbdebug_init(true); printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (u32)status); -- To view, visit https://review.coreboot.org/c/coreboot/+/30481 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78e20a172fd5cc81f366d580f3cce57b9545d7a2 Gerrit-Change-Number: 30481 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

2 1

Change in ...coreboot[master]: soc/intel/cannonlake: Add SOC_INTEL_WHISKEYLAKE kconfig
by Subrata Banik (Code Review) 31 Jan '19

31 Jan '19

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31133 ) Change subject: soc/intel/cannonlake: Add SOC_INTEL_WHISKEYLAKE kconfig ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/31133/4/src/soc/intel/cannonlake/Kconfig File src/soc/intel/cannonlake/Kconfig: https://review.coreboot.org/#/c/31133/4/src/soc/intel/cannonlake/Kconfig@26 PS4, Line 26: SOC_INTEL_CANNONLAKE > I think putting it into OR statement would communicate the same, essentially all SOCs sharing the sa […] yes, i think Intel marketing foils for CFL and WHL SoC also acknowledge that fact its build on CNP patch hence inheritance makes more sense to me rather OR'ing here. -- To view, visit https://review.coreboot.org/c/coreboot/+/31133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66b63361841f5a16615ddce4225c4f6182eabdb3 Gerrit-Change-Number: 31133 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 31 Jan 2019 06:14:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: soc/intel/cannonlake: Add SOC_INTEL_WHISKEYLAKE kconfig
by Aamir Bohra (Code Review) 31 Jan '19

31 Jan '19

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31133 ) Change subject: soc/intel/cannonlake: Add SOC_INTEL_WHISKEYLAKE kconfig ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/31133/4/src/soc/intel/cannonlake/Kconfig File src/soc/intel/cannonlake/Kconfig: https://review.coreboot.org/#/c/31133/4/src/soc/intel/cannonlake/Kconfig@26 PS4, Line 26: SOC_INTEL_CANNONLAKE > yes, that makes sense but if you see in IA coreboot code, we have ~90% code for PCH related work he […] I think putting it into OR statement would communicate the same, essentially all SOCs sharing the same IP bucket. though it won't communicate strongly that all are using CNP, if that is the case , we can keep as is. -- To view, visit https://review.coreboot.org/c/coreboot/+/31133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66b63361841f5a16615ddce4225c4f6182eabdb3 Gerrit-Change-Number: 31133 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 31 Jan 2019 06:12:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/cannonlake: Add SOC_INTEL_WHISKEYLAKE kconfig
by Subrata Banik (Code Review) 31 Jan '19

31 Jan '19

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31133 ) Change subject: soc/intel/cannonlake: Add SOC_INTEL_WHISKEYLAKE kconfig ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/31133/4/src/soc/intel/cannonlake/Kconfig File src/soc/intel/cannonlake/Kconfig: https://review.coreboot.org/#/c/31133/4/src/soc/intel/cannonlake/Kconfig@26 PS4, Line 26: SOC_INTEL_CANNONLAKE > How about SOC_INTEL_CANNONLAKE || SOC_INTEL_COFFELAKE || SOC_INTEL_WHISKEYLAKE ? […] yes, that makes sense but if you see in IA coreboot code, we have ~90% code for PCH related work hence selecting CNL from WHL or CFL still make sense to tell its based on CNP PCH. -- To view, visit https://review.coreboot.org/c/coreboot/+/31133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66b63361841f5a16615ddce4225c4f6182eabdb3 Gerrit-Change-Number: 31133 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 31 Jan 2019 06:01:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/cannonlake: Add SOC_INTEL_WHISKEYLAKE kconfig
by Aamir Bohra (Code Review) 31 Jan '19

31 Jan '19

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31133 ) Change subject: soc/intel/cannonlake: Add SOC_INTEL_WHISKEYLAKE kconfig ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/31133/4/src/soc/intel/cannonlake/Kconfig File src/soc/intel/cannonlake/Kconfig: https://review.coreboot.org/#/c/31133/4/src/soc/intel/cannonlake/Kconfig@26 PS4, Line 26: SOC_INTEL_CANNONLAKE How about SOC_INTEL_CANNONLAKE || SOC_INTEL_COFFELAKE || SOC_INTEL_WHISKEYLAKE ? Then we don't have to select SOC CANNONLAKE from coffeelake and whiskeylake configs. This might help ease checks at many places, where we want to configure something SOC specific, even IS_CFL_OR_WHL config might not be needed then. thoughts? -- To view, visit https://review.coreboot.org/c/coreboot/+/31133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66b63361841f5a16615ddce4225c4f6182eabdb3 Gerrit-Change-Number: 31133 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 31 Jan 2019 05:57:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: lib/hardwaremain: One more typo ACPI
by Subrata Banik (Code Review) 31 Jan '19

31 Jan '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31152 Change subject: lib/hardwaremain: One more typo ACPI ...................................................................... lib/hardwaremain: One more typo ACPI CB:31139 fix few ACPI type error. Here is one more typo mistake. Change-Id: Ieecf0ba8fe09ed5003d5ae766079b8f83cc891b9 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/include/nhlt.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/31152/1 diff --git a/src/include/nhlt.h b/src/include/nhlt.h index a361ed8..e4cfcf6 100644 --- a/src/include/nhlt.h +++ b/src/include/nhlt.h @@ -54,7 +54,7 @@ /* Obtain an nhlt object for adding endpoints. Returns NULL on error. */ struct nhlt *nhlt_init(void); -/* Return the size of the NHLT table including APCI header. */ +/* Return the size of the NHLT table including ACPI header. */ size_t nhlt_current_size(struct nhlt *nhlt); /* -- To view, visit https://review.coreboot.org/c/coreboot/+/31152 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieecf0ba8fe09ed5003d5ae766079b8f83cc891b9 Gerrit-Change-Number: 31152 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Documentation: Add some description of our communal places
by Patrick Georgi (Code Review) 31 Jan '19

31 Jan '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31146 Change subject: Documentation: Add some description of our communal places ...................................................................... Documentation: Add some description of our communal places Change-Id: Iede98359c22aefbfd5725a5e7cd661ef18d7284e Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- R Documentation/community/code_of_conduct.md A Documentation/community/conferences.md A Documentation/community/forums.md M Documentation/index.md 4 files changed, 40 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/31146/1 diff --git a/Documentation/code_of_conduct.md b/Documentation/community/code_of_conduct.md similarity index 100% rename from Documentation/code_of_conduct.md rename to Documentation/community/code_of_conduct.md diff --git a/Documentation/community/conferences.md b/Documentation/community/conferences.md new file mode 100644 index 0000000..5531d51 --- /dev/null +++ b/Documentation/community/conferences.md @@ -0,0 +1,19 @@ +# Conferences +The coreboot community is present at a number of conferences over the year, +usually at [FOSDEM](https://fosdem.org), [OSFC](https://osfc.io), and the +[Chaos Communication Congress](https://events.ccc.de/congress/). + +The kind of presence differs, but there's usually a booth or other kind of +gathering where everybody is welcome to say hello and to learn more about +coreboot. + +Depending on the nature of the conference, coreboot developers might bring +their development kit with them and conduct development sessions. + +## Upcoming events + +TODO: add them + +## Talks + +TODO: link to recorded talks diff --git a/Documentation/community/forums.md b/Documentation/community/forums.md new file mode 100644 index 0000000..cb0817f --- /dev/null +++ b/Documentation/community/forums.md @@ -0,0 +1,18 @@ +# Our forums + +The coreboot community has various venues to help each other and discuss the +direction of our project. + +## Mailing list + +The first address for coreboot related discussion is our mailing list. +You can subscribe on its +[information page](https://mail.coreboot.org/postorius/lists/coreboot.coreboot.org/) and +read its +[archives](https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/). + +## IRC + +We also have a +[real time chat](http://webchat.freenode.net?channels=%23coreboot) +on the Freenode IRC network's #coreboot channel diff --git a/Documentation/index.md b/Documentation/index.md index 9fdb0dc..30ab35c 100644 --- a/Documentation/index.md +++ b/Documentation/index.md @@ -9,7 +9,9 @@ * [Getting Started](getting_started/index.md) * [Rookie Guide](lessons/index.md) -* [Code of Conduct](code_of_conduct.md) +* [Code of Conduct](community/code_of_conduct.md) +* [Community forums](community/forums.md) +* [coreboot at conferences](community/conferences.md) * [Timestamps](timestamp.md) * [Intel IFD Binary Extraction](Binary_Extraction.md) * [Dealing with Untrusted Input in SMM](technotes/2017-02-dealing-with-untrusted-input-in-smm.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/31146 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iede98359c22aefbfd5725a5e7cd661ef18d7284e Gerrit-Change-Number: 31146 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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