coreboot-gerrit January 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: siemens/mc_apl2: Correct whitespaces of devicetree
by Mario Scheithauer (Code Review) 30 Jan '19

30 Jan '19

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31137 Change subject: siemens/mc_apl2: Correct whitespaces of devicetree ...................................................................... siemens/mc_apl2: Correct whitespaces of devicetree Change-Id: Ie0e11b1ce6c6acb1b74ce1196304f7e6ac4664d9 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb 1 file changed, 10 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/31137/1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb index d2d5394..e54444a 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb @@ -84,17 +84,17 @@ device i2c 0x32 on end # RTC RX6110 SA end end - device pci 16.1 on end # - I2C 1 - device pci 16.2 on end # - I2C 2 - device pci 16.3 on end # - I2C 3 - device pci 17.0 on end # - I2C 4 - device pci 17.1 on end # - I2C 5 - device pci 17.2 on end # - I2C 6 + device pci 16.1 on end # - I2C 1 + device pci 16.2 on end # - I2C 2 + device pci 16.3 on end # - I2C 3 + device pci 17.0 on end # - I2C 4 + device pci 17.1 on end # - I2C 5 + device pci 17.2 on end # - I2C 6 device pci 17.3 on end # - I2C 7 - device pci 18.0 on end # - UART 0 - device pci 18.1 on end # - UART 1 - device pci 18.2 on end # - UART 2 - device pci 18.3 on end # - UART 3 + device pci 18.0 on end # - UART 0 + device pci 18.1 on end # - UART 1 + device pci 18.2 on end # - UART 2 + device pci 18.3 on end # - UART 3 device pci 19.0 off end # - SPI 0 device pci 19.1 off end # - SPI 1 device pci 19.2 off end # - SPI 2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31137 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0e11b1ce6c6acb1b74ce1196304f7e6ac4664d9 Gerrit-Change-Number: 31137 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: siemens/mc_apl2: Activate TPM support
by Mario Scheithauer (Code Review) 30 Jan '19

30 Jan '19

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31125 Change subject: siemens/mc_apl2: Activate TPM support ...................................................................... siemens/mc_apl2: Activate TPM support TEST=Build coreboot for mc_apl2 board and check the TPM console output. Change-Id: I2b0d5a6f2c230187857c2428a70de61f21da6724 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c 3 files changed, 19 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/31125/1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig index 393f9c6..4e4a928 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig @@ -6,5 +6,8 @@ select DRIVER_INTEL_I210 select DRIVERS_I2C_RX6110SA select DRIVER_SIEMENS_NC_FPGA + select MAINBOARD_HAS_TPM2 + select MAINBOARD_HAS_LPC_TPM + select TPM_ON_FAST_SPI endif # BOARD_SIEMENS_MC_APL2 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb index 42c4310..c362e6c 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb @@ -5,7 +5,6 @@ end register "sci_irq" = "SCIS_IRQ10" - register "serirq_mode" = "SERIRQ_CONTINUOUS" # Disable all clkreq of PCIe root ports as SMARC interface do not # have this pins. @@ -84,17 +83,17 @@ device i2c 0x32 on end # RTC RX6110 SA end end - device pci 16.1 on end # - I2C 1 - device pci 16.2 on end # - I2C 2 - device pci 16.3 on end # - I2C 3 - device pci 17.0 on end # - I2C 4 - device pci 17.1 on end # - I2C 5 - device pci 17.2 on end # - I2C 6 + device pci 16.1 on end # - I2C 1 + device pci 16.2 on end # - I2C 2 + device pci 16.3 on end # - I2C 3 + device pci 17.0 on end # - I2C 4 + device pci 17.1 on end # - I2C 5 + device pci 17.2 on end # - I2C 6 device pci 17.3 on end # - I2C 7 - device pci 18.0 on end # - UART 0 - device pci 18.1 on end # - UART 1 - device pci 18.2 on end # - UART 2 - device pci 18.3 on end # - UART 3 + device pci 18.0 on end # - UART 0 + device pci 18.1 on end # - UART 1 + device pci 18.2 on end # - UART 2 + device pci 18.3 on end # - UART 3 device pci 19.0 off end # - SPI 0 device pci 19.1 off end # - SPI 1 device pci 19.2 off end # - SPI 2 @@ -104,6 +103,11 @@ device pci 1d.0 off end # - UFS device pci 1e.0 off end # - SDIO device pci 1f.0 on end # - LPC + device pci 1f.0 on # - LPC + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end device pci 1f.1 on end # - SMBUS end end diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c index a54dae5..d12e106 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c @@ -364,7 +364,7 @@ /* SIO_SPI_FS0_1V8 - Connected to ESPI_CS0# of SMARC connector. */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_105, DN_20K, DEEP, NF1, HIZCRx0, ENPD), /* SIO_SPI_FS1_1V8 - Connected to ESPI_CS1# of SMARC connector. */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_106, UP_20K, DEEP, NF1, HIZCRx0, ENPD), + PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */ /* SIO_SPI_MISO_1V8 - Connected to ESPI_IO_0 of SMARC connector. */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_109, DN_20K, DEEP, NF1, HIZCRx0, ENPD), /* SIO_SPI_MOSI_1V8 - Connected to ESPI_IO_1 of SMARC connector. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31125 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b0d5a6f2c230187857c2428a70de61f21da6724 Gerrit-Change-Number: 31125 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: lib/hardwaremain: Fix typo ACPI
by Subrata Banik (Code Review) 30 Jan '19

30 Jan '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31139 Change subject: lib/hardwaremain: Fix typo ACPI ...................................................................... lib/hardwaremain: Fix typo ACPI Change-Id: I51493203b82868d221806c2e22b0c4b62e9fac97 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/lib/hardwaremain.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/31139/1 diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index e4d5aec..98b8841 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -458,7 +458,7 @@ post_code(POST_CONSOLE_READY); /* - * CBMEM needs to be recovered because timestamps, APCI, etc rely on + * CBMEM needs to be recovered because timestamps, ACPI, etc rely on * the cbmem infrastructure being around. Explicitly recover it. */ cbmem_initialize(); -- To view, visit https://review.coreboot.org/c/coreboot/+/31139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51493203b82868d221806c2e22b0c4b62e9fac97 Gerrit-Change-Number: 31139 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: security/vboot: Add measured boot mode
by Werner Zeh (Code Review) 30 Jan '19

30 Jan '19

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29547 ) Change subject: security/vboot: Add measured boot mode ...................................................................... Patch Set 43: (1 comment) https://review.coreboot.org/#/c/29547/43/src/security/vboot/vboot_crtm.c File src/security/vboot/vboot_crtm.c: https://review.coreboot.org/#/c/29547/43/src/security/vboot/vboot_crtm.c@56 PS43, Line 56: > it's struct region_device * in both cases Sure, in this case you will end up using a variable where you store the right rdev-pointer and than have the call to tpm_measure_region() once. I can have a look into it. -- To view, visit https://review.coreboot.org/c/coreboot/+/29547 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I339a2f1051e44f36aba9f99828f130592a09355e Gerrit-Change-Number: 29547 Gerrit-PatchSet: 43 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 30 Jan 2019 10:14:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: sb/intel/common/firmware: Don't call GbE binary `firmware`
by Nico Huber (Code Review) 30 Jan '19

30 Jan '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31108 Change subject: sb/intel/common/firmware: Don't call GbE binary `firmware` ...................................................................... sb/intel/common/firmware: Don't call GbE binary `firmware` Unless things changed considerably, this file doesn't contain any firmware. It is merely replacing a configuration EEPROM for the MAC address etc. So don't call it firmware. Change-Id: Ife6190639e7f05da2cb6eddeb1b0db0e8ffc8e6e Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/southbridge/intel/common/firmware/Kconfig 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/31108/1 diff --git a/src/southbridge/intel/common/firmware/Kconfig b/src/southbridge/intel/common/firmware/Kconfig index ba54fcd..31a3df3 100644 --- a/src/southbridge/intel/common/firmware/Kconfig +++ b/src/southbridge/intel/common/firmware/Kconfig @@ -111,15 +111,15 @@ def_bool n config HAVE_GBE_BIN - bool "Add gigabit ethernet firmware" + bool "Add gigabit ethernet configuration" depends on HAVE_IFD_BIN && MAINBOARD_USES_IFD_GBE_REGION help - The integrated gigabit ethernet controller needs a firmware file. - Select this if you are going to use the PCH integrated controller - and have the firmware. + The integrated gigabit ethernet controller needs a configuration + file. Select this if you are going to use the PCH integrated + controller and want to add that file. config GBE_BIN_PATH - string "Path to gigabit ethernet firmware" + string "Path to gigabit ethernet configuration" depends on HAVE_GBE_BIN default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/gbe.bin" -- To view, visit https://review.coreboot.org/c/coreboot/+/31108 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife6190639e7f05da2cb6eddeb1b0db0e8ffc8e6e Gerrit-Change-Number: 31108 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: security/vboot: Add measured boot mode
by Patrick Rudolph (Code Review) 30 Jan '19

30 Jan '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29547 ) Change subject: security/vboot: Add measured boot mode ...................................................................... Patch Set 43: (2 comments) https://review.coreboot.org/#/c/29547/43/src/security/vboot/vboot_crtm.c File src/security/vboot/vboot_crtm.c: https://review.coreboot.org/#/c/29547/43/src/security/vboot/vboot_crtm.c@56 PS43, Line 56: > There are different arguments for tpm_measure_region() in both cases. […] it's struct region_device * in both cases https://review.coreboot.org/#/c/29547/43/src/security/vboot/vboot_crtm.c@80 PS43, Line 80: if (IS_ENABLED(CONFIG_VBOOT_SEPARATE_VERSTAGE)) { > Why? The upper code deals with romstage while this one deals with verstage. […] probably doesn't matter as the linker will drop code anyway -- To view, visit https://review.coreboot.org/c/coreboot/+/29547 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I339a2f1051e44f36aba9f99828f130592a09355e Gerrit-Change-Number: 29547 Gerrit-PatchSet: 43 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 30 Jan 2019 08:34:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: security/vboot: Add measured boot mode
by Werner Zeh (Code Review) 30 Jan '19

30 Jan '19

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29547 ) Change subject: security/vboot: Add measured boot mode ...................................................................... Patch Set 43: (2 comments) https://review.coreboot.org/#/c/29547/43/src/security/vboot/vboot_crtm.c File src/security/vboot/vboot_crtm.c: https://review.coreboot.org/#/c/29547/43/src/security/vboot/vboot_crtm.c@56 PS43, Line 56: > move tpm_measure_region() here to increase readability There are different arguments for tpm_measure_region() in both cases. Do you want to have these arguments stored in a variable? Or how do you prefer the handling of this different arguments? https://review.coreboot.org/#/c/29547/43/src/security/vboot/vboot_crtm.c@80 PS43, Line 80: if (IS_ENABLED(CONFIG_VBOOT_SEPARATE_VERSTAGE)) { > else if ? Why? The upper code deals with romstage while this one deals with verstage. We need to be able to have both paths active in one run. Or do I oversee something here? -- To view, visit https://review.coreboot.org/c/coreboot/+/29547 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I339a2f1051e44f36aba9f99828f130592a09355e Gerrit-Change-Number: 29547 Gerrit-PatchSet: 43 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 30 Jan 2019 08:02:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: security/vboot: Add measured boot mode
by Patrick Rudolph (Code Review) 30 Jan '19

30 Jan '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29547 ) Change subject: security/vboot: Add measured boot mode ...................................................................... Patch Set 43: (4 comments) https://review.coreboot.org/#/c/29547/43/src/security/tpm/tspi/tspi.c File src/security/tpm/tspi/tspi.c: https://review.coreboot.org/#/c/29547/43/src/security/tpm/tspi/tspi.c@219 PS43, Line 219: //tcpa_log_add_table_entry(name, pcr, digest, digest_len); please don't include dead code https://review.coreboot.org/#/c/29547/43/src/security/vboot/vboot_crtm.c File src/security/vboot/vboot_crtm.c: https://review.coreboot.org/#/c/29547/43/src/security/vboot/vboot_crtm.c@35 PS43, Line 35: prog_name(&bootblock), coding style is non uniform in this function https://review.coreboot.org/#/c/29547/43/src/security/vboot/vboot_crtm.c@56 PS43, Line 56: move tpm_measure_region() here to increase readability https://review.coreboot.org/#/c/29547/43/src/security/vboot/vboot_crtm.c@80 PS43, Line 80: if (IS_ENABLED(CONFIG_VBOOT_SEPARATE_VERSTAGE)) { else if ? -- To view, visit https://review.coreboot.org/c/coreboot/+/29547 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I339a2f1051e44f36aba9f99828f130592a09355e Gerrit-Change-Number: 29547 Gerrit-PatchSet: 43 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 30 Jan 2019 07:43:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: security/vboot: Add measured boot mode
by Werner Zeh (Code Review) 30 Jan '19

30 Jan '19

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29547 ) Change subject: security/vboot: Add measured boot mode ...................................................................... Patch Set 43: Code-Review+2 This patch works fine on mc_aplx and mc_bdx1. Let us bring it in as a starting point for further improvements. -- To view, visit https://review.coreboot.org/c/coreboot/+/29547 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I339a2f1051e44f36aba9f99828f130592a09355e Gerrit-Change-Number: 29547 Gerrit-PatchSet: 43 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 30 Jan 2019 06:52:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/cannonlake: Add SOC_INTEL_WHISKEYLAKE kconfig
by Subrata Banik (Code Review) 30 Jan '19

30 Jan '19

Hello Patrick Rudolph, PraveenX Hodagatta Pranesh, Angel Pons, Aamir Bohra, Duncan Laurie, Rizwan Qureshi, build bot (Jenkins), Lijian Zhao, Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/31133 to look at the new patch set (#4). Change subject: soc/intel/cannonlake: Add SOC_INTEL_WHISKEYLAKE kconfig ...................................................................... soc/intel/cannonlake: Add SOC_INTEL_WHISKEYLAKE kconfig This patch selects correct SoC support for hatch, sarien, cflrvps and whlrvp. * Hatch is WHL SoC based board * Sarien is WHL SoC based board * CFLRVP U/8/11 are CFL SoC based board * WHLRVP is based on WHL SoC Also add correct FSP blobs path for WHL SoC based designs. Change-Id: I66b63361841f5a16615ddce4225c4f6182eabdb3 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/drivers/intel/fsp2_0/Kconfig M src/mainboard/google/hatch/Kconfig M src/mainboard/google/sarien/Kconfig M src/mainboard/intel/coffeelake_rvp/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/romstage/fsp_params.c 7 files changed, 21 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/31133/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/31133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66b63361841f5a16615ddce4225c4f6182eabdb3 Gerrit-Change-Number: 31133 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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coreboot-gerrit January 2019