Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31145
Change subject: mb/google/sarien: Turn on ASPM L1.2 for Card Reader ......................................................................
mb/google/sarien: Turn on ASPM L1.2 for Card Reader
Enable ASPM L1.2 support for embedded realtek card reader, after change the power consumption for SD controller from 5mW to less than 2mW.
BUG=N/A TEST=Build and boot up on Arcada platform, check the PCI configuration on pcie root port offset 0x208 is 0x0f, and offset 0x168 on card reader is also 0x0f.
Signed-off-by: Lijian Zhao lijian.zhao@intel.com Change-Id: I08d85ee332ceee8ed85cd816bc3e6c895528fdb0 --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb 2 files changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/31145/1
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 2b0408e..478c97f 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -15,7 +15,6 @@
# FSP configuration register "SaGv" = "3" - register "HeciEnabled" = "1" register "SataSalpSupport" = "1" register "SataMode" = "Sata_AHCI" register "SataPortsEnable[2]" = "1" @@ -98,6 +97,7 @@
# PCIe port 11 for card reader register "PcieRpEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "1" register "PcieClkSrcUsage[1]" = "10" register "PcieClkSrcClkReq[1]" = "1"
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 0bf7e98..51d8f34 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -99,6 +99,7 @@
# PCIe port 8 for Card Reader register "PcieRpEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "1" register "PcieClkSrcUsage[4]" = "7" register "PcieClkSrcClkReq[4]" = "4"
Hello Casper Chang, Subrata Banik, Roy Mingi Park, Duncan Laurie, Bora Guvendik, build bot (Jenkins), Krzysztof M Sywula,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31145
to look at the new patch set (#2).
Change subject: mb/google/sarien: Turn on ASPM L1.2 for Card Reader ......................................................................
mb/google/sarien: Turn on ASPM L1.2 for Card Reader
Enable ASPM L1.2 support for embedded realtek card reader, after change the power consumption for SD controller from 5mW to less than 2mW.
BUG=N/A TEST=Build and boot up on Arcada platform, check the PCI configuration on pcie root port offset 0x208 is 0x0f, and offset 0x168 on card reader is also 0x0f.
Signed-off-by: Lijian Zhao lijian.zhao@intel.com Change-Id: I08d85ee332ceee8ed85cd816bc3e6c895528fdb0 --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb 2 files changed, 3 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/31145/2
Roy Mingi Park has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31145 )
Change subject: mb/google/sarien: Turn on ASPM L1.2 for Card Reader ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/31145/2/src/mainboard/google/sarien/variants... File src/mainboard/google/sarien/variants/arcada/devicetree.cb:
https://review.coreboot.org/#/c/31145/2/src/mainboard/google/sarien/variants... PS2, Line 18: : Hi Lance, Please remove space before tab.
Hello Casper Chang, Subrata Banik, Roy Mingi Park, Duncan Laurie, Bora Guvendik, build bot (Jenkins), Krzysztof M Sywula,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31145
to look at the new patch set (#3).
Change subject: mb/google/sarien: Turn on ASPM L1.2 for Card Reader ......................................................................
mb/google/sarien: Turn on ASPM L1.2 for Card Reader
Enable ASPM L1.2 support for embedded realtek card reader, after change the power consumption for SD controller from 5mW to less than 2mW.
BUG=N/A TEST=Build and boot up on Arcada platform, check the PCI configuration on pcie root port offset 0x208 is 0x0f, and offset 0x168 on card reader is also 0x0f.
Signed-off-by: Lijian Zhao lijian.zhao@intel.com Change-Id: I08d85ee332ceee8ed85cd816bc3e6c895528fdb0 --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb 2 files changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/31145/3
Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31145 )
Change subject: mb/google/sarien: Turn on ASPM L1.2 for Card Reader ......................................................................
Patch Set 4: Code-Review+2
Roy Mingi Park has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31145 )
Change subject: mb/google/sarien: Turn on ASPM L1.2 for Card Reader ......................................................................
Patch Set 4: Code-Review+1
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31145 )
Change subject: mb/google/sarien: Turn on ASPM L1.2 for Card Reader ......................................................................
mb/google/sarien: Turn on ASPM L1.2 for Card Reader
Enable ASPM L1.2 support for embedded realtek card reader, after change the power consumption for SD controller from 5mW to less than 2mW.
BUG=N/A TEST=Build and boot up on Arcada platform, check the PCI configuration on pcie root port offset 0x208 is 0x0f, and offset 0x168 on card reader is also 0x0f.
Signed-off-by: Lijian Zhao lijian.zhao@intel.com Change-Id: I08d85ee332ceee8ed85cd816bc3e6c895528fdb0 Reviewed-on: https://review.coreboot.org/c/31145 Reviewed-by: Duncan Laurie dlaurie@chromium.org Reviewed-by: Roy Mingi Park roy.mingi.park@intel.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb 2 files changed, 2 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved Roy Mingi Park: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 4efaf55..a47a53d 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -100,6 +100,7 @@
# PCIe port 11 for card reader register "PcieRpEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "1" register "PcieClkSrcUsage[1]" = "10" register "PcieClkSrcClkReq[1]" = "1"
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 85d4f9d..d3d26f9 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -99,6 +99,7 @@
# PCIe port 8 for Card Reader register "PcieRpEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "1" register "PcieClkSrcUsage[4]" = "7" register "PcieClkSrcClkReq[4]" = "4"
-
Duncan Laurie (Code Review) -
Lijian Zhao (Code Review)
-
Patrick Georgi (Code Review)
-
Roy Mingi Park (Code Review)