Change in ...coreboot[master]: soc/intel/icelake: Make correct C-state entries for S0ix and non-S0ix

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. (
https://review.coreboot.org/c/coreboot/+/31153


Change subject: soc/intel/icelake: Make correct C-state entries for S0ix and non-S0ix
......................................................................

soc/intel/icelake: Make correct C-state entries for S0ix and non-S0ix

TEST=Dump SSDT entries to verify _CST between S0ix enable and disable.

Change-Id: I82d8bf9d143263a80a544f6e11186a3bc9c41052
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
M src/soc/intel/icelake/acpi.c
1 file changed, 2 insertions(+), 2 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/31153/1

diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c
index 39ec58a..0e13d034 100644
--- a/src/soc/intel/icelake/acpi.c
+++ b/src/soc/intel/icelake/acpi.c
@@ -119,13 +119,13 @@
 	},
 };
 
-static int cstate_set_s0ix[] = {
+static int cstate_set_non_s0ix[] = {
 	C_STATE_C1E,
 	C_STATE_C6_LONG_LAT,
 	C_STATE_C7S_LONG_LAT
 };
 
-static int cstate_set_non_s0ix[] = {
+static int cstate_set_s0ix[] = {
 	C_STATE_C1E,
 	C_STATE_C7S_LONG_LAT,
 	C_STATE_C10

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[Ronak Kanabar (Code Review)]

Ronak Kanabar has posted comments on this change. (
https://review.coreboot.org/c/coreboot/+/31153 )

Change subject: soc/intel/icelake: Make correct C-state entries for S0ix and non-S0ix
......................................................................


Patch Set 1: Code-Review+1


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[Aamir Bohra (Code Review)]

Aamir Bohra has posted comments on this change. (
https://review.coreboot.org/c/coreboot/+/31153 )

Change subject: soc/intel/icelake: Make correct C-state entries for S0ix and non-S0ix
......................................................................


Patch Set 1: Code-Review+2


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[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. (
https://review.coreboot.org/c/coreboot/+/31153 )

Change subject: soc/intel/icelake: Make correct C-state entries for S0ix and non-S0ix
......................................................................


Patch Set 1: Code-Review+1

(2 comments)

https://review.coreboot.org/#/c/31153/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/#/c/31153/1//COMMIT_MSG@8 
PS1, Line 8: 
So currently they are switched.


https://review.coreboot.org/#/c/31153/1//COMMIT_MSG@9 
PS1, Line 9: TEST=Dump SSDT entries to verify _CST between S0ix enable and disable.
Having the actual commands to do that would be helpful.



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[Subrata Banik (Code Review)]

Hello Patrick Rudolph, Aamir Bohra, Ronak Kanabar, Paul Menzel, Duncan Laurie, Shelley
Chen, build bot (Jenkins), Furquan Shaikh, 

I'd like you to reexamine a change. Please visit

    https://review.coreboot.org/c/coreboot/+/31153

to look at the new patch set (#2).

Change subject: soc/intel/icelake: Make correct C-state entries for S0ix and non-S0ix
......................................................................

soc/intel/icelake: Make correct C-state entries for S0ix and non-S0ix

TEST=Dump SSDT entries to verify _CST between S0ix enable and disable.
 > iasl -d SSDT # to generate SSDT.dsl
Change-Id: I82d8bf9d143263a80a544f6e11186a3bc9c41052
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
M src/soc/intel/icelake/acpi.c
1 file changed, 2 insertions(+), 2 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/31153/2
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[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. (
https://review.coreboot.org/c/coreboot/+/31153 )

Change subject: soc/intel/icelake: Make correct C-state entries for S0ix and non-S0ix
......................................................................


Patch Set 2:

(1 comment)

https://review.coreboot.org/#/c/31153/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/#/c/31153/1//COMMIT_MSG@8 
PS1, Line 8: 
  So currently they are switched.
its kind of miss
i believe when initial code been developed.

basically one need to tell the C-state capability when S0ix is enable/disable.



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[Subrata Banik (Code Review)]

Subrata Banik has submitted this change and it was merged. (
https://review.coreboot.org/c/coreboot/+/31153 )

Change subject: soc/intel/icelake: Make correct C-state entries for S0ix and non-S0ix
......................................................................

soc/intel/icelake: Make correct C-state entries for S0ix and non-S0ix

TEST=Dump SSDT entries to verify _CST between S0ix enable and disable.
 > iasl -d SSDT # to generate SSDT.dsl
Change-Id: I82d8bf9d143263a80a544f6e11186a3bc9c41052
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
Reviewed-on: https://review.coreboot.org/c/31153
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar(a)intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra(a)intel.com>
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
---
M src/soc/intel/icelake/acpi.c
1 file changed, 2 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Paul Menzel: Looks good to me, but someone else must approve
  Aamir Bohra: Looks good to me, approved
  Ronak Kanabar: Looks good to me, but someone else must approve



diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c
index 39ec58a..0e13d034 100644
--- a/src/soc/intel/icelake/acpi.c
+++ b/src/soc/intel/icelake/acpi.c
@@ -119,13 +119,13 @@
 	},
 };
 
-static int cstate_set_s0ix[] = {
+static int cstate_set_non_s0ix[] = {
 	C_STATE_C1E,
 	C_STATE_C6_LONG_LAT,
 	C_STATE_C7S_LONG_LAT
 };
 
-static int cstate_set_non_s0ix[] = {
+static int cstate_set_s0ix[] = {
 	C_STATE_C1E,
 	C_STATE_C7S_LONG_LAT,
 	C_STATE_C10

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Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com>
Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
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