coreboot-gerrit January 2019

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Change in ...coreboot[master]: sb/amd/agesa/hudson/Kconfig: Disable XHCI by default, enable only wit...
by mikeb mikeb (Code Review) 22 Feb '19

22 Feb '19

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30749 to review the following change. Change subject: sb/amd/agesa/hudson/Kconfig: Disable XHCI by default, enable only with firmware ...................................................................... sb/amd/agesa/hudson/Kconfig: Disable XHCI by default, enable only with firmware Currently, by default AGESA's XHCI controller is enabled without XHCI firmware being added if USE_BLOBS isn't selected. With this faulty set of default values at least AMD Lenovo G505S laptop has the following problem: both USB 3.0 ports are not working at all, even at 2.0 mode. To avoid it we should disable XHCI controller by default and allow enabling it only with a firmware provided. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I9f2b88d65f4f300ba1a28db09fb41d6bac6252b6 --- M src/southbridge/amd/agesa/hudson/Kconfig 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/30749/1 diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index b80f734..0c6ac3e 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -41,7 +41,8 @@ config HUDSON_XHCI_ENABLE bool "Enable Hudson XHCI Controller" - default y + default n + select HUDSON_XHCI_FWM help The XHCI controller must be enabled and the XHCI firmware must be added in order to have USB 3.0 support configured @@ -50,7 +51,7 @@ XHCI controller is not enabled by coreboot. config HUDSON_XHCI_FWM - bool "Add xhci firmware" + bool "Add XHCI firmware" default y if USE_BLOBS help Add Hudson 2/3/4 XHCI Firmware to support the onboard USB 3.0 -- To view, visit https://review.coreboot.org/c/coreboot/+/30749 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f2b88d65f4f300ba1a28db09fb41d6bac6252b6 Gerrit-Change-Number: 30749 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/soc/intel/common/block/pcie: Add a workaround for ThP2 9260
by Gaggery Tsai (Code Review) 22 Feb '19

22 Feb '19

Gaggery Tsai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30486 Change subject: src/soc/intel/common/block/pcie: Add a workaround for ThP2 9260 ...................................................................... src/soc/intel/common/block/pcie: Add a workaround for ThP2 9260 This patch adds a workaround for ThP2. The PCIe root port LCTL2.TLS is by default GEN1 and ThP has bad synchronization on polarity inversion. When the root port request for speed change, ThP doesn’t confirm the request, and both sides are moving to polling after timeout, hot reset is issued, and then most of the CFG space is initialized. From the observation, CCC/ECPM/LTR would be reset to default but CCC/ECPM of root port and end devices have been reconfigured in pci_scan. The LTR configuration for root port is still missing. BUG=B:117618636 BRANCH=None TEST=Add THP2_9260_WORKAROUND in Atlas configuration & emerge-atlas coreboot chromeos-bootimage & Warm/cold reset for 10 times and didn't see unsupported request related AER error messages & $lspci -vvs 00:1c.0|grep LTR and ensure LTR+ is present. Change-Id: Id5d2814488fbc9db927edb2ead972b73ebc336ce Signed-off-by: Gaggery Tsai <gaggery.tsai(a)intel.com> --- M src/soc/intel/common/block/pcie/Kconfig M src/soc/intel/common/block/pcie/pcie.c 2 files changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/30486/1 diff --git a/src/soc/intel/common/block/pcie/Kconfig b/src/soc/intel/common/block/pcie/Kconfig index aa32324..36915fa 100644 --- a/src/soc/intel/common/block/pcie/Kconfig +++ b/src/soc/intel/common/block/pcie/Kconfig @@ -13,3 +13,8 @@ Enable debug logs in PCIe module. Allows debug information on memory base and limit, prefetchable memory base and limit, prefetchable memory base upper 32 bits and prefetchable memory limit upper 32 bits. + +config THP2_9260_WORKAROUND + bool + help + THP2 workaround diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index 3ebb4f6..07a2321 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -28,12 +28,36 @@ /* PCI-E Sub-System ID */ #define PCIE_SUBSYSTEM_VENDOR_ID 0x94 +/* + * Check the LTR for root port and enable it + */ +static void pciexp_enable_root_port_ltr(struct device *root, unsigned root_cap) +{ + u16 root_ltr; + unsigned int val; + + val = pci_read_config16(root, root_cap + PCI_EXP_DEV_CAP2_OFFSET); + + if (val & LTR_MECHANISM_SUPPORT) { + root_ltr = pci_read_config16(root, root_cap + PCI_EXP_DEV_CTL_STS2_CAP_OFFSET); + root_ltr |= LTR_MECHANISM_EN; + pci_write_config16(root, root_cap + PCI_EXP_DEV_CTL_STS2_CAP_OFFSET, root_ltr); + } +} + static void pch_pcie_init(struct device *dev) { u16 reg16; + unsigned int dev_cap; printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n"); + if (IS_ENABLED(CONFIG_THP2_9260_WORKAROUND)) { + dev_cap = pci_find_capability(dev, PCI_CAP_ID_PCIE); + if (dev_cap) + pciexp_enable_root_port_ltr(dev, dev_cap); + } + /* Enable SERR */ pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_SERR); -- To view, visit https://review.coreboot.org/c/coreboot/+/30486 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5d2814488fbc9db927edb2ead972b73ebc336ce Gerrit-Change-Number: 30486 Gerrit-PatchSet: 1 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mediatek/mt8183: Support gpio eh and rsel setting for I2C
by wang qii (Code Review) 21 Feb '19

21 Feb '19

wang qii has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30974 Change subject: mediatek/mt8183: Support gpio eh and rsel setting for I2C ...................................................................... mediatek/mt8183: Support gpio eh and rsel setting for I2C The setting of these registers are only for i2c pin. BUG=b:80501386 BRANCH=none TEST=Boot correctly on Kukui Change-Id: I518ca07645fe55aa55e94e4f98178baa0b74a882 Signed-off-by: jg_poxu <jg_poxu(a)mediatek.com> --- M src/soc/mediatek/mt8183/gpio.c M src/soc/mediatek/mt8183/include/soc/gpio.h 2 files changed, 67 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/30974/1 diff --git a/src/soc/mediatek/mt8183/gpio.c b/src/soc/mediatek/mt8183/gpio.c index d555c33..c87509a 100644 --- a/src/soc/mediatek/mt8183/gpio.c +++ b/src/soc/mediatek/mt8183/gpio.c @@ -15,10 +15,12 @@ #include <arch/io.h> #include <gpio.h> +#include <assert.h> enum { EN_OFFSET = 0x60, SEL_OFFSET = 0x80, + EH_RSEL_OFFSET = 0xF0, }; static void gpio_set_pull_pupd(gpio_t gpio, enum pull_enable enable, @@ -67,3 +69,66 @@ else gpio_set_pull_en_sel(gpio, enable, select); } + +struct i2c_pin_spec { + uint16_t id; + uint8_t eh_bit; + uint8_t rsel_bit; +}; + +#define MTK_I2C_PIN_SPEC(pad_id, eh, rsel) \ + { \ + .id = pad_id, \ + .eh_bit = eh, \ + .rsel_bit = rsel, \ + } + +static const struct i2c_pin_spec i2c_pin_spec_list[] = { + MTK_I2C_PIN_SPEC(PAD_SCL5_ID, 20, 18), + MTK_I2C_PIN_SPEC(PAD_SDA5_ID, 15, 13), + MTK_I2C_PIN_SPEC(PAD_SCL3_ID, 12, 10), + MTK_I2C_PIN_SPEC(PAD_SDA3_ID, 7, 5), + MTK_I2C_PIN_SPEC(PAD_SDA1_ID, 12, 7), + MTK_I2C_PIN_SPEC(PAD_SDA0_ID, 9, 5), + MTK_I2C_PIN_SPEC(PAD_SCL0_ID, 19, 15), + MTK_I2C_PIN_SPEC(PAD_SCL1_ID, 22, 17), + MTK_I2C_PIN_SPEC(PAD_SCL2_ID, 24, 20), + MTK_I2C_PIN_SPEC(PAD_SDA2_ID, 14, 10), + MTK_I2C_PIN_SPEC(PAD_SCL4_ID, 27, 22), + MTK_I2C_PIN_SPEC(PAD_SDA4_ID, 17, 12), +}; + +static const struct i2c_pin_spec *get_i2c_pin_spec(gpio_t gpio) +{ + size_t i; + + for (i = 0; i < ARRAY_SIZE(i2c_pin_spec_list); i++) + if (gpio.id == i2c_pin_spec_list[i].id) + return &i2c_pin_spec_list[i]; + + return NULL; +} + +void gpio_set_i2c_eh(gpio_t gpio, uint32_t select) +{ + void *reg = GPIO_TO_IOCFG_BASE(gpio.base) + EH_RSEL_OFFSET; + uint8_t bit; + const struct i2c_pin_spec *pin = get_i2c_pin_spec(gpio); + + assert(pin); + assert(select < 8); + bit = pin->eh_bit; + clrsetbits_le32(reg, 7 << bit, select << bit); +} + +void gpio_set_i2c_rsel(gpio_t gpio, uint32_t select) +{ + void *reg = GPIO_TO_IOCFG_BASE(gpio.base) + EH_RSEL_OFFSET; + uint8_t bit; + const struct i2c_pin_spec *pin = get_i2c_pin_spec(gpio); + + assert(pin); + assert(select < 4); + bit = pin->rsel_bit; + clrsetbits_le32(reg, 3 << bit, select << bit); +} diff --git a/src/soc/mediatek/mt8183/include/soc/gpio.h b/src/soc/mediatek/mt8183/include/soc/gpio.h index c3c8dda..a3a972b 100644 --- a/src/soc/mediatek/mt8183/include/soc/gpio.h +++ b/src/soc/mediatek/mt8183/include/soc/gpio.h @@ -616,5 +616,6 @@ check_member(gpio_regs, mode[22].val, 0x460); static struct gpio_regs *const mtk_gpio = (void *)(GPIO_BASE); - +void gpio_set_i2c_eh(gpio_t gpio, uint32_t select); +void gpio_set_i2c_rsel(gpio_t gpio, uint32_t select); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/30974 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I518ca07645fe55aa55e94e4f98178baa0b74a882 Gerrit-Change-Number: 30974 Gerrit-PatchSet: 1 Gerrit-Owner: wang qii <Qii.Wang(a)mediatek.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [TEST]sb/intel/common: Remove CAR_GLOBAL use
by Arthur Heymans (Code Review) 20 Feb '19

20 Feb '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30506 Change subject: [TEST]sb/intel/common: Remove CAR_GLOBAL use ...................................................................... [TEST]sb/intel/common: Remove CAR_GLOBAL use We have NO_CAR_GLOBAL_MIGRATION now. (yes?) Change-Id: Ic2c90d264d851ab4abeca07f412d43d088ad96dc Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/common/gpio.c M src/southbridge/intel/common/pmbase.c M src/southbridge/intel/common/spi.c 3 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/30506/1 diff --git a/src/southbridge/intel/common/gpio.c b/src/southbridge/intel/common/gpio.c index 7c8cfe8..140839f 100644 --- a/src/southbridge/intel/common/gpio.c +++ b/src/southbridge/intel/common/gpio.c @@ -40,7 +40,7 @@ /* Don't assume GPIO_BASE is still the same */ return pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffe; #else - static u16 gpiobase CAR_GLOBAL; + static u16 gpiobase; if (gpiobase) return gpiobase; diff --git a/src/southbridge/intel/common/pmbase.c b/src/southbridge/intel/common/pmbase.c index 2de57d6..b022629 100644 --- a/src/southbridge/intel/common/pmbase.c +++ b/src/southbridge/intel/common/pmbase.c @@ -42,7 +42,7 @@ /* Don't assume PMBASE is still the same */ return pci_read_config16(PCH_LPC_DEV, PMBASE) & 0xfffc; #else - static u16 pmbase CAR_GLOBAL; + static u16 pmbase; if (pmbase) return pmbase; diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 3ca0d6c..6ef6769 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -69,7 +69,7 @@ typedef struct spi_slave ich_spi_slave; -static int g_ichspi_lock CAR_GLOBAL = 0; +static int g_ichspi_lock = 0; typedef struct ich7_spi_regs { uint16_t spis; @@ -138,7 +138,7 @@ uint8_t fpr_max; } ich_spi_controller; -static ich_spi_controller g_cntlr CAR_GLOBAL; +static ich_spi_controller g_cntlr; enum { SPIS_SCIP = 0x0001, -- To view, visit https://review.coreboot.org/c/coreboot/+/30506 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2c90d264d851ab4abeca07f412d43d088ad96dc Gerrit-Change-Number: 30506 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/sarien/variants/sarien: Update dptf.asl for EVT1
by John Su (Code Review) 18 Feb '19

18 Feb '19

John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31170 Change subject: mb/google/sarien/variants/sarien: Update dptf.asl for EVT1 ...................................................................... mb/google/sarien/variants/sarien: Update dptf.asl for EVT1 Follow thermal table (b:123383634 comment#1) for EVT1 tunning. BUG=b:123383634 BRANCH=sarien TEST=Built and tested on sarien system Change-Id: I22908e4bf39aedb8cf31a9060084f6f36bff56ca Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> --- M src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl 1 file changed, 15 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/31170/1 diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl index d6a1274..66839a0 100644 --- a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl @@ -13,42 +13,42 @@ * GNU General Public License for more details. */ -#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_PASSIVE 99 #define DPTF_CPU_CRITICAL 100 /* Skin Sensor for CPU VR temperature monitor */ #define DPTF_TSR0_SENSOR_ID 1 #define DPTF_TSR0_SENSOR_NAME "Skin" -#define DPTF_TSR0_PASSIVE 55 -#define DPTF_TSR0_CRITICAL 70 +#define DPTF_TSR0_PASSIVE 71 +#define DPTF_TSR0_CRITICAL 100 /* Memory Sensor for DDR temperature monitor */ #define DPTF_TSR1_SENSOR_ID 2 #define DPTF_TSR1_SENSOR_NAME "DDR" -#define DPTF_TSR1_PASSIVE 55 -#define DPTF_TSR1_CRITICAL 80 +#define DPTF_TSR1_PASSIVE 56 +#define DPTF_TSR1_CRITICAL 100 /* M.2 Sensor for Ambient temperature monitor */ #define DPTF_TSR2_SENSOR_ID 3 #define DPTF_TSR2_SENSOR_NAME "Ambient" -#define DPTF_TSR2_PASSIVE 55 -#define DPTF_TSR2_CRITICAL 70 +#define DPTF_TSR2_PASSIVE 90 +#define DPTF_TSR2_CRITICAL 100 #undef DPTF_ENABLE_FAN_CONTROL #undef DPTF_ENABLE_CHARGER Name (DTRT, Package () { /* CPU Throttle Effect on CPU */ - Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 10, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 5000, 10, 0, 0, 0, 0 }, /* CPU Throttle Effect on Skin (TSR0) */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 200, 10, 0, 0, 0, 0 }, /* CPU Throttle Effect on DDR (TSR1) */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 90, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 2000, 10, 0, 0, 0, 0 }, /* CPU Throttle Effect on Ambient (TSR2) */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 200, 10, 0, 0, 0, 0 }, }) Name (MPPC, Package () @@ -58,16 +58,16 @@ 0, /* PowerLimitIndex, 0 for Power Limit 1 */ 3000, /* PowerLimitMinimum */ 25000, /* PowerLimitMaximum */ - 28000, /* TimeWindowMinimum */ - 32000, /* TimeWindowMaximum */ + 10000, /* TimeWindowMinimum */ + 10000, /* TimeWindowMaximum */ 100 /* StepSize */ }, Package () { /* Power Limit 2 */ 1, /* PowerLimitIndex, 1 for Power Limit 2 */ - 15000, /* PowerLimitMinimum */ + 3000, /* PowerLimitMinimum */ 51000, /* PowerLimitMaximum */ 28000, /* TimeWindowMinimum */ - 32000, /* TimeWindowMaximum */ + 28000, /* TimeWindowMaximum */ 100 /* StepSize */ } }) -- To view, visit https://review.coreboot.org/c/coreboot/+/31170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22908e4bf39aedb8cf31a9060084f6f36bff56ca Gerrit-Change-Number: 31170 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/baytrail: Don't use CAR_GLOBAL
by Arthur Heymans (Code Review) 13 Feb '19

13 Feb '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30511 Change subject: soc/intel/baytrail: Don't use CAR_GLOBAL ...................................................................... soc/intel/baytrail: Don't use CAR_GLOBAL All platforms using this code have NO_CAR_GLOBAL_MIGRATION. Change-Id: I731bc1c9dec6cb5bbb228b7949a73848cb73eee3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/baytrail/romstage/romstage.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/30511/1 diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 0e1d57e..72ded61 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -134,7 +134,7 @@ return NULL; } -static struct chipset_power_state power_state CAR_GLOBAL; +static struct chipset_power_state power_state; static void migrate_power_state(int is_recovery) { -- To view, visit https://review.coreboot.org/c/coreboot/+/30511 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I731bc1c9dec6cb5bbb228b7949a73848cb73eee3 Gerrit-Change-Number: 30511 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/nehalem: Remove CAR_GLOBAL use
by Arthur Heymans (Code Review) 12 Feb '19

12 Feb '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30505 Change subject: nb/intel/nehalem: Remove CAR_GLOBAL use ...................................................................... nb/intel/nehalem: Remove CAR_GLOBAL use We have NO_CAR_GLOBAL_MIGRATION now. Change-Id: I077f235029e3fe3b1368f028981985895d8b766b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/nehalem/raminit.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/30505/1 diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 54ef278..3af88bb 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -225,7 +225,7 @@ }; /* Global allocation of timings_car */ -timing_bounds_t timings_car[64] CAR_GLOBAL; +timing_bounds_t timings_car[64]; static void write_500(struct raminfo *info, int channel, u32 val, u16 addr, int bits, -- To view, visit https://review.coreboot.org/c/coreboot/+/30505 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I077f235029e3fe3b1368f028981985895d8b766b Gerrit-Change-Number: 30505 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/amd/stoneyridge: Don't use CAR_GLOBAL
by Arthur Heymans (Code Review) 12 Feb '19

12 Feb '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30509 Change subject: soc/amd/stoneyridge: Don't use CAR_GLOBAL ...................................................................... soc/amd/stoneyridge: Don't use CAR_GLOBAL All platforms using this code have NO_CAR_GLOBAL_MIGRATION. Change-Id: I422d5637caa1b55fa6bad30d25f5e34cbba40851 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/stoneyridge/spi.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/30509/1 diff --git a/src/soc/amd/stoneyridge/spi.c b/src/soc/amd/stoneyridge/spi.c index 9baf433..1f168c2 100644 --- a/src/soc/amd/stoneyridge/spi.c +++ b/src/soc/amd/stoneyridge/spi.c @@ -32,7 +32,7 @@ #define SPI_DEBUG_DRIVER IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) -static uintptr_t spibar CAR_GLOBAL; +static uintptr_t spibar; static uintptr_t get_spibase(void) { -- To view, visit https://review.coreboot.org/c/coreboot/+/30509 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I422d5637caa1b55fa6bad30d25f5e34cbba40851 Gerrit-Change-Number: 30509 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: riscv: realign our naming with the true names
by ron minnich (Code Review) 12 Feb '19

12 Feb '19

ron minnich has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31079 Change subject: riscv: realign our naming with the true names ...................................................................... riscv: realign our naming with the true names The riscv world has decided that riscv means rv32 riscv64 means rv64 and that, further, nobody is going to use names like rv32 or rv64! Poor choices IMHO but seems it's too late to change. This is the first step on aligning coreboot naming to the outside world. Partly this is needed for a 32-bit RISCV processor coming to you soon, but largely it's good to be aligned with everyone else's naming. A primary goal here is that src/arch/riscv continues to mean "all riscv regardless of word size" even though it arguably is not following the naming. But the 32- and 64-bit isa's are essentially the same save for XLEN, so this ought to work. Choosing 32- or 64-bit is done in mainboards, hence the name change for the emulation targets. With luck, we might someday be able to say "build the emulation target and pick the 32-bit variant" but our naming does not quite allow that yet. In future commits we'll probably want to move src/soc/ucb/riscv to src/soc/ucb/riscv64 but it's nice to minimize breakage. Change-Id: If842767a4b6c5e82df99b5a57b524b88044afcba Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- M MAINTAINERS R src/mainboard/emulation/qemu-riscv64/Kconfig R src/mainboard/emulation/qemu-riscv64/Kconfig.name R src/mainboard/emulation/qemu-riscv64/Makefile.inc R src/mainboard/emulation/qemu-riscv64/board_info.txt R src/mainboard/emulation/qemu-riscv64/devicetree.cb R src/mainboard/emulation/qemu-riscv64/mainboard.c R src/mainboard/emulation/qemu-riscv64/memlayout.ld R src/mainboard/emulation/qemu-riscv64/mtime.c R src/mainboard/emulation/qemu-riscv64/rom_media.c R src/mainboard/emulation/qemu-riscv64/romstage.c R src/mainboard/emulation/qemu-riscv64/uart.c D src/mainboard/emulation/spike-riscv/Kconfig.name R src/mainboard/emulation/spike-riscv64/Kconfig A src/mainboard/emulation/spike-riscv64/Kconfig.name R src/mainboard/emulation/spike-riscv64/Makefile.inc R src/mainboard/emulation/spike-riscv64/board_info.txt R src/mainboard/emulation/spike-riscv64/clint.c R src/mainboard/emulation/spike-riscv64/devicetree.cb R src/mainboard/emulation/spike-riscv64/mainboard.c R src/mainboard/emulation/spike-riscv64/memlayout.ld R src/mainboard/emulation/spike-riscv64/rom_media.c R src/mainboard/emulation/spike-riscv64/romstage.c R src/mainboard/emulation/spike-riscv64/uart.c 24 files changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/31079/1 diff --git a/MAINTAINERS b/MAINTAINERS index fbaad69..8131178 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -141,7 +141,7 @@ F: src/arch/riscv/ F: src/soc/sifive/ F: src/soc/ucb/ -F: src/mainboard/emulation/*-riscv/ +F: src/mainboard/emulation/*-riscv*/ F: src/mainboard/sifive/ F: util/riscv/ diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig b/src/mainboard/emulation/qemu-riscv64/Kconfig similarity index 91% rename from src/mainboard/emulation/qemu-riscv/Kconfig rename to src/mainboard/emulation/qemu-riscv64/Kconfig index 528b21e..62b8e3a 100644 --- a/src/mainboard/emulation/qemu-riscv/Kconfig +++ b/src/mainboard/emulation/qemu-riscv64/Kconfig @@ -27,11 +27,11 @@ config MAINBOARD_DIR string - default emulation/qemu-riscv + default emulation/qemu-riscv64 config MAINBOARD_PART_NUMBER string - default "QEMU RISCV" + default "QEMU RISCV64" config MAX_CPUS int @@ -41,4 +41,4 @@ int default 32768 -endif # BOARD_EMULATION_QEMU_RISCV +endif # BOARD_EMULATION_QEMU_RISCV64 diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig.name b/src/mainboard/emulation/qemu-riscv64/Kconfig.name similarity index 61% rename from src/mainboard/emulation/qemu-riscv/Kconfig.name rename to src/mainboard/emulation/qemu-riscv64/Kconfig.name index e9243e6..54454cb 100644 --- a/src/mainboard/emulation/qemu-riscv/Kconfig.name +++ b/src/mainboard/emulation/qemu-riscv64/Kconfig.name @@ -1,2 +1,2 @@ config BOARD_EMULATION_QEMU_RISCV - bool "QEMU riscv" + bool "QEMU riscv64" diff --git a/src/mainboard/emulation/qemu-riscv/Makefile.inc b/src/mainboard/emulation/qemu-riscv64/Makefile.inc similarity index 100% rename from src/mainboard/emulation/qemu-riscv/Makefile.inc rename to src/mainboard/emulation/qemu-riscv64/Makefile.inc diff --git a/src/mainboard/emulation/qemu-riscv/board_info.txt b/src/mainboard/emulation/qemu-riscv64/board_info.txt similarity index 100% rename from src/mainboard/emulation/qemu-riscv/board_info.txt rename to src/mainboard/emulation/qemu-riscv64/board_info.txt diff --git a/src/mainboard/emulation/qemu-riscv/devicetree.cb b/src/mainboard/emulation/qemu-riscv64/devicetree.cb similarity index 100% rename from src/mainboard/emulation/qemu-riscv/devicetree.cb rename to src/mainboard/emulation/qemu-riscv64/devicetree.cb diff --git a/src/mainboard/emulation/qemu-riscv/mainboard.c b/src/mainboard/emulation/qemu-riscv64/mainboard.c similarity index 100% rename from src/mainboard/emulation/qemu-riscv/mainboard.c rename to src/mainboard/emulation/qemu-riscv64/mainboard.c diff --git a/src/mainboard/emulation/qemu-riscv/memlayout.ld b/src/mainboard/emulation/qemu-riscv64/memlayout.ld similarity index 100% rename from src/mainboard/emulation/qemu-riscv/memlayout.ld rename to src/mainboard/emulation/qemu-riscv64/memlayout.ld diff --git a/src/mainboard/emulation/qemu-riscv/mtime.c b/src/mainboard/emulation/qemu-riscv64/mtime.c similarity index 100% rename from src/mainboard/emulation/qemu-riscv/mtime.c rename to src/mainboard/emulation/qemu-riscv64/mtime.c diff --git a/src/mainboard/emulation/qemu-riscv/rom_media.c b/src/mainboard/emulation/qemu-riscv64/rom_media.c similarity index 100% rename from src/mainboard/emulation/qemu-riscv/rom_media.c rename to src/mainboard/emulation/qemu-riscv64/rom_media.c diff --git a/src/mainboard/emulation/qemu-riscv/romstage.c b/src/mainboard/emulation/qemu-riscv64/romstage.c similarity index 100% rename from src/mainboard/emulation/qemu-riscv/romstage.c rename to src/mainboard/emulation/qemu-riscv64/romstage.c diff --git a/src/mainboard/emulation/qemu-riscv/uart.c b/src/mainboard/emulation/qemu-riscv64/uart.c similarity index 100% rename from src/mainboard/emulation/qemu-riscv/uart.c rename to src/mainboard/emulation/qemu-riscv64/uart.c diff --git a/src/mainboard/emulation/spike-riscv/Kconfig.name b/src/mainboard/emulation/spike-riscv/Kconfig.name deleted file mode 100644 index 17549c6..0000000 --- a/src/mainboard/emulation/spike-riscv/Kconfig.name +++ /dev/null @@ -1,3 +0,0 @@ -config BOARD_EMULATION_SPIKE_RISCV - bool "SPIKE riscv" - help diff --git a/src/mainboard/emulation/spike-riscv/Kconfig b/src/mainboard/emulation/spike-riscv64/Kconfig similarity index 86% rename from src/mainboard/emulation/spike-riscv/Kconfig rename to src/mainboard/emulation/spike-riscv64/Kconfig index f8c98ab..c09b621 100644 --- a/src/mainboard/emulation/spike-riscv/Kconfig +++ b/src/mainboard/emulation/spike-riscv64/Kconfig @@ -12,7 +12,7 @@ ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. -if BOARD_EMULATION_SPIKE_RISCV +if BOARD_EMULATION_SPIKE_RISCV64 config BOARD_SPECIFIC_OPTIONS def_bool y @@ -24,14 +24,14 @@ config MAINBOARD_DIR string - default emulation/spike-riscv + default emulation/spike-riscv64 config MAINBOARD_PART_NUMBER string - default "SPIKE RISCV" + default "SPIKE RISCV64" config MAX_CPUS int default 1 -endif # BOARD_EMULATION_SPIKE_RISCV +endif # BOARD_EMULATION_SPIKE_RISCV64 diff --git a/src/mainboard/emulation/spike-riscv64/Kconfig.name b/src/mainboard/emulation/spike-riscv64/Kconfig.name new file mode 100644 index 0000000..b743bd5 --- /dev/null +++ b/src/mainboard/emulation/spike-riscv64/Kconfig.name @@ -0,0 +1,3 @@ +config BOARD_EMULATION_SPIKE_RISCV64 + bool "SPIKE riscv64" + help diff --git a/src/mainboard/emulation/spike-riscv/Makefile.inc b/src/mainboard/emulation/spike-riscv64/Makefile.inc similarity index 100% rename from src/mainboard/emulation/spike-riscv/Makefile.inc rename to src/mainboard/emulation/spike-riscv64/Makefile.inc diff --git a/src/mainboard/emulation/spike-riscv/board_info.txt b/src/mainboard/emulation/spike-riscv64/board_info.txt similarity index 100% rename from src/mainboard/emulation/spike-riscv/board_info.txt rename to src/mainboard/emulation/spike-riscv64/board_info.txt diff --git a/src/mainboard/emulation/spike-riscv/clint.c b/src/mainboard/emulation/spike-riscv64/clint.c similarity index 100% rename from src/mainboard/emulation/spike-riscv/clint.c rename to src/mainboard/emulation/spike-riscv64/clint.c diff --git a/src/mainboard/emulation/spike-riscv/devicetree.cb b/src/mainboard/emulation/spike-riscv64/devicetree.cb similarity index 100% rename from src/mainboard/emulation/spike-riscv/devicetree.cb rename to src/mainboard/emulation/spike-riscv64/devicetree.cb diff --git a/src/mainboard/emulation/spike-riscv/mainboard.c b/src/mainboard/emulation/spike-riscv64/mainboard.c similarity index 100% rename from src/mainboard/emulation/spike-riscv/mainboard.c rename to src/mainboard/emulation/spike-riscv64/mainboard.c diff --git a/src/mainboard/emulation/spike-riscv/memlayout.ld b/src/mainboard/emulation/spike-riscv64/memlayout.ld similarity index 100% rename from src/mainboard/emulation/spike-riscv/memlayout.ld rename to src/mainboard/emulation/spike-riscv64/memlayout.ld diff --git a/src/mainboard/emulation/spike-riscv/rom_media.c b/src/mainboard/emulation/spike-riscv64/rom_media.c similarity index 100% rename from src/mainboard/emulation/spike-riscv/rom_media.c rename to src/mainboard/emulation/spike-riscv64/rom_media.c diff --git a/src/mainboard/emulation/spike-riscv/romstage.c b/src/mainboard/emulation/spike-riscv64/romstage.c similarity index 100% rename from src/mainboard/emulation/spike-riscv/romstage.c rename to src/mainboard/emulation/spike-riscv64/romstage.c diff --git a/src/mainboard/emulation/spike-riscv/uart.c b/src/mainboard/emulation/spike-riscv64/uart.c similarity index 100% rename from src/mainboard/emulation/spike-riscv/uart.c rename to src/mainboard/emulation/spike-riscv64/uart.c -- To view, visit https://review.coreboot.org/c/coreboot/+/31079 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If842767a4b6c5e82df99b5a57b524b88044afcba Gerrit-Change-Number: 31079 Gerrit-PatchSet: 1 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newchange

2 6

Change in ...coreboot[master]: mb/intel/galileo: Drop the FSP1.1 option
by Arthur Heymans (Code Review) 11 Feb '19

11 Feb '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30946 Change subject: mb/intel/galileo: Drop the FSP1.1 option ...................................................................... mb/intel/galileo: Drop the FSP1.1 option This board is EOL and has FSP2.0 support, so drop the older version. Change-Id: If5297e87c7a7422e1a129a2d8687fc86a5015a77 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/intel/galileo/Kconfig M src/mainboard/intel/galileo/Makefile.inc M src/mainboard/intel/galileo/romstage.c M src/soc/intel/quark/Kconfig M src/soc/intel/quark/Makefile.inc D src/soc/intel/quark/fsp1_1.c M src/soc/intel/quark/include/soc/pm.h M src/soc/intel/quark/include/soc/ramstage.h M src/soc/intel/quark/include/soc/romstage.h M src/soc/intel/quark/romstage/Makefile.inc D src/soc/intel/quark/romstage/fsp1_1.c D src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h 12 files changed, 11 insertions(+), 671 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/30946/1 diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig index 0af03e5..0f49c7f 100644 --- a/src/mainboard/intel/galileo/Kconfig +++ b/src/mainboard/intel/galileo/Kconfig @@ -23,6 +23,10 @@ select SOC_INTEL_QUARK select MAINBOARD_HAS_I2C_TPM_ATMEL select MAINBOARD_HAS_TPM2 + select PLATFORM_USES_FSP2_0 + select UDK_2015_BINDING + select POSTCAR_STAGE + config MAINBOARD_DIR string @@ -46,31 +50,6 @@ should initialize. choice - prompt "FSP version" - default FSP_VERSION_2_0 - -config FSP_VERSION_1_1 - bool "FSP 1.1" - select PLATFORM_USES_FSP1_1 -# select ADD_FSP_RAW_BIN - help - Use FSP 1_1 binary -config FSP_VERSION_2_0 - bool "FSP 2.0" - select PLATFORM_USES_FSP2_0 - select UDK_2015_BINDING - select POSTCAR_STAGE - help - Use FSP 2.0 binary - -endchoice - -config FSP_VERSION - string - default "fsp1_1" if FSP_VERSION_1_1 - default "fsp2_0" if FSP_VERSION_2_0 - -choice prompt "FSP binary type" default FSP_BUILD_TYPE_DEBUG @@ -92,28 +71,14 @@ choice prompt "FSP type" - depends on FSP_VERSION_2_0 || FSP_VERSION_1_1 - default FSP_TYPE_1_1_PEI if FSP_VERSION_1_1 - default FSP_TYPE_2_0_PEI if FSP_VERSION_2_0 + default FSP_TYPE_2_0_PEI -config FSP_TYPE_1_1 - bool "MemInit subroutine" - depends on FSP_VERSION_1_1 - help - FSP 1.1 implemented as subroutines, no EDK-II cores -config FSP_TYPE_1_1_PEI - bool "SEC + PEI Core + MemInit PEIM" - depends on FSP_VERSION_1_1 - help - FSP 1.1 implemented using SEC and PEI core config FSP_TYPE_2_0 bool "MemInit subroutine" - depends on FSP_VERSION_2_0 help FSP 2.0 implemented as subroutines, no EDK-II cores config FSP_TYPE_2_0_PEI bool "SEC + PEI Core + MemInit PEIM" - depends on FSP_VERSION_2_0 help FSP 2.0 implemented using SEC and PEI core @@ -121,26 +86,22 @@ config FSP_TYPE string - default "Fsp1_1" if FSP_TYPE_1_1 - default "Fsp1_1Pei" if FSP_TYPE_1_1_PEI default "Fsp2_0" if FSP_TYPE_2_0 default "Fsp2_0Pei" if FSP_TYPE_2_0_PEI config FSP_DEBUG_ALL bool "Enable all FSP debug support" - depends on FSP_VERSION_2_0 || FSP_VERSION_1_1 default y # Enable display and verification for coreboot build tests select DISPLAY_HOBS select DISPLAY_MTRRS select DISPLAY_SMM_MEMORY_MAP select DISPLAY_UPD_DATA - select DISPLAY_ESRAM_LAYOUT if FSP_VERSION_2_0 - select DISPLAY_FSP_CALLS_AND_STATUS if FSP_VERSION_2_0 - select DISPLAY_FSP_HEADER if FSP_VERSION_2_0 - select POSTCAR_CONSOLE if FSP_VERSION_2_0 - select VERIFY_HOBS if FSP_VERSION_2_0 - select DISPLAY_FSP_ENTRY_POINTS if FSP_VERSION_1_1 + select DISPLAY_ESRAM_LAYOUT + select DISPLAY_FSP_CALLS_AND_STATUS + select DISPLAY_FSP_HEADER + select POSTCAR_CONSOLE + select VERIFY_HOBS help Turn on debug support to display HOBS, MTRRS, SMM_MEMORY_MAP, UPD_DATA also turn on FSP 2.0 debug support for ESRAM_LAYOUT, diff --git a/src/mainboard/intel/galileo/Makefile.inc b/src/mainboard/intel/galileo/Makefile.inc index 60c0ee0..3c6c7bd 100644 --- a/src/mainboard/intel/galileo/Makefile.inc +++ b/src/mainboard/intel/galileo/Makefile.inc @@ -13,10 +13,6 @@ ## GNU General Public License for more details. ## -ifeq ($(CONFIG_PLATFORM_USES_FSP2_0)$(CONFIG_PLATFORM_USES_FSP1_1),y) -CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/$(CONFIG_FSP_VERSION)/quark -endif - bootblock-y += gpio.c bootblock-y += reg_access.c diff --git a/src/mainboard/intel/galileo/romstage.c b/src/mainboard/intel/galileo/romstage.c index baf9af3..7e06c94 100644 --- a/src/mainboard/intel/galileo/romstage.c +++ b/src/mainboard/intel/galileo/romstage.c @@ -1,26 +1 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) -#include <fsp/romstage.h> - -/* All FSP specific code goes in this block */ -void mainboard_romstage_entry(struct romstage_params *rp) -{ - /* Call back into chipset code with platform values updated. */ - romstage_common(rp); -} -#endif /* IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) */ +/* Dummy */ diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index beed8cd..2a0c132 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -107,17 +107,6 @@ Indicate that ESRAM has been successfully initialized. If the SD LED does not light then the ESRAM initialization needs to be debugged. -config ENABLE_DEBUG_LED_FINDFSP - bool "SD LED indicates fsp.bin file was found" - depends on PLATFORM_USES_FSP1_1 - default n - select ENABLE_DEBUG_LED - help - Indicate that fsp.bin was found. If the SD LED does not light then - the code between ESRAM initialization through find_fsp needs to - debugged. Start by verifying that the correct fsp.bin is in the - image. - config ENABLE_DEBUG_LED_BOOTBLOCK_ENTRY bool "SD LED indicates bootblock.c successfully entered" default n @@ -160,12 +149,10 @@ config DCACHE_RAM_BASE hex - default 0x80070000 if PLATFORM_USES_FSP1_1 default 0x80000000 config DCACHE_RAM_SIZE hex - default 0x8000 if PLATFORM_USES_FSP1_1 default 0x40000 config DISPLAY_ESRAM_LAYOUT @@ -197,48 +184,12 @@ # SoC code to boot coreboot and its payload. ##### -config ADD_FSP_RAW_BIN - bool "Add the Intel FSP binary to the flash image without relocation" - default n - depends on PLATFORM_USES_FSP1_1 - help - Select this option to add an Intel FSP binary to - the resulting coreboot image. - - Note: Without this binary, coreboot builds relying on the FSP - will not boot - -config FSP_FILE - string "Intel FSP binary path and filename" - default "3rdparty/blobs/soc/intel/quark/$(CONFIG_FSP_TYPE)/$(CONFIG_FSP_BUILD_TYPE)/FSP.fd" - depends on PLATFORM_USES_FSP1_1 - depends on ADD_FSP_RAW_BIN - help - The path and filename of the Intel FSP binary for this platform. - -config FSP_LOC - hex - default 0xfff80000 - depends on PLATFORM_USES_FSP1_1 - help - The location in CBFS that the FSP is located. This must match the - value that is set in the FSP binary. If the FSP needs to be moved, - rebase the FSP with Intel's BCT (tool). - config FSP_ESRAM_LOC hex - default 0x80000000 if PLATFORM_USES_FSP1_1 default 0x80040000 help The location in ESRAM where a copy of the FSP binary is placed. -config RELOCATE_FSP_INTO_DRAM - bool "Relocate FSP into DRAM" - default n - depends on PLATFORM_USES_FSP1_1 - help - Relocate the FSP binary into DRAM before the call to SiliconInit. - config FSP_M_FILE string depends on PLATFORM_USES_FSP2_0 diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index 654f0a7..f1382f5 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -49,7 +49,6 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += chip.c ramstage-y += ehci.c -ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1.c ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp2_0.c ramstage-y += gpio_i2c.c ramstage-y += i2c.c diff --git a/src/soc/intel/quark/fsp1_1.c b/src/soc/intel/quark/fsp1_1.c deleted file mode 100644 index 41dbb6c..0000000 --- a/src/soc/intel/quark/fsp1_1.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <fsp/util.h> -#include <soc/ramstage.h> - -void fsp_silicon_init(bool s3wake) -{ - if (IS_ENABLED(CONFIG_RELOCATE_FSP_INTO_DRAM)) - intel_silicon_init(); - else - fsp_run_silicon_init(find_fsp(CONFIG_FSP_ESRAM_LOC), s3wake); -} - -void soc_silicon_init_params(SILICON_INIT_UPD *upd) -{ -} - -void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, - SILICON_INIT_UPD *new) -{ -} diff --git a/src/soc/intel/quark/include/soc/pm.h b/src/soc/intel/quark/include/soc/pm.h index c682a24..a3fb02f 100644 --- a/src/soc/intel/quark/include/soc/pm.h +++ b/src/soc/intel/quark/include/soc/pm.h @@ -25,10 +25,6 @@ } __packed; struct chipset_power_state *get_power_state(void); -#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) -struct chipset_power_state *fill_power_state(void); -#else int fill_power_state(void); -#endif #endif /* _SOC_PM_H_ */ diff --git a/src/soc/intel/quark/include/soc/ramstage.h b/src/soc/intel/quark/include/soc/ramstage.h index 821f43e..da2eb61 100644 --- a/src/soc/intel/quark/include/soc/ramstage.h +++ b/src/soc/intel/quark/include/soc/ramstage.h @@ -20,15 +20,9 @@ #include <arch/cpu.h> #include <chip.h> #include <device/device.h> -#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) -#include <fsp/ramstage.h> -#endif #include <soc/QuarkNcSocId.h> void mainboard_gpio_i2c_init(struct device *dev); -#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) -void fsp_silicon_init(bool s3wake); -#endif asmlinkage void chipset_teardown_car(void); #endif /* _SOC_RAMSTAGE_H_ */ diff --git a/src/soc/intel/quark/include/soc/romstage.h b/src/soc/intel/quark/include/soc/romstage.h index 43d420e..fb8a844 100644 --- a/src/soc/intel/quark/include/soc/romstage.h +++ b/src/soc/intel/quark/include/soc/romstage.h @@ -22,11 +22,7 @@ #error "Don't include romstage.h from a ramstage compilation unit!" #endif -#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) -#include <fsp/romstage.h> -#else #include <soc/car.h> -#endif #include <soc/reg_access.h> asmlinkage void *car_stage_c_entry(void); diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc index 3a33f43..742a4fa 100644 --- a/src/soc/intel/quark/romstage/Makefile.inc +++ b/src/soc/intel/quark/romstage/Makefile.inc @@ -19,7 +19,6 @@ romstage-$(CONFIG_DISPLAY_UPD_DATA) += debug.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp2_0.c endif # CONFIG_PLATFORM_USES_FSP2_0 -romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1.c romstage-y += mtrr.c romstage-y += pcie.c romstage-y += report_platform.c diff --git a/src/soc/intel/quark/romstage/fsp1_1.c b/src/soc/intel/quark/romstage/fsp1_1.c deleted file mode 100644 index 88f7376..0000000 --- a/src/soc/intel/quark/romstage/fsp1_1.c +++ /dev/null @@ -1,247 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/early_variables.h> -#include <console/console.h> -#include "../chip.h" -#include <fsp/memmap.h> -#include <fsp/util.h> -#include <soc/pci_devs.h> -#include <soc/QuarkNcSocId.h> -#include <soc/romstage.h> -#include <string.h> - -extern void asmlinkage light_sd_led(void); - -asmlinkage void *car_stage_c_entry(void) -{ - FSP_INFO_HEADER *fih; - struct cache_as_ram_params car_params = {0}; - void *top_of_stack; - - post_code(0x20); - - /* Copy the FSP binary into ESRAM */ - memcpy((void *)CONFIG_FSP_ESRAM_LOC, (void *)CONFIG_FSP_LOC, - 0x00040000); - - /* Locate the FSP header in ESRAM */ - fih = find_fsp(CONFIG_FSP_ESRAM_LOC); - if (IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_FINDFSP)) - light_sd_led(); - - /* Start the early verstage/romstage code */ - post_code(0x2A); - car_params.fih = fih; - top_of_stack = cache_as_ram_main(&car_params); - - /* Initialize MTRRs and switch stacks after RAM initialized */ - return top_of_stack; -} - -static struct chipset_power_state power_state CAR_GLOBAL; - -struct chipset_power_state *get_power_state(void) -{ - return (struct chipset_power_state *)car_get_var_ptr(&power_state); -} - -struct chipset_power_state *fill_power_state(void) -{ - struct chipset_power_state *ps = get_power_state(); - - ps->prev_sleep_state = 0; - printk(BIOS_SPEW, "prev_sleep_state %d\n", ps->prev_sleep_state); - return ps; -} - -size_t mmap_region_granularity(void) -{ - /* Align to 8 MiB by default */ - return 8 << 20; -} - -/* Initialize the UPD parameters for MemoryInit */ -void soc_memory_init_params(struct romstage_params *params, - MEMORY_INIT_UPD *upd) -{ - const struct device *dev; - const struct soc_intel_quark_config *config; - void *rmu_data; - size_t rmu_data_len; - - /* Locate the configuration data from devicetree.cb */ - dev = pcidev_path_on_root(LPC_DEV_FUNC); - if (!dev) { - printk(BIOS_CRIT, - "Error! Device (PCI:0:%02x.%01x) not found, " - "soc_memory_init_params!\n", PCI_DEVICE_NUMBER_QNC_LPC, - PCI_FUNCTION_NUMBER_QNC_LPC); - return; - } - config = dev->chip_info; - - /* Clear SMI and wake events */ - clear_smi_and_wake_events(); - - /* Locate the RMU data file in flash */ - rmu_data = locate_rmu_file(&rmu_data_len); - if (!rmu_data) - die("Microcode file (rmu.bin) not found."); - - /* Display the ESRAM layout */ - if (IS_ENABLED(CONFIG_DISPLAY_ESRAM_LAYOUT)) { - printk(BIOS_SPEW, "\nESRAM Layout:\n\n"); - printk(BIOS_SPEW, - "+-------------------+ 0x80080000 - ESRAM end\n"); - if (_car_relocatable_data_end != (void *)0x80080000) { - printk(BIOS_SPEW, "| |\n"); - printk(BIOS_SPEW, "+-------------------+ 0x%p\n", - _car_relocatable_data_end); - } - printk(BIOS_SPEW, "| coreboot data |\n"); - printk(BIOS_SPEW, "+-------------------+ 0x%p\n", - _car_stack_end); - printk(BIOS_SPEW, "| coreboot stack |\n"); - printk(BIOS_SPEW, "+-------------------+ 0x%p", - _car_stack_start); - if (IS_ENABLED(CONFIG_VBOOT_SEPARATE_VERSTAGE)) { - printk(BIOS_SPEW, "\n"); - printk(BIOS_SPEW, "| vboot data |\n"); - printk(BIOS_SPEW, "+-------------------+ 0x%08x", - CONFIG_DCACHE_RAM_BASE); - } - printk(BIOS_SPEW, " (CONFIG_DCACHE_RAM_BASE)\n"); - - printk(BIOS_SPEW, "| FSP data |\n"); - printk(BIOS_SPEW, "+-------------------+\n"); - printk(BIOS_SPEW, "| FSP stack |\n"); - printk(BIOS_SPEW, "+-------------------+\n"); - printk(BIOS_SPEW, "| FSP binary |\n"); - printk(BIOS_SPEW, - "+-------------------+ 0x80000000 - ESRAM start\n\n"); - } - - /* Update the UPD data for MemoryInit */ - upd->AddrMode = config->AddrMode; - upd->ChanMask = config->ChanMask; - upd->ChanWidth = config->ChanWidth; - upd->DramDensity = config->DramDensity; - upd->DramRonVal = config->DramRonVal; - upd->DramRttNomVal = config->DramRttNomVal; - upd->DramRttWrVal = config->DramRttWrVal; - upd->DramSpeed = config->DramSpeed; - upd->DramType = config->DramType; - upd->DramWidth = config->DramWidth; - upd->EccScrubBlkSize = config->EccScrubBlkSize; - upd->EccScrubInterval = config->EccScrubInterval; - upd->Flags = config->Flags; - upd->FspReservedMemoryLength = config->FspReservedMemoryLength; - upd->RankMask = config->RankMask; - upd->RmuBaseAddress = (uintptr_t)rmu_data; - upd->RmuLength = rmu_data_len; - upd->SerialPortWriteChar = console_log_level(BIOS_SPEW) - ? (uintptr_t)fsp_write_line : 0; - upd->SmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? - config->SmmTsegSize : 0; - upd->SocRdOdtVal = config->SocRdOdtVal; - upd->SocWrRonVal = config->SocWrRonVal; - upd->SocWrSlewRate = config->SocWrSlewRate; - upd->SrInt = config->SrInt; - upd->SrTemp = config->SrTemp; - upd->tCL = config->tCL; - upd->tFAW = config->tFAW; - upd->tRAS = config->tRAS; - upd->tRRD = config->tRRD; - upd->tWTR = config->tWTR; -} - -void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, - MEMORY_INIT_UPD *new) -{ - /* Display the parameters for MemoryInit */ - printk(BIOS_SPEW, "UPD values for MemoryInit at: 0x%p\n", new); - fsp_display_upd_value("AddrMode", sizeof(old->AddrMode), - old->AddrMode, new->AddrMode); - fsp_display_upd_value("ChanMask", sizeof(old->ChanMask), - old->ChanMask, new->ChanMask); - fsp_display_upd_value("ChanWidth", sizeof(old->ChanWidth), - old->ChanWidth, new->ChanWidth); - fsp_display_upd_value("DramDensity", sizeof(old->DramDensity), - old->DramDensity, new->DramDensity); - fsp_display_upd_value("DramRonVal", sizeof(old->DramRonVal), - old->DramRonVal, new->DramRonVal); - fsp_display_upd_value("DramRttNomVal", sizeof(old->DramRttNomVal), - old->DramRttNomVal, new->DramRttNomVal); - fsp_display_upd_value("DramRttWrVal", sizeof(old->DramRttWrVal), - old->DramRttWrVal, new->DramRttWrVal); - fsp_display_upd_value("DramSpeed", sizeof(old->DramSpeed), - old->DramSpeed, new->DramSpeed); - fsp_display_upd_value("DramType", sizeof(old->DramType), - old->DramType, new->DramType); - fsp_display_upd_value("DramWidth", sizeof(old->DramWidth), - old->DramWidth, new->DramWidth); - fsp_display_upd_value("EccScrubBlkSize", sizeof(old->EccScrubBlkSize), - old->EccScrubBlkSize, new->EccScrubBlkSize); - fsp_display_upd_value("EccScrubInterval", sizeof(old->EccScrubInterval), - old->EccScrubInterval, new->EccScrubInterval); - fsp_display_upd_value("Flags", sizeof(old->Flags), old->Flags, - new->Flags); - fsp_display_upd_value("FspReservedMemoryLength", - sizeof(old->FspReservedMemoryLength), - old->FspReservedMemoryLength, new->FspReservedMemoryLength); - fsp_display_upd_value("RankMask", sizeof(old->RankMask), old->RankMask, - new->RankMask); - fsp_display_upd_value("RmuBaseAddress", sizeof(old->RmuBaseAddress), - old->RmuBaseAddress, new->RmuBaseAddress); - fsp_display_upd_value("RmuLength", sizeof(old->RmuLength), - old->RmuLength, new->RmuLength); - fsp_display_upd_value("SerialPortPollForChar", - sizeof(old->SerialPortPollForChar), - old->SerialPortPollForChar, new->SerialPortPollForChar); - fsp_display_upd_value("SerialPortReadChar", - sizeof(old->SerialPortReadChar), - old->SerialPortReadChar, new->SerialPortReadChar); - fsp_display_upd_value("SerialPortWriteChar", - sizeof(old->SerialPortWriteChar), - old->SerialPortWriteChar, new->SerialPortWriteChar); - fsp_display_upd_value("SmmTsegSize", sizeof(old->SmmTsegSize), - old->SmmTsegSize, new->SmmTsegSize); - fsp_display_upd_value("SocRdOdtVal", sizeof(old->SocRdOdtVal), - old->SocRdOdtVal, new->SocRdOdtVal); - fsp_display_upd_value("SocWrRonVal", sizeof(old->SocWrRonVal), - old->SocWrRonVal, new->SocWrRonVal); - fsp_display_upd_value("SocWrSlewRate", sizeof(old->SocWrSlewRate), - old->SocWrSlewRate, new->SocWrSlewRate); - fsp_display_upd_value("SrInt", sizeof(old->SrInt), old->SrInt, - new->SrInt); - fsp_display_upd_value("SrTemp", sizeof(old->SrTemp), old->SrTemp, - new->SrTemp); - fsp_display_upd_value("tCL", sizeof(old->tCL), old->tCL, new->tCL); - fsp_display_upd_value("tFAW", sizeof(old->tFAW), old->tFAW, new->tFAW); - fsp_display_upd_value("tRAS", sizeof(old->tRAS), old->tRAS, new->tRAS); - fsp_display_upd_value("tRRD", sizeof(old->tRRD), old->tRRD, new->tRRD); - fsp_display_upd_value("tWTR", sizeof(old->tWTR), old->tWTR, new->tWTR); -} - -void soc_after_ram_init(struct romstage_params *params) -{ - /* Disable the ROM shadow 0x000e0000 - 0x000fffff */ - disable_rom_shadow(); - - /* Initialize the PCIe bridges */ - pcie_init(); -} diff --git a/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h b/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h deleted file mode 100644 index 743e4ee..0000000 --- a/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h +++ /dev/null @@ -1,245 +0,0 @@ -/** @file - -Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPUPDVPD_H__ -#define __FSPUPDVPD_H__ - -#pragma pack(1) - - -#define MAX_CHANNELS_NUM 1 -#define MAX_DIMMS_NUM 1 - -typedef struct { - UINT8 DimmId; - UINT32 SizeInMb; - UINT16 MfgId; - /** Module part number for DDR3 is 18 bytes however for - DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes - **/ - UINT8 ModulePartNum[20]; -} DIMM_INFO; - -typedef struct { - UINT8 ChannelId; - UINT8 DimmCount; - DIMM_INFO DimmInfo[MAX_DIMMS_NUM]; -} CHANNEL_INFO; - -typedef struct { - UINT8 Revision; - UINT16 DataWidth; - /** As defined in SMBIOS 3.0 spec - Section 7.18.2 and Table 75 - **/ - UINT8 MemoryType; - UINT16 MemoryFrequencyInMHz; - /** As defined in SMBIOS 3.0 spec - Section 7.17.3 and Table 72 - **/ - UINT8 ErrorCorrectionType; - UINT8 ChannelCount; - CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM]; -} FSP_SMBIOS_MEMORY_INFO; - - - -typedef struct { -/** Offset 0x0018 -**/ - UINT64 Signature; -/** Offset 0x0020 -**/ - UINT64 Revision; -/** Offset 0x0028 -**/ - UINT32 RmuBaseAddress; -/** Offset 0x002C -**/ - UINT32 RmuLength; -/** Offset 0x0030 -**/ - UINT32 Reserved_30; -/** Offset 0x0034 -**/ - UINT32 tRAS; -/** Offset 0x0038 -**/ - UINT32 tWTR; -/** Offset 0x003C -**/ - UINT32 tRRD; -/** Offset 0x0040 -**/ - UINT32 tFAW; -/** Offset 0x0044 -**/ - UINT32 Flags; -/** Offset 0x0048 -**/ - UINT8 DramWidth; -/** Offset 0x0049 -**/ - UINT8 DramSpeed; -/** Offset 0x004A -**/ - UINT8 DramType; -/** Offset 0x004B -**/ - UINT8 RankMask; -/** Offset 0x004C -**/ - UINT8 ChanMask; -/** Offset 0x004D -**/ - UINT8 ChanWidth; -/** Offset 0x004E -**/ - UINT8 AddrMode; -/** Offset 0x004F -**/ - UINT8 SrInt; -/** Offset 0x0050 -**/ - UINT8 SrTemp; -/** Offset 0x0051 -**/ - UINT8 DramRonVal; -/** Offset 0x0052 -**/ - UINT8 DramRttNomVal; -/** Offset 0x0053 -**/ - UINT8 DramRttWrVal; -/** Offset 0x0054 -**/ - UINT8 SocRdOdtVal; -/** Offset 0x0055 -**/ - UINT8 SocWrRonVal; -/** Offset 0x0056 -**/ - UINT8 SocWrSlewRate; -/** Offset 0x0057 -**/ - UINT8 DramDensity; -/** Offset 0x0058 -**/ - UINT8 tCL; -/** Offset 0x0059 -**/ - UINT8 EccScrubInterval; -/** Offset 0x005A -**/ - UINT8 EccScrubBlkSize; -/** Offset 0x005B -**/ - UINT8 SmmTsegSize; -/** Offset 0x005C -**/ - UINT32 FspReservedMemoryLength; -/** Offset 0x0060 -**/ - UINT32 MrcDataPtr; -/** Offset 0x0064 -**/ - UINT32 MrcDataLength; -/** Offset 0x0068 -**/ - UINT32 SerialPortPollForChar; -/** Offset 0x006C -**/ - UINT32 SerialPortReadChar; -/** Offset 0x0070 -**/ - UINT32 SerialPortWriteChar; -/** Offset 0x0074 -**/ - UINT8 ReservedMemoryInitUpd[12]; -} MEMORY_INIT_UPD; - -typedef struct { -/** Offset 0x0080 -**/ - UINT64 Signature; -/** Offset 0x0088 -**/ - UINT64 Revision; -/** Offset 0x0090 -**/ - UINT16 PcdRegionTerminator; -} SILICON_INIT_UPD; - -#define FSP_UPD_SIGNATURE 0x244450554B525124 /* '$QRKUPD$' */ -#define FSP_MEMORY_INIT_UPD_SIGNATURE 0x244450554D454D24 /* '$MEMUPD$' */ -#define FSP_SILICON_INIT_UPD_SIGNATURE 0x244450555F495324 /* '$SI_UPD$' */ - -typedef struct _UPD_DATA_REGION { -/** Offset 0x0000 -**/ - UINT64 Signature; -/** Offset 0x0008 -**/ - UINT64 Revision; -/** Offset 0x0010 -**/ - UINT32 MemoryInitUpdOffset; -/** Offset 0x0014 -**/ - UINT32 SiliconInitUpdOffset; -/** Offset 0x0018 -**/ - MEMORY_INIT_UPD MemoryInitUpd; -/** Offset 0x0080 -**/ - SILICON_INIT_UPD SiliconInitUpd; -} UPD_DATA_REGION; - -#define FSP_IMAGE_ID 0x305053462D4B5551 /* 'QUK-FSP0' */ -#define FSP_IMAGE_REV 0x00000000 - -typedef struct _VPD_DATA_REGION { -/** Offset 0x0000 -**/ - UINT64 PcdVpdRegionSign; -/** Offset 0x0008 - PcdImageRevision -**/ - UINT32 PcdImageRevision; -/** Offset 0x000C -**/ - UINT32 PcdUpdRegionOffset; -} VPD_DATA_REGION; - -#pragma pack() - -#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/30946 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5297e87c7a7422e1a129a2d8687fc86a5015a77 Gerrit-Change-Number: 30946 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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coreboot-gerrit January 2019