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Change in ...coreboot[master]: inteltool: Add multiple device IDs of Intel GPUs
by Felix Singer (Code Review) 06 Mar '19

06 Mar '19

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30610 Change subject: inteltool: Add multiple device IDs of Intel GPUs ...................................................................... inteltool: Add multiple device IDs of Intel GPUs * Intel UHD Graphics 615 * Intel UHD Graphics 620 (2x) * Intel UHD Graphics 630 (2x) * Intel Iris Graphics 655 Change-Id: I299a5fc082433b0aab4861a24aecbe83b61a404a Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> --- M util/inteltool/inteltool.c M util/inteltool/inteltool.h 2 files changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/30610/1 diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 9a58ed8..bace49e 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -347,6 +347,18 @@ "Intel(R) HD 5000 Graphics" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HD_5000_2, "Intel(R) HD 5000 Graphics" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UHD_615, + "Intel(R) UHD Graphics 615" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UHD_620_1, + "Intel(R) UHD Graphics 620" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UHD_620_2, + "Intel(R) UHD Graphics 620" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UHD_630_1, + "Intel(R) UHD Graphics 630" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UHD_630_2, + "Intel(R) UHD Graphics 630" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IRIS_PLUS_655, + "Intel(R) Iris Plus Graphics 655" }, }; #ifndef __DARWIN__ diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index d86ba35..8a36333 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -301,6 +301,15 @@ #define PCI_DEVICE_ID_INTEL_HD_5000 0x0422 #define PCI_DEVICE_ID_INTEL_HD_5000_1 0x0426 #define PCI_DEVICE_ID_INTEL_HD_5000_2 0x042A +#define PCI_DEVICE_ID_INTEL_UHD_615 0x591C +#define PCI_DEVICE_ID_INTEL_UHD_620_1 0x5917 +#define PCI_DEVICE_ID_INTEL_UHD_620_2 0x3EA0 +#define PCI_DEVICE_ID_INTEL_UHD_630_1 0x3E92 +#define PCI_DEVICE_ID_INTEL_UHD_630_2 0x3E9B +#define PCI_DEVICE_ID_INTEL_IRIS_PLUS_655 0x3EA5 + + + #if !defined(__DARWIN__) && !defined(__FreeBSD__) typedef struct { uint32_t hi, lo; } msr_t; -- To view, visit https://review.coreboot.org/c/coreboot/+/30610 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I299a5fc082433b0aab4861a24aecbe83b61a404a Gerrit-Change-Number: 30610 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-MessageType: newchange

4 8

Change in ...coreboot[master]: mb/qemu-{i440fx,q35}: Use POSTCAR stage to load the ramstage
by Patrick Rudolph (Code Review) 05 Mar '19

05 Mar '19

Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30499 to review the following change. Change subject: mb/qemu-{i440fx,q35}: Use POSTCAR stage to load the ramstage ...................................................................... mb/qemu-{i440fx,q35}: Use POSTCAR stage to load the ramstage Qemu does not have a real CAR but postcar stage is still useful to setup pagetables for x86_64 ramstage. Change-Id: I6638534d99fde312e55b6a6be8c95e4cb25cca80 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/lib/Makefile.inc M src/mainboard/emulation/qemu-i440fx/Kconfig M src/mainboard/emulation/qemu-i440fx/Makefile.inc A src/mainboard/emulation/qemu-i440fx/exit_car.S M src/mainboard/emulation/qemu-i440fx/romstage.c M src/mainboard/emulation/qemu-q35/Kconfig M src/mainboard/emulation/qemu-q35/Makefile.inc M src/mainboard/emulation/qemu-q35/romstage.c 8 files changed, 75 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/30499/1 diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 2fd4e4c..48dc664 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -132,6 +132,7 @@ ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c ramstage-$(CONFIG_TRACE) += trace.c +postcar-$(CONFIG_TRACE) += trace.c ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c ramstage-$(CONFIG_COVERAGE) += libgcov.c ramstage-y += edid.c diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index eb9f011..3a507d3 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -14,6 +14,8 @@ select MAINBOARD_FORCE_NATIVE_VGA_INIT select BOOTBLOCK_CONSOLE select NO_CAR_GLOBAL_MIGRATION + select POSTCAR_STAGE + select POSTCAR_CONSOLE config MAINBOARD_DIR string diff --git a/src/mainboard/emulation/qemu-i440fx/Makefile.inc b/src/mainboard/emulation/qemu-i440fx/Makefile.inc index 9e2880a..de790e6 100644 --- a/src/mainboard/emulation/qemu-i440fx/Makefile.inc +++ b/src/mainboard/emulation/qemu-i440fx/Makefile.inc @@ -2,3 +2,5 @@ ramstage-y += fw_cfg.c romstage-y += memory.c ramstage-y += memory.c +postcar-y += memory.c +postcar-y += exit_car.S diff --git a/src/mainboard/emulation/qemu-i440fx/exit_car.S b/src/mainboard/emulation/qemu-i440fx/exit_car.S new file mode 100644 index 0000000..74f6ed2 --- /dev/null +++ b/src/mainboard/emulation/qemu-i440fx/exit_car.S @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cr.h> +/* jump directly to the main function, as there is no real CAR to tear down. */ +.text +.global chipset_teardown_car +chipset_teardown_car: + /* Set up new stack. */ + mov post_car_stack_top, %esp + /* Call C code */ + call main diff --git a/src/mainboard/emulation/qemu-i440fx/romstage.c b/src/mainboard/emulation/qemu-i440fx/romstage.c index e31394c..137dfbf 100644 --- a/src/mainboard/emulation/qemu-i440fx/romstage.c +++ b/src/mainboard/emulation/qemu-i440fx/romstage.c @@ -20,14 +20,35 @@ #include <cpu/intel/romstage.h> #include <timestamp.h> #include <program_loading.h> +#include <cpu/x86/mtrr.h> + +#include "memory.h" asmlinkage void car_stage_entry(void) { + struct postcar_frame pcf; + console_init(); cbmem_recovery(0); timestamp_add_now(TS_START_ROMSTAGE); - run_ramstage(); + if (postcar_frame_init(&pcf, 5 * KiB)) + die("Unable to initialize postcar frame.\n"); + + /* Cache the ROM as WP just below 4GiB. */ + postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); + + /* Cache memory below 4 GiB */ + postcar_frame_add_mtrr(&pcf, 0, qemu_get_memory_size() * KiB, + MTRR_TYPE_WRBACK); + + /* Cache memory beyond 4 GiB */ + if (qemu_get_high_memory_size() > 0) + postcar_frame_add_mtrr(&pcf, (4ULL * GiB), + qemu_get_high_memory_size() * KiB, + MTRR_TYPE_WRBACK); + + run_postcar_phase(&pcf); } diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index 1cc7148..07c15f3 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -13,6 +13,8 @@ select MAINBOARD_FORCE_NATIVE_VGA_INIT select BOOTBLOCK_CONSOLE select NO_CAR_GLOBAL_MIGRATION + select POSTCAR_STAGE + select POSTCAR_CONSOLE config MAINBOARD_DIR string diff --git a/src/mainboard/emulation/qemu-q35/Makefile.inc b/src/mainboard/emulation/qemu-q35/Makefile.inc index 1c06d77..a0ac5dd 100644 --- a/src/mainboard/emulation/qemu-q35/Makefile.inc +++ b/src/mainboard/emulation/qemu-q35/Makefile.inc @@ -3,4 +3,6 @@ ramstage-y += ../qemu-i440fx/fw_cfg.c romstage-y += ../qemu-i440fx/memory.c +postcar-y += ../qemu-i440fx/memory.c +postcar-y += ../qemu-i440fx/exit_car.S bootblock-y += bootblock.c diff --git a/src/mainboard/emulation/qemu-q35/romstage.c b/src/mainboard/emulation/qemu-q35/romstage.c index 2b8d935..badafdd 100644 --- a/src/mainboard/emulation/qemu-q35/romstage.c +++ b/src/mainboard/emulation/qemu-q35/romstage.c @@ -21,9 +21,13 @@ #include <timestamp.h> #include <southbridge/intel/i82801ix/i82801ix.h> #include <program_loading.h> +#include <cpu/x86/mtrr.h> + +#include "../qemu-i440fx/memory.h" asmlinkage void car_stage_entry(void) { + struct postcar_frame pcf; i82801ix_early_init(); console_init(); @@ -31,5 +35,21 @@ timestamp_add_now(TS_START_ROMSTAGE); - run_ramstage(); + if (postcar_frame_init(&pcf, 5 * KiB)) + die("Unable to initialize postcar frame.\n"); + + /* Cache the ROM as WP just below 4GiB. */ + postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); + + /* Cache memory below 4 GiB */ + postcar_frame_add_mtrr(&pcf, 0, qemu_get_memory_size() * KiB, + MTRR_TYPE_WRBACK); + + /* Cache memory beyond 4 GiB */ + if (qemu_get_high_memory_size() > 0) + postcar_frame_add_mtrr(&pcf, (4ULL * GiB), + qemu_get_high_memory_size() * KiB, + MTRR_TYPE_WRBACK); + + run_postcar_phase(&pcf); } -- To view, visit https://review.coreboot.org/c/coreboot/+/30499 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6638534d99fde312e55b6a6be8c95e4cb25cca80 Gerrit-Change-Number: 30499 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 16

Change in ...coreboot[master]: mainboard/hp: Add HP Elitebook 8760w as a variant of 8460p
by Iru Cai (vimacs) (Code Review) 04 Mar '19

04 Mar '19

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30936 to review the following change. Change subject: mainboard/hp: Add HP Elitebook 8760w as a variant of 8460p ...................................................................... mainboard/hp: Add HP Elitebook 8760w as a variant of 8460p Tested: - i7-2630QM, 4G - boots Arch Linux on USB drive from SeaBIOS payload with VGA option ROM added Issues: - it takes longer time to boot, and the fan is noisier in the boot process Change-Id: Icd49f5c9e17cf8f5ef8c73e73bea111188427590 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- M src/mainboard/hp/8460p/Kconfig M src/mainboard/hp/8460p/Kconfig.name M src/mainboard/hp/8460p/Makefile.inc M src/mainboard/hp/8460p/romstage.c R src/mainboard/hp/8460p/variants/8460p/devicetree.cb R src/mainboard/hp/8460p/variants/8460p/gpio.c A src/mainboard/hp/8460p/variants/8460p/romstage.c A src/mainboard/hp/8460p/variants/8760w/board_info.txt A src/mainboard/hp/8460p/variants/8760w/devicetree.cb A src/mainboard/hp/8460p/variants/8760w/gpio.c A src/mainboard/hp/8460p/variants/8760w/romstage.c 11 files changed, 495 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/30936/1 diff --git a/src/mainboard/hp/8460p/Kconfig b/src/mainboard/hp/8460p/Kconfig index 57e6268..5f0d827 100644 --- a/src/mainboard/hp/8460p/Kconfig +++ b/src/mainboard/hp/8460p/Kconfig @@ -13,45 +13,57 @@ # GNU General Public License for more details. # -if BOARD_HP_8460P - -config BOARD_SPECIFIC_OPTIONS - def_bool y +config BOARD_HP_BASEBOARD_8460P + def_bool n select BOARD_ROMSIZE_KB_8192 select CPU_INTEL_SOCKET_RPGA989 select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_INT15 select NORTHBRIDGE_INTEL_SANDYBRIDGE - select SANDYBRIDGE_IVYBRIDGE_LVDS + select SANDYBRIDGE_IVYBRIDGE_LVDS if !BOARD_HP_8760W select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_BD82X6X select SYSTEM_TYPE_LAPTOP select USE_NATIVE_RAMINIT - select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_LIBGFXINIT if !BOARD_HP_8760W select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 - select GFX_GMA_INTERNAL_IS_LVDS + select GFX_GMA_INTERNAL_IS_LVDS if !BOARD_HP_8760W select EC_HP_KBC1126 select SUPERIO_SMSC_LPC47N217 select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT +if BOARD_HP_BASEBOARD_8460P + +config VARIANT_DIR + string + default "8460p" if BOARD_HP_8460P + default "8760w" if BOARD_HP_8760W + config MAINBOARD_DIR string default hp/8460p +config DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + config MAINBOARD_PART_NUMBER string - default "EliteBook 8460p" + default "EliteBook 8460p" if BOARD_HP_8460P + default "EliteBook 8760w" if BOARD_HP_8760W config VGA_BIOS_FILE string - default "pci8086,0116.rom" + default "pci8086,0116.rom" if BOARD_HP_8460P + default "pci10de,0e3a.rom" if BOARD_HP_8760W config VGA_BIOS_ID string - default "8086,0116" + default "8086,0116" if BOARD_HP_8460P + default "10de,0e3a" if BOARD_HP_8760W config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID hex diff --git a/src/mainboard/hp/8460p/Kconfig.name b/src/mainboard/hp/8460p/Kconfig.name index 94f2fe9..8d48d43 100644 --- a/src/mainboard/hp/8460p/Kconfig.name +++ b/src/mainboard/hp/8460p/Kconfig.name @@ -1,2 +1,7 @@ config BOARD_HP_8460P bool "EliteBook 8460p" + select BOARD_HP_BASEBOARD_8460P + +config BOARD_HP_8760W + bool "EliteBook 8760w" + select BOARD_HP_BASEBOARD_8460P diff --git a/src/mainboard/hp/8460p/Makefile.inc b/src/mainboard/hp/8460p/Makefile.inc index 7a00cce..5819ac0 100644 --- a/src/mainboard/hp/8460p/Makefile.inc +++ b/src/mainboard/hp/8460p/Makefile.inc @@ -13,6 +13,7 @@ ## GNU General Public License for more details. ## -romstage-y += gpio.c +romstage-y += variants/$(VARIANT_DIR)/gpio.c +romstage-y += variants/$(VARIANT_DIR)/romstage.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/hp/8460p/romstage.c b/src/mainboard/hp/8460p/romstage.c index b97d5e4..899ffab 100644 --- a/src/mainboard/hp/8460p/romstage.c +++ b/src/mainboard/hp/8460p/romstage.c @@ -42,23 +42,6 @@ { } -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 1, 0 }, /* USB0, eSATA */ - { 1, 0, 0 }, /* USB charger */ - { 0, 1, 1 }, - { 1, 1, 1 }, /* camera */ - { 1, 0, 2 }, /* USB4 expresscard */ - { 1, 0, 2 }, /* bluetooth */ - { 0, 0, 3 }, - { 1, 0, 3 }, /* smartcard */ - { 1, 1, 4 }, /* fingerprint */ - { 1, 1, 4 }, /* WWAN */ - { 1, 0, 5 }, /* CONN */ - { 1, 0, 5 }, /* docking */ - { 1, 0, 6 }, /* CONN */ - { 1, 0, 6 }, /* docking */ -}; - void mainboard_early_init(int s3resume) { } @@ -73,9 +56,3 @@ kbc1126_pm1_init(); kbc1126_exit_conf(); } - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x52, id_only); -} diff --git a/src/mainboard/hp/8460p/devicetree.cb b/src/mainboard/hp/8460p/variants/8460p/devicetree.cb similarity index 100% rename from src/mainboard/hp/8460p/devicetree.cb rename to src/mainboard/hp/8460p/variants/8460p/devicetree.cb diff --git a/src/mainboard/hp/8460p/gpio.c b/src/mainboard/hp/8460p/variants/8460p/gpio.c similarity index 100% rename from src/mainboard/hp/8460p/gpio.c rename to src/mainboard/hp/8460p/variants/8460p/gpio.c diff --git a/src/mainboard/hp/8460p/variants/8460p/romstage.c b/src/mainboard/hp/8460p/variants/8460p/romstage.c new file mode 100644 index 0000000..2221046 --- /dev/null +++ b/src/mainboard/hp/8460p/variants/8460p/romstage.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Iru Cai <mytbk920423(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, /* USB0, eSATA */ + { 1, 0, 0 }, /* USB charger */ + { 0, 1, 1 }, + { 1, 1, 1 }, /* camera */ + { 1, 0, 2 }, /* USB4 expresscard */ + { 1, 0, 2 }, /* bluetooth */ + { 0, 0, 3 }, + { 1, 0, 3 }, /* smartcard */ + { 1, 1, 4 }, /* fingerprint */ + { 1, 1, 4 }, /* WWAN */ + { 1, 0, 5 }, /* CONN */ + { 1, 0, 5 }, /* docking */ + { 1, 0, 6 }, /* CONN */ + { 1, 0, 6 }, /* docking */ +}; + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x52, id_only); +} diff --git a/src/mainboard/hp/8460p/variants/8760w/board_info.txt b/src/mainboard/hp/8460p/variants/8760w/board_info.txt new file mode 100644 index 0000000..887ec7b --- /dev/null +++ b/src/mainboard/hp/8460p/variants/8760w/board_info.txt @@ -0,0 +1,7 @@ +Category: laptop +Board URL: https://support.hp.com/us-en/product/hp-elitebook-8760w-mobile-workstation/… +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n +Release year: 2011 diff --git a/src/mainboard/hp/8460p/variants/8760w/devicetree.cb b/src/mainboard/hp/8460p/variants/8760w/devicetree.cb new file mode 100644 index 0000000..7d4ba42 --- /dev/null +++ b/src/mainboard/hp/8460p/variants/8760w/devicetree.cb @@ -0,0 +1,139 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2019 Iru Cai <mytbk920423(a)gmail.com> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +chip northbridge/intel/sandybridge + device cpu_cluster 0x0 on + chip cpu/intel/socket_rPGA989 + device lapic 0x0 on + end + end + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0xacac off + end + end + end + device domain 0x0 on + device pci 00.0 on # Host bridge + subsystemid 0x103c 0x1630 + end + device pci 01.0 on # PCIe Bridge for discrete graphics + subsystemid 0x8086 0x2010 + end + device pci 02.0 off # Internal graphics + end + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x007c0201" + register "gen2_dec" = "0x000c0101" + register "gen3_dec" = "0x00fcfe01" + register "gen4_dec" = "0x000402e9" + register "p_cnt_throttling_supported" = "1" + register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + # HDD(0, 1), ODD(2), eSATA(4) + register "sata_port_map" = "0x3f" + register "spi_uvscc" = "0x2005" + register "spi_lvscc" = "0" + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x103c 0x1630 + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x103c 0x1630 + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x103c 0x1630 + end + device pci 1b.0 on # High Definition Audio Audio controller + subsystemid 0x103c 0x1630 + end + device pci 1c.0 on # PCIe Port #1, WWAN + subsystemid 0x103c 0x1630 + end + device pci 1c.1 on # PCIe Port #2 + subsystemid 0x103c 0x1630 + end + device pci 1c.2 on # PCIe Port #3, SD/MMC + subsystemid 0x103c 0x1630 + end + device pci 1c.3 on # PCIe Port #4, WLAN + subsystemid 0x103c 0x1630 + end + device pci 1c.4 off # PCIe Port #5 + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 on # PCIe Port #8, NEC USB 3.0 Host Controller + subsystemid 0x103c 0x1630 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x103c 0x1630 + end + device pci 1e.0 off # PCI bridge + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x103c 0x1630 + chip ec/hp/kbc1126 + register "ec_data_port" = "0x60" + register "ec_cmd_port" = "0x64" + register "ec_ctrl_reg" = "0xca" + register "ec_fan_ctrl_value" = "0x9a" + device pnp ff.1 off end + end # kbc1126 + chip superio/smsc/lpc47n217 + device pnp 4e.3 on # Parallel + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 4e.4 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.5 off # Com2 + end + end #chip superio/smsc/lpc47n217 + + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x103c 0x1630 + end + device pci 1f.3 off # SMBus + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + end +end diff --git a/src/mainboard/hp/8460p/variants/8760w/gpio.c b/src/mainboard/hp/8460p/variants/8760w/gpio.c new file mode 100644 index 0000000..bed7996 --- /dev/null +++ b/src/mainboard/hp/8460p/variants/8760w/gpio.c @@ -0,0 +1,236 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Iru Cai <mytbk920423(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_OUTPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, + .gpio11 = GPIO_LEVEL_LOW, + .gpio17 = GPIO_LEVEL_HIGH, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, + .gpio30 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio3 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio10 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio37 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_OUTPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio61 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_OUTPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_OUTPUT, + .gpio72 = GPIO_DIR_OUTPUT, + .gpio73 = GPIO_DIR_OUTPUT, + .gpio74 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio68 = GPIO_LEVEL_HIGH, + .gpio70 = GPIO_LEVEL_HIGH, + .gpio72 = GPIO_LEVEL_LOW, + .gpio73 = GPIO_LEVEL_HIGH, + .gpio74 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/hp/8460p/variants/8760w/romstage.c b/src/mainboard/hp/8460p/variants/8760w/romstage.c new file mode 100644 index 0000000..7648c12 --- /dev/null +++ b/src/mainboard/hp/8460p/variants/8760w/romstage.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Iru Cai <mytbk920423(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, /* USB charger */ + { 1, 1, 0 }, /* CONN */ + { 1, 1, 1 }, /* eSATA */ + { 1, 1, 1 }, /* camera */ + { 1, 0, 2 }, + { 1, 0, 2 }, /* bluetooth */ + { 0, 0, 3 }, + { 1, 0, 3 }, + { 1, 1, 4 }, /* fingerprint */ + { 1, 1, 4 }, /* WWAN */ + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 }, + { 1, 0, 6 }, +}; + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/30936 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd49f5c9e17cf8f5ef8c73e73bea111188427590 Gerrit-Change-Number: 30936 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-MessageType: newchange

3 8

Change in ...coreboot[master]: Revert "mb/google/sarien: Update GPIOs for next build"
by Lijian Zhao (Code Review) 02 Mar '19

02 Mar '19

Hello Duncan Laurie, build bot (Jenkins), Patrick Georgi, Furquan Shaikh, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30940 to review the following change. Change subject: Revert "mb/google/sarien: Update GPIOs for next build" ...................................................................... Revert "mb/google/sarien: Update GPIOs for next build" This reverts commit 025a03f6164b4f24e36aea39688b39abdec28fee. Reason for revert: <INSERT REASONING HERE> Change-Id: Ie0932da238dfacf61c507f042e72ad8452ab1bfe --- M src/mainboard/google/sarien/variants/arcada/gpio.c M src/mainboard/google/sarien/variants/sarien/gpio.c 2 files changed, 27 insertions(+), 40 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/30940/1 diff --git a/src/mainboard/google/sarien/variants/arcada/gpio.c b/src/mainboard/google/sarien/variants/arcada/gpio.c index a29fd06..0ffd029 100644 --- a/src/mainboard/google/sarien/variants/arcada/gpio.c +++ b/src/mainboard/google/sarien/variants/arcada/gpio.c @@ -30,23 +30,18 @@ /* ESPI_CLK */ /* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE), /* PME# */ PAD_NC(GPP_A11, NONE), - /* ISH_LID_CL#_TAB */ -/* BM_BUSY# */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), +/* BM_BUSY# */ PAD_NC(GPP_A12, NONE), /* SUSWARN# */ PAD_NC(GPP_A13, NONE), /* ESPI_RESET# */ /* SUSACK# */ PAD_NC(GPP_A15, NONE), /* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), /* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE), - /* ISH_ACC1_INT# */ -/* ISH_GP0 */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), - /* ISH_ACC2_INT# */ -/* ISH_GP1 */ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), +/* ISH_GP0 */ PAD_NC(GPP_A18, NONE), +/* ISH_GP1 */ PAD_NC(GPP_A19, NONE), /* ISH_GP2 */ PAD_NC(GPP_A20, NONE), /* ISH_GP3 */ PAD_NC(GPP_A21, NONE), - /* ISH_NB_MODE */ -/* ISH_GP4 */ PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1), - /* ISH_LID_CL#_NB */ -/* ISH_GP5 */ PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), +/* ISH_GP4 */ PAD_NC(GPP_A22, NONE), +/* ISH_GP5 */ PAD_NC(GPP_A23, NONE), /* CORE_VID0 */ /* CORE_VID1 */ @@ -54,17 +49,12 @@ /* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, EDGE_SINGLE, INVERT), /* TOUCHPAD_INTR# */ /* CPU_GP3 */ PAD_CFG_GPI(GPP_B4, NONE, DEEP), /* TOUCH_SCREEN_DET# */ - /* LAN_CLKREQ_CPU_N */ /* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), - /* CARD_CLKREQ_CPU_N */ /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), - /* WLAN_CLKREQ_CPU_N */ /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), - /* WWAN_CLKREQ_CPU_N */ /* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), - /* SSD_CKLREQ_CPU_N */ /* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), -/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), /* TBT_CLKREQ_CPU_N (nostuff) */ +/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), /* EXT_PWR_GATE# */ PAD_CFG_GPO(GPP_B11, 0, DEEP), /* 3.3V_CAM_EN# */ /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), @@ -73,7 +63,7 @@ /* GSPI0_CLK */ PAD_CFG_GPI(GPP_B16, NONE, DEEP), /* ONE_DIMM# */ /* GSPI0_MISO */ PAD_CFG_GPI(GPP_B17, NONE, DEEP), /* RTC_DET# */ /* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), -/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* HDD_FALL_INT (nostuff) */ +/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), /* TPM_PIRQ# (nostuff) */ /* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */ /* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), @@ -122,10 +112,8 @@ /* ISH_SPI_CLK */ PAD_NC(GPP_D10, NONE), /* ISH_SPI_MISO */ PAD_CFG_GPI(GPP_D11, NONE, DEEP), /* TBT_DET# */ /* ISH_SPI_MOSI */ PAD_NC(GPP_D12, NONE), - /* ISH_CPU_UART0_RX */ -/* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), - /* ISH_CPU_UART0_TX */ -/* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), +/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE), +/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), /* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 1, DEEP), /* WWAN_FULL_PWR_EN */ /* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE), /* DMIC_CLK1 */ PAD_CFG_GPI(GPP_D17, NONE, DEEP), /* KB_DET# */ @@ -156,10 +144,10 @@ /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DP_HPD_CPU */ /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DP2_HPD_CPU */ /* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* PCH_WP */ -/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), /* FFS_INT2 (nostuff) */ +/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), -/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* HDMI_SCL_CPU */ -/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* HDMI_SDA_CPU */ +/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE), /* DDPC_CTRLDATA */ PAD_NC(GPP_E21, NONE), /* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), @@ -191,9 +179,9 @@ /* A4WP_PRESENT */ PAD_NC(GPP_F23, NONE), /* SD_CMD */ PAD_CFG_GPI(GPP_G0, NONE, DEEP), /* CAM_MIC_CBL_DET# */ -/* SD_DATA0 */ PAD_NC(GPP_G1, NONE), /* ANT_CONFIG (nostuff) */ +/* SD_DATA0 */ PAD_NC(GPP_G1, NONE), /* SD_DATA1 */ PAD_NC(GPP_G2, NONE), /* TBT_CIO_PLUG_EVT# (nostuff) */ -/* SD_DATA2 */ PAD_NC(GPP_G3, NONE), +/* SD_DATA2 */ PAD_NC(GPP_G3, NONE), /* T383 */ /* SD_DATA3 */ PAD_CFG_GPI(GPP_G4, NONE, DEEP), /* CTLESS_DET# */ /* SD_CD# */ PAD_CFG_GPO(GPP_G5, 1, DEEP), /* HOST_SD_WP# */ /* SD_CLK */ PAD_CFG_GPO(GPP_G6, 1, DEEP), /* AUD_PWR_EN */ diff --git a/src/mainboard/google/sarien/variants/sarien/gpio.c b/src/mainboard/google/sarien/variants/sarien/gpio.c index 38d21c8..a41d940 100644 --- a/src/mainboard/google/sarien/variants/sarien/gpio.c +++ b/src/mainboard/google/sarien/variants/sarien/gpio.c @@ -49,11 +49,11 @@ /* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, EDGE_SINGLE, INVERT), /* TOUCHPAD_INTR# */ /* CPU_GP3 */ PAD_CFG_GPI(GPP_B4, NONE, DEEP), /* TOUCH_SCREEN_DET# */ -/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* CLKREQ_PCIE#0 */ -/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* CLKREQ_PCIE#1 */ -/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* CLKREQ_PCIE#2 */ -/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* CLKREQ_PCIE#3 */ -/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* CLKREQ_PCIE#4 */ +/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), +/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), +/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), +/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), +/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), /* EXT_PWR_GATE# */ PAD_CFG_GPO(GPP_B11, 0, DEEP), /* 3.3V_CAM_EN# */ /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), @@ -63,7 +63,8 @@ /* GSPI0_CLK */ PAD_NC(GPP_B16, NONE), /* GSPI0_MISO */ PAD_NC(GPP_B17, NONE), /* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), -/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* HDD_FALL_INT (nostuff) */ +/* GSPI1_CS# */ PAD_CFG_GPI_APIC(GPP_B19, NONE, PLTRST, + EDGE_SINGLE, INVERT), /* HDD_FALL_INT */ /* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), /* TPM_PIRQ# (nostuff) */ /* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */ /* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), @@ -100,7 +101,7 @@ EDGE_SINGLE, INVERT), /* MEDIACARD_IRQ# */ /* SPI1_CLK */ PAD_NC(GPP_D1, NONE), /* SPI1_MISO */ PAD_NC(GPP_D2, NONE), -/* SPI1_MOSI */ PAD_CFG_GPI(GPP_D3, NONE, DEEP), /* RTC_DET# */ +/* SPI1_MOSI */ PAD_NC(GPP_D3, NONE), /* FASHTRIG */ PAD_NC(GPP_D4, NONE), /* ISH_I2C0_SDA */ PAD_NC(GPP_D5, NONE), /* ISH_I2C0_SCL */ PAD_NC(GPP_D6, NONE), @@ -134,7 +135,7 @@ /* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* M3042_DEVSLP */ /* SATA_DEVSLP2 */ PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), /* M2280_DEVSLP */ /* CPU_GP1 */ PAD_CFG_GPO(GPP_E7, 1, DEEP), /* TOUCH_SCREEN_PD# */ -/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */ +/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY */ /* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_OC0# */ /* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB_OC1# */ /* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USB_OC2# */ @@ -142,7 +143,8 @@ /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* HDMI_DP1_HPD */ /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* CPU_DP2_HPD */ /* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* H1_FLASH_WP */ -/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), /* FFS_INT2 (nostuff) */ +/* DDPE_HPD3 */ PAD_CFG_GPI_APIC(GPP_E16, NONE, PLTRST, + EDGE_SINGLE, INVERT), /* FFS_INT2 */ /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), @@ -235,7 +237,7 @@ /* RESET# need to stay low before FULL_CARD_POWER_OFF assert */ /* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 0, DEEP), /* WWAN_BB_RST# */ /* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */ -/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */ +/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY */ /* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* H1_FLASH_WP */ }; @@ -252,10 +254,7 @@ } static const struct cros_gpio cros_gpios[] = { - /* - * TODO: re-enable recovery mode when boards are updated: - * CROS_GPIO_REC_AL(GPP_E8, CROS_GPIO_DEVICE_NAME), - */ + CROS_GPIO_REC_AH(GPP_E8, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPP_E15, CROS_GPIO_DEVICE_NAME), }; -- To view, visit https://review.coreboot.org/c/coreboot/+/30940 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0932da238dfacf61c507f042e72ad8452ab1bfe Gerrit-Change-Number: 30940 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/sarien: Set CPU boot up mode to turbo
by Lijian Zhao (Code Review) 01 Mar '19

01 Mar '19

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30446 Change subject: mb/google/sarien: Set CPU boot up mode to turbo ...................................................................... mb/google/sarien: Set CPU boot up mode to turbo Set CPU to be running at non-turbo maxium speed first and then switch to turbo maxium speed to accelerate boot performance. BUG=N/A TEST=Boot up with sarien platform, check with cbmem -t, boot time had been 110ms less. Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: I43bdb7ef82a5e6e147b3b506756c118dacdb0321 --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/30446/1 diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 52840de..ce83d10 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -24,6 +24,7 @@ register "SkipExtGfxScan" = "1" register "VmxEnable" = "1" + register "bootfreq" = "2" register "speed_shift_enable" = "1" register "s0ix_enable" = "1" register "dptf_enable" = "1" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 47abadc..98566f1 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -28,6 +28,7 @@ register "SkipExtGfxScan" = "1" register "VmxEnable" = "1" + register "bootfreq" = "2" register "speed_shift_enable" = "1" register "s0ix_enable" = "1" register "dptf_enable" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/30446 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43bdb7ef82a5e6e147b3b506756c118dacdb0321 Gerrit-Change-Number: 30446 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: Add option for boot frquency
by Lijian Zhao (Code Review) 01 Mar '19

01 Mar '19

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30445 Change subject: soc/intel/cannonlake: Add option for boot frquency ...................................................................... soc/intel/cannonlake: Add option for boot frquency Cannonlake/Coffeelake FSP have options for CPU boot up frequency selection, expose that in coreboot side. Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: I6bd5849122c9035bb7f448acf08e258e8c207013 --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/romstage/fsp_params.c 2 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/30445/1 diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 3a723d2..7e50a73 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -110,6 +110,11 @@ SaGv_Enabled, } SaGv; + /* Boot Frequency from reset vector. + * 0: Maximum battery performance, 1: Maximum non-turbo performance, 2: + * Maximum turbo performance @note If 2 is selected, system will start + * with non-turbo mode and then switch to turbo. */ + uint8_t bootfreq; /* Rank Margin Tool. 1:Enable, 0:Disable */ uint8_t RMT; diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index c3a2509..0514844 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -54,6 +54,8 @@ #if IS_ENABLED(CONFIG_SOC_INTEL_COFFEELAKE) m_cfg->SkipMpInit = !chip_get_fsp_mp_init(); #endif + m_cfg->BootFrequency = config->bootfreq; + /* If ISH is enabled, enable ISH elements */ if (!dev) m_cfg->PchIshEnable = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/30445 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6bd5849122c9035bb7f448acf08e258e8c207013 Gerrit-Change-Number: 30445 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/mb/sifive/hifive-unleashed: replace fdt in maskrom
by Xiang Wang (Code Review) 28 Feb '19

28 Feb '19

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31047 Change subject: src/mb/sifive/hifive-unleashed: replace fdt in maskrom ...................................................................... src/mb/sifive/hifive-unleashed: replace fdt in maskrom The fdt in the maskrom cannot be used to start linux. The correct fdt is dumped by replacing the bbl of the original firmware and used in coreboot. Correct the mac address in fdt by reading otp Change-Id: Ic29f0e590311360b85fafd12ebc36cd189fbbc38 Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/Makefile.inc A src/arch/riscv/fdt.c A src/arch/riscv/include/fdt.h M src/commonlib/include/commonlib/cbmem_id.h M src/mainboard/sifive/hifive-unleashed/Makefile.inc A src/mainboard/sifive/hifive-unleashed/hifive-unleashed.dts M src/mainboard/sifive/hifive-unleashed/romstage.c 7 files changed, 1,054 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/31047/1 diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index aee4b3b..a27b3e8 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -57,6 +57,7 @@ bootblock-y += smp.c bootblock-y += misc.c bootblock-y += pmp.c +bootblock-y += fdt.c bootblock-y += \ $(top)/src/lib/memchr.c \ $(top)/src/lib/memcmp.c \ @@ -87,6 +88,7 @@ romstage-y += misc.c romstage-y += pmp.c romstage-y += smp.c +romstage-y += fdt.c romstage-y += \ $(top)/src/lib/memchr.c \ $(top)/src/lib/memcmp.c \ @@ -128,6 +130,7 @@ ramstage-y += tables.c ramstage-y += payload.S ramstage-y += pmp.c +ramstage-y += fdt.c ramstage-y += \ $(top)/src/lib/memchr.c \ $(top)/src/lib/memcmp.c \ diff --git a/src/arch/riscv/fdt.c b/src/arch/riscv/fdt.c new file mode 100644 index 0000000..a3815b6 --- /dev/null +++ b/src/arch/riscv/fdt.c @@ -0,0 +1,276 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 SiFive, Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include "fdt.h" + +static inline uint32_t bswap(uint32_t x) +{ + uint32_t y = (x & 0x00FF00FF) << 8 | (x & 0xFF00FF00) >> 8; + uint32_t z = (y & 0x0000FFFF) << 16 | (y & 0xFFFF0000) >> 16; + return z; +} + +static inline int isstring(char c) +{ + if (c >= 'A' && c <= 'Z') + return 1; + if (c >= 'a' && c <= 'z') + return 1; + if (c >= '0' && c <= '9') + return 1; + if (c == '\0' || c == ' ' || c == ',' || c == '-') + return 1; + return 0; +} + +static uint32_t *fdt_scan_helper( + uint32_t *lex, + const char *strings, + struct fdt_scan_node *node, + const struct fdt_cb *cb) +{ + struct fdt_scan_node child; + struct fdt_scan_prop prop; + int last = 0; + + child.parent = node; + // these are the default cell counts, as per the FDT spec + child.address_cells = 2; + child.size_cells = 1; + prop.node = node; + + while (1) { + switch (bswap(lex[0])) { + case FDT_NOP: { + lex += 1; + break; + } + case FDT_PROP: { + // assert (!last); + prop.name = strings + bswap(lex[2]); + prop.len = bswap(lex[1]); + prop.value = lex + 3; + if (node && !strcmp(prop.name, "#address-cells")) + node->address_cells = bswap(lex[3]); + if (node && !strcmp(prop.name, "#size-cells")) + node->size_cells = bswap(lex[3]); + lex += 3 + (prop.len+3)/4; + cb->prop(&prop, cb->extra); + break; + } + case FDT_BEGIN_NODE: { + uint32_t *lex_next; + if (!last && node && cb->done) + cb->done(node, cb->extra); + last = 1; + child.name = (const char *)(lex+1); + if (cb->open) + cb->open(&child, cb->extra); + lex_next = fdt_scan_helper( + lex + 2 + strlen(child.name)/4, + strings, &child, cb); + if (cb->close && + cb->close(&child, cb->extra) == -1) + while (lex != lex_next) + *lex++ = bswap(FDT_NOP); + lex = lex_next; + break; + } + case FDT_END_NODE: { + if (!last && node && cb->done) + cb->done(node, cb->extra); + return lex + 1; + } + default: { // FDT_END + if (!last && node && cb->done) + cb->done(node, cb->extra); + return lex; + } + } + } +} + +void fdt_scan(uintptr_t fdt, const struct fdt_cb *cb) +{ + struct fdt_header *header = (struct fdt_header *)fdt; + + // Only process FDT that we understand + if (bswap(header->magic) != FDT_MAGIC || + bswap(header->last_comp_version) > FDT_VERSION) + return; + + const char *strings = + (const char *)(fdt + bswap(header->off_dt_strings)); + uint32_t *lex = (uint32_t *)(fdt + bswap(header->off_dt_struct)); + + fdt_scan_helper(lex, strings, 0, cb); +} + +uint32_t fdt_size(uintptr_t fdt) +{ + struct fdt_header *header = (struct fdt_header *)fdt; + + // Only process FDT that we understand + if (bswap(header->magic) != FDT_MAGIC || + bswap(header->last_comp_version) > FDT_VERSION) + return 0; + return bswap(header->totalsize); +} + +const uint32_t *fdt_get_address( + const struct fdt_scan_node *node, + const uint32_t *value, + uint64_t *result) +{ + *result = 0; + for (int cells = node->address_cells; cells > 0; --cells) + *result = (*result << 32) + bswap(*value++); + return value; +} + +const uint32_t *fdt_get_size( + const struct fdt_scan_node *node, + const uint32_t *value, + uint64_t *result) +{ + *result = 0; + for (int cells = node->size_cells; cells > 0; --cells) + *result = (*result << 32) + bswap(*value++); + return value; +} + +void fdt_set_size( + const struct fdt_scan_node *node, + uint32_t *value, + uint64_t set) +{ + for (int cells = node->size_cells; cells > 0; --cells) { + value[cells-1] = bswap(set); + set >>= 32; + } +} + +int fdt_string_list_index(const struct fdt_scan_prop *prop, const char *str) +{ + const char *list = (const char *)prop->value; + const char *end = list + prop->len; + int index = 0; + while (end - list > 0) { + if (!strcmp(list, str)) + return index; + ++index; + list += strlen(list) + 1; + } + return -1; +} + +//////////////////////////// MEMORY REDUCE ///////////////////////////////////// + +struct mem_scan { + uint64_t size; + int memory; + const uint32_t *reg_value; + int reg_len; +}; + +static void mem_open(const struct fdt_scan_node *node, void *extra) +{ + struct mem_scan *scan = (struct mem_scan *)extra; + scan->memory = 0; +} + +static void mem_prop(const struct fdt_scan_prop *prop, void *extra) +{ + struct mem_scan *scan = (struct mem_scan *)extra; + if (!strcmp(prop->name, "device_type") && + !strcmp((const char *)prop->value, "memory")) { + scan->memory = 1; + } else if (!strcmp(prop->name, "reg")) { + scan->reg_value = prop->value; + scan->reg_len = prop->len; + } +} + +static void mem_done(const struct fdt_scan_node *node, void *extra) +{ + struct mem_scan *scan = (struct mem_scan *)extra; + const uint32_t *value = scan->reg_value; + const uint32_t *end = value + scan->reg_len/4; + uint32_t *size_ptr; + + if (!scan->memory) + return; + // assert (scan->reg_value && scan->reg_len % 4 == 0); + + while (end - value > 0) { + uint64_t base, size; + value = fdt_get_address(node->parent, value, &base); + size_ptr = (uint32_t *)value; + value = fdt_get_size(node->parent, value, &size); + if (size > scan->size) { + fdt_set_size(node->parent, size_ptr, scan->size); + scan->size = 0; + } else { + scan->size -= size; + } + } + // assert (end == value); +} + +void fdt_reduce_mem(uintptr_t fdt, uintptr_t size) +{ + struct fdt_cb cb; + struct mem_scan scan; + + memset(&cb, 0, sizeof(cb)); + cb.open = mem_open; + cb.prop = mem_prop; + cb.done = mem_done; + cb.extra = &scan; + scan.size = size; + + fdt_scan(fdt, &cb); +} + +//////////////////////////// MAC ADDRESS SET /////////////////////////////////// + +struct prop_scan { + const char *prop; + uint8_t *value; +}; + +static void set_prop(const struct fdt_scan_prop *prop, void *extra) +{ + struct prop_scan *scan = (struct prop_scan *)extra; + if (!strcmp(prop->name, scan->prop)) + memcpy(prop->value, scan->value, prop->len); +} + +void fdt_set_prop(uintptr_t fdt, const char *prop, uint8_t *value) +{ + struct fdt_cb cb; + struct prop_scan scan; + + memset(&cb, 0, sizeof(cb)); + cb.prop = set_prop; + cb.extra = &scan; + scan.value = value; + scan.prop = prop; + + fdt_scan(fdt, &cb); +} + diff --git a/src/arch/riscv/include/fdt.h b/src/arch/riscv/include/fdt.h new file mode 100644 index 0000000..1b8d498 --- /dev/null +++ b/src/arch/riscv/include/fdt.h @@ -0,0 +1,89 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 SiFive, Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef FDT_H +#define FDT_H + +#define FDT_MAGIC 0xd00dfeed +#define FDT_VERSION 17 + +struct fdt_header { + uint32_t magic; + uint32_t totalsize; + uint32_t off_dt_struct; + uint32_t off_dt_strings; + uint32_t off_mem_rsvmap; + uint32_t version; + uint32_t last_comp_version; /* <= 17 */ + uint32_t boot_cpuid_phys; + uint32_t size_dt_strings; + uint32_t size_dt_struct; +}; + +#define FDT_BEGIN_NODE 1 +#define FDT_END_NODE 2 +#define FDT_PROP 3 +#define FDT_NOP 4 +#define FDT_END 9 + +struct fdt_scan_node { + const struct fdt_scan_node *parent; + const char *name; + int address_cells; + int size_cells; +}; + +struct fdt_scan_prop { + const struct fdt_scan_node *node; + const char *name; + uint32_t *value; + int len; // in bytes of value +}; + +struct fdt_cb { + void (*open)(const struct fdt_scan_node *node, void *extra); + void (*prop)(const struct fdt_scan_prop *prop, void *extra); + // last property was seen + void (*done)(const struct fdt_scan_node *node, void *extra); + // -1 => delete the node + children + int (*close)(const struct fdt_scan_node *node, void *extra); + void *extra; +}; + +// Scan the contents of FDT +void fdt_scan(uintptr_t fdt, const struct fdt_cb *cb); +uint32_t fdt_size(uintptr_t fdt); + +// Extract fields +const uint32_t *fdt_get_address( + const struct fdt_scan_node *node, + const uint32_t *base, + uint64_t *value); +const uint32_t *fdt_get_size( + const struct fdt_scan_node *node, + const uint32_t *base, + uint64_t *value); +void fdt_set_size( + const struct fdt_scan_node *node, + uint32_t *value, + uint64_t set); +// -1 if not found +int fdt_string_list_index( + const struct fdt_scan_prop *prop, + const char *str); + +void fdt_reduce_mem(uintptr_t fdt, uintptr_t size); +void fdt_set_prop(uintptr_t fdt, const char *prop, uint8_t *value); + +#endif diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index 2e0eeb6..f410b14 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -77,6 +77,7 @@ #define CBMEM_ID_ROM1 0x524f4d31 #define CBMEM_ID_ROM2 0x524f4d32 #define CBMEM_ID_ROM3 0x524f4d33 +#define CBMEM_ID_DEVICETREE 0x44544220 #define CBMEM_ID_TO_NAME_TABLE \ { CBMEM_ID_ACPI, "ACPI " }, \ @@ -133,5 +134,6 @@ { CBMEM_ID_ROM0, "VGA ROM #0 "}, \ { CBMEM_ID_ROM1, "VGA ROM #1 "}, \ { CBMEM_ID_ROM2, "VGA ROM #2 "}, \ - { CBMEM_ID_ROM3, "VGA ROM #3 "}, + { CBMEM_ID_ROM3, "VGA ROM #3 "}, \ + { CBMEM_ID_DEVICETREE, "Device Tree"}, #endif /* _CBMEM_ID_H_ */ diff --git a/src/mainboard/sifive/hifive-unleashed/Makefile.inc b/src/mainboard/sifive/hifive-unleashed/Makefile.inc index 37d9804..1366038 100644 --- a/src/mainboard/sifive/hifive-unleashed/Makefile.inc +++ b/src/mainboard/sifive/hifive-unleashed/Makefile.inc @@ -23,3 +23,13 @@ ramstage-y += memlayout.ld ramstage-y += flash.c ramstage-y += media.c + + +DTB=build/hifive-unleashed.dtb +DTS=src/mainboard/sifive/hifive-unleashed/hifive-unleashed.dts +$(DTB): $(DTS) + dtc -I dts -O dtb -o $(DTB) $(DTS) + +cbfs-files-y += fallback/DTB +fallback/DTB-file := $(DTB) +fallback/DTB-type := raw diff --git a/src/mainboard/sifive/hifive-unleashed/hifive-unleashed.dts b/src/mainboard/sifive/hifive-unleashed/hifive-unleashed.dts new file mode 100644 index 0000000..6b9bbaa --- /dev/null +++ b/src/mainboard/sifive/hifive-unleashed/hifive-unleashed.dts @@ -0,0 +1,640 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 SiFive, Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +/dts-v1/; + +/ { + #address-cells = <2>; + #size-cells = <2>; + compatible = "sifive,fu540g", "sifive,fu500"; + model = "sifive,hifive-unleashed-a00"; + + aliases { + serial0 = &L28; + serial1 = &L29; + }; + + chosen { + }; +/* + firmware { + sifive,fsbl = "YYYY-MM-DD"; + }; +*/ + L3: cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <1000000>; + L9: cpu@0 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <16384>; + next-level-cache = <&L24 &L0>; + reg = <0>; + riscv,isa = "rv64imac"; + sifive,dtim = <&L8>; + sifive,itim = <&L7>; + status = "okay"; + L10: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + L12: cpu@1 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + next-level-cache = <&L24 &L0>; + reg = <1>; + riscv,isa = "rv64imafdc"; + sifive,itim = <&L11>; + status = "okay"; + tlb-split; + L13: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + L15: cpu@2 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + next-level-cache = <&L24 &L0>; + reg = <2>; + riscv,isa = "rv64imafdc"; + sifive,itim = <&L14>; + status = "okay"; + tlb-split; + L16: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + L18: cpu@3 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + next-level-cache = <&L24 &L0>; + reg = <3>; + riscv,isa = "rv64imafdc"; + sifive,itim = <&L17>; + status = "okay"; + tlb-split; + L19: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + L21: cpu@4 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + next-level-cache = <&L24 &L0>; + reg = <4>; + riscv,isa = "rv64imafdc"; + sifive,itim = <&L20>; + status = "okay"; + tlb-split; + L22: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + L36: memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x2 0x00000000>; + }; + L2: soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "SiFive,FU540G-soc", "fu500-soc", "sifive-soc", "simple-bus"; + ranges; + refclk: refclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <33333333>; + clock-output-names = "xtal"; + }; + prci: prci@10000000 { + /* compatible = "sifive,ux00prci0"; */ + compatible = "sifive,aloeprci0"; + reg = <0x0 0x10000000 0x0 0x1000>; + reg-names = "control"; + clocks = <&refclk>; + #clock-cells = <1>; + }; + tlclk: tlclk { + compatible = "fixed-factor-clock"; + clocks = <&prci 0>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; + L51: cadence-gemgxl-mgmt@100a0000 { + compatible = "sifive,cadencegemgxlmgmt0"; + reg = <0x0 0x100a0000 0x0 0x1000>; + reg-names = "control"; + #clock-cells = <0>; + }; + L35: bus-blocker@100b8000 { + compatible = "sifive,bus-blocker0"; + reg = <0x0 0x100b8000 0x0 0x1000>; + reg-names = "control"; + }; + L0: cache-controller@2010000 { + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <2048>; + cache-size = <2097152>; + cache-unified; + compatible = "sifive,ccache0", "cache"; + interrupt-parent = <&L4>; + interrupts = <1 2 3>; + next-level-cache = <&L25 &L40 &L36>; + reg = <0x0 0x2010000 0x0 0x1000 0x0 0x8000000 0x0 0x2000000>; + reg-names = "control", "sideband"; + }; + L33: cadence-ddr-mgmt@100c0000 { + compatible = "sifive,cadenceddrmgmt0"; + reg = <0x0 0x100c0000 0x0 0x1000>; + reg-names = "control"; + }; + L40: chiplink@40000000 { + #address-cells = <2>; + #size-cells = <2>; + compatible = "sifive,chiplink", "simple-bus"; + ranges = <0x0 0x60000000 0x0 0x60000000 0x0 0x20000000 0x30 0x0 0x30 0x0 0x10 0x0 0x0 0x40000000 0x0 0x40000000 0x0 0x20000000 0x20 0x0 0x20 0x0 0x10 0x0>; + }; + L5: clint@2000000 { + compatible = "riscv,clint0"; + interrupts-extended = <&L10 3 &L10 7 &L13 3 &L13 7 &L16 3 &L16 7 &L19 3 &L19 7 &L22 3 &L22 7>; + reg = <0x0 0x2000000 0x0 0x10000>; + reg-names = "control"; + }; + L6: debug-controller@0 { + compatible = "sifive,debug-013", "riscv,debug-013"; + interrupts-extended = <&L10 65535 &L13 65535 &L16 65535 &L19 65535 &L22 65535>; + reg = <0x0 0x0 0x0 0x1000>; + reg-names = "control"; + }; + L32: dma@3000000 { + #dma-cells = <1>; + compatible = "riscv,dma0"; + dma-channels = <4>; + dma-requests = <0>; + interrupt-parent = <&L4>; + interrupts = <23 24 25 26 27 28 29 30>; + reg = <0x0 0x3000000 0x0 0x100000>; + reg-names = "control"; + riscv,dma-pools = <1>; + }; + L8: dtim@1000000 { + compatible = "sifive,dtim0"; + reg = <0x0 0x1000000 0x0 0x2000>; + reg-names = "mem"; + }; + L44: ememoryotp@10070000 { + compatible = "sifive,ememoryotp0"; + reg = <0x0 0x10070000 0x0 0x1000>; + reg-names = "control"; + }; + L24: error-device@18000000 { + compatible = "sifive,error0"; + reg = <0x0 0x18000000 0x0 0x8000000>; + reg-names = "mem"; + }; + L52: ethernet@10090000 { + compatible = "cdns,macb"; + interrupt-parent = <&L4>; + interrupts = <53>; + reg = <0x0 0x10090000 0x0 0x2000>; + reg-names = "control"; + + local-mac-address = [00 00 00 00 00 00]; + phy-mode = "gmii"; + clock-names = "pclk", "hclk", "tx_clk"; + clocks = <&prci 1>, <&prci 1>, <&L51>; + + #address-cells = <1>; + #size-cells = <0>; + phy1: ethernet-phy@0 { + reg = <0>; + reset-gpios = <&L31 12 1>; + }; + }; + L31: gpio@10060000 { + compatible = "sifive,gpio0"; + interrupt-parent = <&L4>; + interrupts = <7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22>; + reg = <0x0 0x10060000 0x0 0x1000>; + reg-names = "control"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + gpio-restart { + compatible = "gpio-restart"; + gpios = <&L31 10 1>; + }; + L47: i2c@10030000 { + compatible = "sifive,i2c0", "opencores,i2c-ocores"; + reg = <0x0 0x10030000 0x0 0x1000>; + reg-names = "control"; + clocks = <&tlclk>; + + reg-shift = <2>; + reg-io-width = <1>; + + #address-cells = <1>; + #size-cells = <0>; + + /* On pre-production boards only */ +/* + ina233-vdd_soc_core@40 { + compatible = "ti,pmbus"; + reg = <0x40>; + }; + ina233-vdd_ddr_soc@44 { + compatible = "ti,pmbus"; + reg = <0x44>; + }; + ina233-vdd_ddr_mem@45 { + compatible = "ti,pmbus"; + reg = <0x45>; + }; + ina233-vdd_corepll@47 { + compatible = "ti,pmbus"; + reg = <0x47>; + }; + ina233-vdd_otp@4a { + compatible = "ti,pmbus"; + reg = <0x4a>; + }; + ina233-vdd_io@4b { + compatible = "ti,pmbus"; + reg = <0x4b>; + }; + ina233-vdd_ddrpll@48 { + compatible = "ti,pmbus"; + reg = <0x48>; + }; + ina233-avdd_ddrpll@49 { + compatible = "ti,pmbus"; + reg = <0x49>; + }; + ina233-vdd_givdd@4c { + compatible = "ti,pmbus"; + reg = <0x4c>; + }; + ina233vdd_gemgxlpll@4d { + compatible = "ti,pmbus"; + reg = <0x4d>; + }; +*/ + /* On the tester board */ +/* + m24c02 { + compatible = "st,24c02"; + reg = <0x51>; + }; +*/ + }; + L4: interrupt-controller@c000000 { + #interrupt-cells = <1>; + compatible = "riscv,plic0"; + interrupt-controller; + interrupts-extended = <&L10 11 &L13 11 &L13 9 &L16 11 &L16 9 &L19 11 &L19 9 &L22 11 &L22 9>; + reg = <0x0 0xc000000 0x0 0x4000000>; + reg-names = "control"; + riscv,max-priority = <7>; + riscv,ndev = <53>; + }; + L7: itim@1800000 { + compatible = "sifive,itim0"; + reg = <0x0 0x1800000 0x0 0x4000>; + reg-names = "mem"; + }; + L11: itim@1808000 { + compatible = "sifive,itim0"; + reg = <0x0 0x1808000 0x0 0x8000>; + reg-names = "mem"; + }; + L14: itim@1810000 { + compatible = "sifive,itim0"; + reg = <0x0 0x1810000 0x0 0x8000>; + reg-names = "mem"; + }; + L17: itim@1818000 { + compatible = "sifive,itim0"; + reg = <0x0 0x1818000 0x0 0x8000>; + reg-names = "mem"; + }; + L20: itim@1820000 { + compatible = "sifive,itim0"; + reg = <0x0 0x1820000 0x0 0x8000>; + reg-names = "mem"; + }; + L37: memory-controller@100b0000 { + /* compatible = "sifive,ux00ddr0"; */ + compatible = "sifive,aloeddr0"; + interrupt-parent = <&L4>; + interrupts = <31>; + reg = <0x0 0x100b0000 0x0 0x4000>; + reg-names = "control"; + }; + pci@2000000000 { + #address-cells = <3>; + #interrupt-cells = <1>; + #size-cells = <2>; + compatible = "xlnx,axi-pcie-host-1.00.a"; + device_type = "pci"; + interrupt-map = <0 0 0 1 &xil_pcie_intc 1 0 0 0 2 &xil_pcie_intc 2 0 0 0 3 &xil_pcie_intc 3 0 0 0 4 &xil_pcie_intc 4>; + interrupt-map-mask = <0 0 0 7>; + interrupt-parent = <&L4>; + interrupts = <32>; + ranges = <0x2000000 0x0 0x40000000 0x0 0x40000000 0x0 0x20000000>; + reg = <0x020 0x0 0x0 0x4000000>; + reg-names = "control"; + xil_pcie_intc: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; +/* + pci@2030000000 { + #address-cells = <3>; + #interrupt-cells = <1>; + #size-cells = <2>; + compatible = "ms-pf,axi-pcie-host"; + device_type = "pci"; + bus-range = <0x01 0x7f>; + interrupt-map = <0 0 0 1 &ms_pcie_intc 1 0 0 0 2 &ms_pcie_intc 2 0 0 0 3 &ms_pcie_intc 3 0 0 0 4 &ms_pcie_intc 4>; + interrupt-map-mask = <0 0 0 7>; + interrupt-parent = <&L4>; + interrupts = <32>; + ranges = <0x2000000 0x0 0x40000000 0x0 0x40000000 0x0 0x20000000>; + reg = <0x20 0x30000000 0x0 0x4000000 0x20 0x0 0x0 0x100000>; + reg-names = "control", "apb"; + ms_pcie_intc: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; +*/ + L53: pinctrl@10080000 { + compatible = "sifive,pinctrl0"; + reg = <0x0 0x10080000 0x0 0x1000>; + reg-names = "control"; + }; + L45: pwm@10020000 { + compatible = "sifive,pwm0"; + interrupt-parent = <&L4>; + interrupts = <42 43 44 45>; + reg = <0x0 0x10020000 0x0 0x1000>; + reg-names = "control"; + clocks = <&tlclk>; + sifive,approx-period = <1000000>; + #pwm-cells = <2>; + }; + L46: pwm@10021000 { + compatible = "sifive,pwm0"; + interrupt-parent = <&L4>; + interrupts = <46 47 48 49>; + reg = <0x0 0x10021000 0x0 0x1000>; + reg-names = "control"; + clocks = <&tlclk>; + sifive,approx-period = <1000000>; + #pwm-cells = <2>; + }; + pwmleds { + compatible = "pwm-leds"; + heartbeat { + pwms = <&L45 0 0>; + max-brightness = <255>; + linux,default-trigger = "heartbeat"; + }; + mtd { + pwms = <&L45 1 0>; + max-brightness = <255>; + linux,default-trigger = "mtd"; + }; + netdev { + pwms = <&L45 2 0>; + max-brightness = <255>; + linux,default-trigger = "netdev"; + }; + panic { + pwms = <&L45 3 0>; + max-brightness = <255>; + linux,default-trigger = "panic"; + }; + /* These LEDs are on the tester board */ +/* + testled { + pwms = <&L46 0 0>; + max-brightness = <255>; + }; + green { + pwms = <&L46 1 0>; + max-brightness = <255>; + }; + red { + pwms = <&L46 2 0>; + max-brightness = <255>; + }; + blue { + pwms = <&L46 3 0>; + max-brightness = <255>; + }; +*/ + }; + L27: rom@1000 { + compatible = "sifive,modeselect0"; + reg = <0x0 0x1000 0x0 0x1000>; + reg-names = "mem"; + }; + L26: rom@10000 { + compatible = "sifive,maskrom0"; + reg = <0x0 0x10000 0x0 0x8000>; + reg-names = "mem"; + }; + L25: rom@a000000 { + compatible = "ucbbar,cacheable-zero0"; + reg = <0x0 0xa000000 0x0 0x2000000>; + reg-names = "mem"; + }; + L28: serial@10010000 { + compatible = "sifive,uart0"; + interrupt-parent = <&L4>; + interrupts = <4>; + reg = <0x0 0x10010000 0x0 0x1000>; + reg-names = "control"; + clocks = <&tlclk>; + }; + L29: serial@10011000 { + compatible = "sifive,uart0"; + interrupt-parent = <&L4>; + interrupts = <5>; + reg = <0x0 0x10011000 0x0 0x1000>; + reg-names = "control"; + clocks = <&tlclk>; + }; + L49: spi@10040000 { + compatible = "sifive,spi0"; + interrupt-parent = <&L4>; + interrupts = <51>; + reg = <0x0 0x10040000 0x0 0x1000 0x0 0x20000000 0x0 0x10000000>; + reg-names = "control", "mem"; + clocks = <&tlclk>; + + #address-cells = <1>; + #size-cells = <0>; + flash@0 { + compatible = "issi,is25wp256d", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; + }; + L50: spi@10041000 { + compatible = "sifive,spi0"; + interrupt-parent = <&L4>; + interrupts = <52>; + reg = <0x0 0x10041000 0x0 0x1000 0x0 0x30000000 0x0 0x10000000>; + reg-names = "control", "mem"; + clocks = <&tlclk>; + + #address-cells = <1>; + #size-cells = <0>; + + /* These flash chips are on the tester board */ +/* + flash@0 { + compatible = "issi,is25wp032", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + m25p,fast-read; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; + flash@1 { + compatible = "issi,is25wp032", "jedec,spi-nor"; + reg = <1>; + spi-max-frequency = <25000000>; + m25p,fast-read; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; + flash@2 { + compatible = "issi,is25wp032", "jedec,spi-nor"; + reg = <2>; + spi-max-frequency = <25000000>; + m25p,fast-read; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; + flash@3 { + compatible = "issi,is25wp032", "jedec,spi-nor"; + reg = <3>; + spi-max-frequency = <25000000>; + m25p,fast-read; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +*/ + }; + L30: spi@10050000 { + compatible = "sifive,spi0"; + interrupt-parent = <&L4>; + interrupts = <6>; + reg = <0x0 0x10050000 0x0 0x1000>; + reg-names = "control"; + clocks = <&tlclk>; + + #address-cells = <1>; + #size-cells = <0>; + mmc@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + spi-max-frequency = <20000000>; + voltage-ranges = <3300 3300>; + disable-wp; + gpios = <&L31 11 1>; + }; + }; + L23: teststatus@4000 { + compatible = "sifive,test0"; + reg = <0x0 0x4000 0x0 0x1000>; + reg-names = "control"; + }; + }; +}; diff --git a/src/mainboard/sifive/hifive-unleashed/romstage.c b/src/mainboard/sifive/hifive-unleashed/romstage.c index 8277141..17d1aef 100644 --- a/src/mainboard/sifive/hifive-unleashed/romstage.c +++ b/src/mainboard/sifive/hifive-unleashed/romstage.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google, Inc. + * Copyright (C) 2019 HardenedLinux * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -20,6 +21,36 @@ #include <program_loading.h> #include <soc/clock.h> #include <soc/sdram.h> +#include <mcall.h> +#include <fdt.h> +#include <string.h> +#include <symbols.h> +#include <cbfs.h> +#include <soc/otp.h> + +static void update_dtb(void) +{ + uintptr_t dtb_maskrom = (uintptr_t)cbfs_boot_map_with_leak( + "fallback/DTB", CBFS_TYPE_RAW, NULL); + uint32_t dtb_size = fdt_size(dtb_maskrom); + uintptr_t dtb_target = (uintptr_t)cbmem_add(CBMEM_ID_DEVICETREE, + dtb_size); + + memcpy((void *)dtb_target, (void *)dtb_maskrom, dtb_size); + fdt_reduce_mem(dtb_target, sdram_size_mb() * 1024 * 1024); + + uint32_t serial = otp_read_serial(); + unsigned char mac[6] = { 0x70, 0xb3, 0xd5, 0x92, 0xf0, 0x00 }; + if (serial != ~0) { + mac[5] |= (serial >> 0) & 0xff; + mac[4] |= (serial >> 8) & 0xff; + mac[3] |= (serial >> 16) & 0xff; + } + fdt_set_prop(dtb_target, "local-mac-address", &mac[0]); + + for (int i = 0; i < CONFIG_MAX_CPUS; i++) + OTHER_HLS(i)->fdt = (void *)dtb_target; +} void main(void) { @@ -43,5 +74,7 @@ cbmem_initialize_empty(); + update_dtb(); + run_ramstage(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/31047 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic29f0e590311360b85fafd12ebc36cd189fbbc38 Gerrit-Change-Number: 31047 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-MessageType: newchange

5 32

Change in ...coreboot[master]: mediatek/mt8183: Add RTC support
by Ran Bi (Code Review) 28 Feb '19

28 Feb '19

Ran Bi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31046 Change subject: mediatek/mt8183: Add RTC support ...................................................................... mediatek/mt8183: Add RTC support This patch implements RTC initialization. 1. initialization dcxo 2. rtc clock using dcxo 32k 3. export RTC_32K1V8_0 to SOC, export RTC_32K1V8_1 to WLAN 4. rtc register initialization BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: Icccb9360a507fcbfd865b107cd3630e71c810d55 Signed-off-by: Ran Bi <ran.bi(a)mediatek.com> --- M src/mainboard/google/kukui/romstage.c M src/soc/mediatek/mt8183/Makefile.inc A src/soc/mediatek/mt8183/include/soc/rtc.h A src/soc/mediatek/mt8183/rtc.c 4 files changed, 630 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/31046/1 diff --git a/src/mainboard/google/kukui/romstage.c b/src/mainboard/google/kukui/romstage.c index 629692d..f4d1e8e 100644 --- a/src/mainboard/google/kukui/romstage.c +++ b/src/mainboard/google/kukui/romstage.c @@ -17,10 +17,12 @@ #include <soc/emi.h> #include <soc/mmu_operations.h> #include <soc/mt6358.h> +#include <soc/rtc.h> void platform_romstage_main(void) { mt6358_init(); + rtc_boot(); mt_mem_init(get_sdram_config()); mtk_mmu_after_dram(); } diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index 9aa1733..bd22585 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -30,6 +30,7 @@ romstage-y += ../common/gpio.c gpio.c romstage-y += ../common/mmu_operations.c mmu_operations.c romstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6358.c +romstage-y += rtc.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c romstage-y += ../common/timer.c romstage-y += ../common/uart.c diff --git a/src/soc/mediatek/mt8183/include/soc/rtc.h b/src/soc/mediatek/mt8183/include/soc/rtc.h new file mode 100644 index 0000000..1f8de50 --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/rtc.h @@ -0,0 +1,208 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_MEDIATEK_MT8183_RTC_H +#define SOC_MEDIATEK_MT8183_RTC_H + +/* + * Default values for RTC initialization + * Year (YEA) : 1970 ~ 2037 + * Month (MTH) : 1 ~ 12 + * Day of Month (DOM): 1 ~ 31 + */ + +enum { + RTC_DEFAULT_YEA = 2010, + RTC_DEFAULT_MTH = 1, + RTC_DEFAULT_DOM = 1, + RTC_DEFAULT_DOW = 5 +}; + +enum { + RTC_2SEC_REBOOT_ENABLE = 1, + RTC_2SEC_MODE = 2 +}; + +/* RTC registers */ +enum { + RTC_BBPU = 0x0588, + RTC_IRQ_STA = 0x058A, + RTC_IRQ_EN = 0x058C, + RTC_CII_EN = 0x058E +}; + +enum { + RTC_TC_SEC = 0x0592, + RTC_TC_MIN = 0x0594, + RTC_TC_HOU = 0x0596, + RTC_TC_DOM = 0x0598, + RTC_TC_DOW = 0x059A, + RTC_TC_MTH = 0x059C, + RTC_TC_YEA = 0x059E +}; + +enum { + RTC_AL_SEC = 0x05A0, + RTC_AL_MIN = 0x05A2, + RTC_AL_HOU = 0x05A4, + RTC_AL_DOM = 0x05A6, + RTC_AL_DOW = 0x05A8, + RTC_AL_MTH = 0x05AA, + RTC_AL_YEA = 0x05AC, + RTC_AL_MASK = 0x0590 +}; + +enum { + RTC_OSC32CON = 0x05AE, + RTC_CON = 0x05C4, + RTC_WRTGR = 0x05C2 +}; + +enum { + RTC_POWERKEY1 = 0x05B0, + RTC_POWERKEY2 = 0x05B2 +}; + +enum { + RTC_PDN1 = 0x05B4, + RTC_PDN2 = 0x05B6, + RTC_SPAR0 = 0x05B8, + RTC_SPAR1 = 0x05BA, + RTC_PROT = 0x05BC, + RTC_DIFF = 0x05BE, + RTC_CALI = 0x05C0 +}; + +enum { + RTC_OSC32CON_UNLOCK1 = 0x1A57, + RTC_OSC32CON_UNLOCK2 = 0x2B68 +}; + +enum { + RTC_PROT_UNLOCK1 = 0x586A, + RTC_PROT_UNLOCK2 = 0x9136 +}; + +enum { + RTC_BBPU_PWREN = 1U << 0, + RTC_BBPU_CLR = 1U << 1, + RTC_BBPU_INIT = 1U << 2, + RTC_BBPU_AUTO = 1U << 3, + RTC_BBPU_CLRPKY = 1U << 4, + RTC_BBPU_RELOAD = 1U << 5, + RTC_BBPU_CBUSY = 1U << 6, + + RTC_CBUSY_TIMEOUT_US = 800 +}; + +enum { + RTC_BBPU_KEY = 0x43 << 8 +}; + +enum { + RTC_IRQ_STA_AL = 1U << 0, + RTC_IRQ_STA_TC = 1U << 1, + RTC_IRQ_STA_LP = 1U << 3 +}; + +enum { + RTC_IRQ_EN_AL = 1U << 0, + RTC_IRQ_EN_TC = 1U << 1, + RTC_IRQ_EN_ONESHOT = 1U << 2, + RTC_IRQ_EN_LP = 1U << 3, + RTC_IRQ_EN_ONESHOT_AL = RTC_IRQ_EN_ONESHOT | RTC_IRQ_EN_AL +}; + +enum { + RTC_POWERKEY1_KEY = 0xa357, + RTC_POWERKEY2_KEY = 0x67d2 +}; + +enum { + RTC_CON_VBAT_LPSTA_RAW = 1U << 0, + RTC_CON_EOSC32_LPEN = 1U << 1, + RTC_CON_XOSC32_LPEN = 1U << 2, + RTC_CON_LPRST = 1U << 3, + RTC_CON_CDBO = 1U << 4, + RTC_CON_F32KOB = 1U << 5, + RTC_CON_GPO = 1U << 6, + RTC_CON_GOE = 1U << 7, + RTC_CON_GSR = 1U << 8, + RTC_CON_GSMT = 1U << 9, + RTC_CON_GPEN = 1U << 10, + RTC_CON_GPU = 1U << 11, + RTC_CON_GE4 = 1U << 12, + RTC_CON_GE8 = 1U << 13, + RTC_CON_GPI = 1U << 14, + RTC_CON_LPSTA_RAW = 1U << 15 +}; + +enum { + RTC_EMBCK_SRC_SEL = 1 << 8, + RTC_EMBCK_SEL_MODE = 3 << 6, + RTC_XOSC32_ENB = 1 << 5, + RTC_REG_XOSC32_ENB = 1 << 15 +}; + +enum { + RTC_SPAR0_32K_LESS = 1U << 6 +}; + +enum { + RTC_MIN_YEAR = 1968, + RTC_BASE_YEAR = 1900, + RTC_MIN_YEAR_OFFSET = RTC_MIN_YEAR - RTC_BASE_YEAR, + + RTC_NUM_YEARS = 128 +}; + +enum { + RTC_STATE_REBOOT = 0, + RTC_STATE_RECOVER = 1, + RTC_STATE_INIT = 2 +}; + +/* PMIC TOP Register Definition */ +enum { + PMIC_RG_TOP_CKPDN_CON1 = 0x0112, + PMIC_RG_TOP_CKPDN_CON1_SET = 0x0114, + PMIC_RG_TOP_CKPDN_CON1_CLR = 0x0116, + PMIC_RG_TOP_CKSEL_CON0 = 0x0118, + PMIC_RG_TOP_CKSEL_CON0_SET = 0x011A, + PMIC_RG_TOP_CKSEL_CON0_CLR = 0x011C +}; + +/* PMIC DCXO Register Definition */ +enum { + PMIC_RG_DCXO_CW00 = 0x0788, + PMIC_RG_DCXO_CW07 = 0x079A, + PMIC_RG_DCXO_CW09 = 0x079E, + PMIC_RG_DCXO_CW11 = 0x07A2, + PMIC_RG_DCXO_CW13 = 0x07AA, + PMIC_RG_DCXO_CW15 = 0x07AE, + PMIC_RG_DCXO_CW16 = 0x07B0, + PMIC_RG_DCXO_CW21 = 0x07BA, + PMIC_RG_DCXO_ELR0 = 0x07C4 +}; + +enum { + PMIC_RG_TOP_TMA_KEY = 0x03A8 +}; + +void rtc_boot(void); +void rtc_bbpu_power_on(void); +void rtc_bbpu_power_down(void); + +#endif /* SOC_MEDIATEK_MT8183_RTC_H */ diff --git a/src/soc/mediatek/mt8183/rtc.c b/src/soc/mediatek/mt8183/rtc.c new file mode 100644 index 0000000..e3f4e3a --- /dev/null +++ b/src/soc/mediatek/mt8183/rtc.c @@ -0,0 +1,419 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <bcd.h> +#include <console/console.h> +#include <delay.h> +#include <rtc.h> +#include <timer.h> + +#include <soc/mt6358.h> +#include <soc/pmic_wrap.h> +#include <soc/rtc.h> + +#define RTC_GPIO_USER_MASK ((1 << 13) - (1 << 8)) + +/* ensure rtc write success */ +static inline int rtc_busy_wait(void) +{ + struct stopwatch sw; + u16 bbpu; + + stopwatch_init_usecs_expire(&sw, RTC_CBUSY_TIMEOUT_US); + + do { + pwrap_read(RTC_BBPU, &bbpu); + /* Time > 1sec, time out and set recovery mode enable.*/ + if (stopwatch_expired(&sw)) { + printk(BIOS_INFO, "[RTC] BBPU CBUSY time out !!\n"); + return 0; + } + } while (bbpu & RTC_BBPU_CBUSY); + + return 1; +} + +static int write_trigger(void) +{ + pwrap_write(RTC_WRTGR, 1); + return rtc_busy_wait(); +} + +/* unlock rtc write interface */ +static int writeif_unlock(void) +{ + pwrap_write(RTC_PROT, RTC_PROT_UNLOCK1); + if (!write_trigger()) + return 0; + pwrap_write(RTC_PROT, RTC_PROT_UNLOCK2); + if (!write_trigger()) + return 0; + + return 1; +} + +/* set rtc time */ +int rtc_set(const struct rtc_time *time) +{ + return -1; +} + +/* get rtc time */ +int rtc_get(struct rtc_time *time) +{ + u16 value; + + pwrap_read(RTC_TC_SEC, &value); + time->sec = value; + pwrap_read(RTC_TC_MIN, &value); + time->min = value; + pwrap_read(RTC_TC_HOU, &value); + time->hour = value; + pwrap_read(RTC_TC_DOM, &value); + time->mday = value; + pwrap_read(RTC_TC_MTH, &value); + time->mon = value; + pwrap_read(RTC_TC_YEA, &value); + time->year = (value + RTC_MIN_YEAR_OFFSET) % 100; + + return 0; +} + +/* set rtc xosc setting */ +static void rtc_xosc_write(u16 val) +{ + pwrap_write(RTC_OSC32CON, RTC_OSC32CON_UNLOCK1); + udelay(200); + pwrap_write(RTC_OSC32CON, RTC_OSC32CON_UNLOCK2); + udelay(200); + + pwrap_write(RTC_OSC32CON, val); + udelay(200); +} + +/* initialize rtc related registers */ +static int rtc_reg_init(void) +{ + u16 irqsta; + + pwrap_write(RTC_IRQ_EN, 0); + pwrap_write(RTC_CII_EN, 0); + pwrap_write(RTC_AL_MASK, 0); + pwrap_write(RTC_AL_YEA, 1970 - RTC_MIN_YEAR); + pwrap_write(RTC_AL_MTH, 1); + pwrap_write(RTC_AL_DOM, 1); + pwrap_write(RTC_AL_DOW, 4); + pwrap_write(RTC_AL_HOU, 0); + pwrap_write(RTC_AL_MIN, 0); + pwrap_write(RTC_AL_SEC, 0); + + pwrap_write(RTC_DIFF, 0); + pwrap_write(RTC_CALI, 0); + if (!write_trigger()) + return 0; + + pwrap_read(RTC_IRQ_STA, &irqsta); /* read clear */ + + /* init time counters after resetting RTC_DIFF and RTC_CALI */ + pwrap_write(RTC_TC_YEA, RTC_DEFAULT_YEA - RTC_MIN_YEAR); + pwrap_write(RTC_TC_MTH, RTC_DEFAULT_MTH); + pwrap_write(RTC_TC_DOM, RTC_DEFAULT_DOM); + pwrap_write(RTC_TC_DOW, RTC_DEFAULT_DOW); + pwrap_write(RTC_TC_HOU, 0); + pwrap_write(RTC_TC_MIN, 0); + pwrap_write(RTC_TC_SEC, 0); + + return write_trigger(); +} + +/* initialize rtc setting of using dcxo clock */ +static void rtc_enable_dcxo(void) +{ + u16 bbpu, con, osc32con, sec; + + pwrap_read(RTC_BBPU, &bbpu); + pwrap_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD); + write_trigger(); + + mdelay(1); + if (!writeif_unlock()) /* Unlock for reload */ + printk(BIOS_INFO, "[RTC] %s writeif_unlock() fail\n", __func__); + + pwrap_read(RTC_OSC32CON, &osc32con); + rtc_xosc_write((osc32con & ~RTC_EMBCK_SRC_SEL) | RTC_XOSC32_ENB | RTC_REG_XOSC32_ENB); + pwrap_read(RTC_BBPU, &bbpu); + pwrap_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD); + write_trigger(); + + pwrap_read(RTC_CON, &con); + pwrap_read(RTC_OSC32CON, &osc32con); + pwrap_read(RTC_AL_SEC, &sec); + printk(BIOS_INFO, "[RTC] %s con = 0x%x, osc32con = 0x%x, sec = 0x%x\n", + __func__, con, osc32con, sec); +} + +/* initialize rtc related gpio */ +static int rtc_gpio_init(void) +{ + u16 con; + + /* RTC_32K1V8 clock change from 128k div 4 source + * to RTC 32k source + */ + pwrap_write_field(PMIC_RG_TOP_CKSEL_CON0_SET, 0x1, 0x1, 3); + + /* Export 32K clock RTC_32K1V8_1 */ + pwrap_write_field(PMIC_RG_TOP_CKPDN_CON1_CLR, 0x1, 0x1, 1); + + /* Export 32K clock RTC_32K2V8 */ + pwrap_read(RTC_CON, &con); + con &= (RTC_CON_LPSTA_RAW | RTC_CON_LPRST | RTC_CON_EOSC32_LPEN); + con |= (RTC_CON_GPEN | RTC_CON_GOE); + con &= ~(RTC_CON_F32KOB); + pwrap_write(RTC_CON, con); + return write_trigger(); +} + +/* set xosc mode */ +static void rtc_osc_init(void) +{ + /* enable 32K export */ + rtc_gpio_init(); +} + +/* low power detect setting */ +static int rtc_lpd_init(void) +{ + u16 con; + + con = pwrap_read(RTC_CON, &con) | RTC_CON_XOSC32_LPEN; + con &= ~RTC_CON_LPRST; + pwrap_write(RTC_CON, con); + if (!write_trigger()) + return 0; + + con |= RTC_CON_LPRST; + pwrap_write(RTC_CON, con); + if (!write_trigger()) + return 0; + + con &= ~RTC_CON_LPRST; + pwrap_write(RTC_CON, con); + if (!write_trigger()) + return 0; + + con = pwrap_read(RTC_CON, &con) | RTC_CON_EOSC32_LPEN; + con &= ~RTC_CON_LPRST; + pwrap_write(RTC_CON, con); + if (!write_trigger()) + return 0; + + con |= RTC_CON_LPRST; + pwrap_write(RTC_CON, con); + if (!write_trigger()) + return 0; + + con &= ~RTC_CON_LPRST; + pwrap_write(RTC_CON, con); + if (!write_trigger()) + return 0; + + return 1; +} + +static bool rtc_hw_init(void) +{ + u16 bbpu; + + pwrap_read(RTC_BBPU, &bbpu); + pwrap_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_INIT); + write_trigger(); + + udelay(500); + + pwrap_read(RTC_BBPU, &bbpu); + pwrap_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD); + write_trigger(); + + pwrap_read(RTC_BBPU, &bbpu); + if (bbpu & RTC_BBPU_INIT) { + printk(BIOS_INFO, "[RTC] %s:%d timeout\n", __func__,__LINE__); + return false; + } + + return true; +} + +/* rtc init check */ +static int rtc_init(u8 recover) +{ + printk(BIOS_INFO, "[RTC] %s recovery: %d\n", __func__, recover); + + if (!writeif_unlock()) + return 0; + + if (!rtc_gpio_init()) + return 0; + + /* using dcxo 32K clock */ + rtc_enable_dcxo(); + + if (recover) + mdelay(20); + + /* write powerkeys */ + pwrap_write(RTC_POWERKEY1, RTC_POWERKEY1_KEY); + pwrap_write(RTC_POWERKEY2, RTC_POWERKEY2_KEY); + if (!write_trigger()) + return 0; + + if (!rtc_reg_init()) + return 0; + if (!rtc_lpd_init()) + return 0; + if (!rtc_hw_init()) + return 0; + + return 1; +} + +/* enable rtc bbpu */ +void rtc_bbpu_power_on(void) +{ + u16 bbpu; + int ret; + + /* pull powerhold high, control by pmic */ + pmic_set_power_hold(true); + + /* pull PWRBB high */ + bbpu = RTC_BBPU_KEY | RTC_BBPU_AUTO | RTC_BBPU_RELOAD | RTC_BBPU_PWREN; + pwrap_write(RTC_BBPU, bbpu); + ret = write_trigger(); + printk(BIOS_INFO, "[RTC] %s write_trigger=%d\n", __func__, ret); + + /* enable dcxo to transform external 32KHz clock to 26MHz clock + directly sent to SoC */ + + pwrap_read(RTC_BBPU, &bbpu); + printk(BIOS_INFO, "[RTC] %s done BBPU=%#x\n", __func__, bbpu); +} + +void rtc_bbpu_power_down(void) +{ + u16 bbpu; + + if (!writeif_unlock()) + printk(BIOS_INFO, "[RTC] %s Writeif_unlock() fail\n", __func__); + /* pull PWRBB low */ + bbpu = RTC_BBPU_KEY | RTC_BBPU_RELOAD | RTC_BBPU_PWREN; + pwrap_write(RTC_BBPU, bbpu); + + pmic_set_power_hold(false); +} + +static u8 rtc_check_state(void) +{ + u16 con; + u16 pwrky1; + u16 pwrky2; + + pwrap_read(RTC_CON, &con); + pwrap_read(RTC_POWERKEY1, &pwrky1); + pwrap_read(RTC_POWERKEY2, &pwrky2); + + if (con & RTC_CON_LPSTA_RAW) + return RTC_STATE_INIT; + + if (!rtc_busy_wait()) + return RTC_STATE_RECOVER; + + if (!writeif_unlock()) + return RTC_STATE_RECOVER; + + if (pwrky1 != RTC_POWERKEY1_KEY || pwrky2 != RTC_POWERKEY2_KEY) + return RTC_STATE_INIT; + else + return RTC_STATE_REBOOT; +} + +static void dcxo_init(void) +{ + /* Buffer setting */ + pwrap_write(PMIC_RG_DCXO_CW15, 0xA2AA); + pwrap_write(PMIC_RG_DCXO_CW13, 0x98E9); + pwrap_write(PMIC_RG_DCXO_CW16, 0x9855); + + /* 26M enable control */ + /* Enable clock buffer XO_SOC, XO_CEL */ + pwrap_write(PMIC_RG_DCXO_CW00, 0x4805); + pwrap_write(PMIC_RG_DCXO_CW11, 0x8000); + + /* Load thermal coefficient */ + pwrap_write(PMIC_RG_TOP_TMA_KEY, 0x9CA7); + pwrap_write(PMIC_RG_DCXO_CW21, 0x12A7); + pwrap_write(PMIC_RG_DCXO_ELR0, 0xD004); + pwrap_write(PMIC_RG_TOP_TMA_KEY, 0x0000); + + /* Adjust OSC FPM setting */ + pwrap_write(PMIC_RG_DCXO_CW07, 0x8FFE); + + /* Re-Calibrate OSC current */ + pwrap_write(PMIC_RG_DCXO_CW09, 0x008F); + mdelay(1); + pwrap_write(PMIC_RG_DCXO_CW09, 0x408F); + mdelay(5); +} + +/* the rtc boot flow entry */ +void rtc_boot(void) +{ + u16 bbpu; + u16 con; + u16 irqsta; + + /* dcxo clock init settings */ + dcxo_init(); + + /* dcxo 32k init settings */ + pwrap_write_field(0x790, 0xF, 0xF, 0); + pwrap_write_field(0x50C, 0x1, 0x1, 0); + + switch (rtc_check_state()) { + case RTC_STATE_REBOOT: + pwrap_write_field(RTC_BBPU, RTC_BBPU_KEY | RTC_BBPU_RELOAD, + 0xFFFF, 0); + write_trigger(); + rtc_osc_init(); + break; + case RTC_STATE_RECOVER: + rtc_init(1); + break; + case RTC_STATE_INIT: + default: + if (!rtc_init(0)) + rtc_init(1); + break; + } + + pwrap_read(RTC_IRQ_STA, &irqsta); /* Read clear */ + pwrap_read(RTC_BBPU, &bbpu); + pwrap_read(RTC_CON, &con); + + printk(BIOS_INFO, "[RTC] irqsta = %x", irqsta); + printk(BIOS_INFO, " bbpu = %#x, con = %#x\n", bbpu, con); + rtc_bbpu_power_on(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/31046 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icccb9360a507fcbfd865b107cd3630e71c810d55 Gerrit-Change-Number: 31046 Gerrit-PatchSet: 1 Gerrit-Owner: Ran Bi <ran.bi(a)mediatek.com> Gerrit-MessageType: newchange

7 19

Change in ...coreboot[master]: Revert "vboot: Fix linking error with USE_OPTION_TABLE enabled"
by Angel Pons (Code Review) 24 Feb '19

24 Feb '19

Hello Aaron Durbin, Patrick Rudolph, Arthur Heymans, Patrick Rudolph, Paul Menzel, Philipp Deppenwiese, build bot (Jenkins), Patrick Georgi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30904 to review the following change. Change subject: Revert "vboot: Fix linking error with USE_OPTION_TABLE enabled" ...................................................................... Revert "vboot: Fix linking error with USE_OPTION_TABLE enabled" This reverts commit 9554b26f9fd608cc613fc3ad869db33ef0edfe5c. Reason for revert: This breaks USB Always On, and no one cared to investigate the issue further. Change-Id: I5a13be56d47dc8373d9c6d556505bb2e3674d4a8 --- M src/drivers/pc80/rtc/mc146818rtc.c M src/lib/cbfs.c M src/security/vboot/Makefile.inc 3 files changed, 18 insertions(+), 71 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/30904/1 diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c index 34db4c3..928b403 100644 --- a/src/drivers/pc80/rtc/mc146818rtc.c +++ b/src/drivers/pc80/rtc/mc146818rtc.c @@ -240,34 +240,9 @@ return CB_SUCCESS; } -static enum cb_err locate_cmos_layout(struct region_device *rdev) -{ - uint32_t cbfs_type = CBFS_COMPONENT_CMOS_LAYOUT; - struct cbfsf fh; - - /* - * In case VBOOT is enabled and this function is called from SMM, - * we have multiple CMOS layout files and to locate them we'd need to - * include VBOOT into SMM... - * - * Support only one CMOS layout in the 'COREBOOT' region for now. - */ - if (cbfs_locate_file_in_region(&fh, "COREBOOT", "cmos_layout.bin", - &cbfs_type)) { - printk(BIOS_ERR, "RTC: cmos_layout.bin could not be found. " - "Options are disabled\n"); - return CB_CMOS_LAYOUT_NOT_FOUND; - } - - cbfs_file_data(rdev, &fh); - - return CB_SUCCESS; -} - enum cb_err get_option(void *dest, const char *name) { struct cmos_option_table *ct; - struct region_device rdev; struct cmos_entries *ce; size_t namelen; int found = 0; @@ -280,20 +255,16 @@ /* Figure out how long name is */ namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); - if (locate_cmos_layout(&rdev) != CB_SUCCESS) { - UNLOCK_NVRAM_CBFS_SPINLOCK(); - return CB_CMOS_LAYOUT_NOT_FOUND; - } - ct = rdev_mmap_full(&rdev); - if (!ct) { - printk(BIOS_ERR, "RTC: cmos_layout.bin could not be mapped. " - "Options are disabled\n"); - - UNLOCK_NVRAM_CBFS_SPINLOCK(); - return CB_CMOS_LAYOUT_NOT_FOUND; - } - /* find the requested entry record */ + ct = cbfs_boot_map_with_leak("cmos_layout.bin", + CBFS_COMPONENT_CMOS_LAYOUT, NULL); + if (!ct) { + printk(BIOS_ERR, "RTC: cmos_layout.bin could not be found. " + "Options are disabled\n"); + + UNLOCK_NVRAM_CBFS_SPINLOCK(); + return CB_CMOS_LAYOUT_NOT_FOUND; + } ce = (struct cmos_entries *)((unsigned char *)ct + ct->header_length); for (; ce->tag == LB_TAG_OPTION; ce = (struct cmos_entries *)((unsigned char *)ce + ce->size)) { @@ -304,22 +275,18 @@ } if (!found) { printk(BIOS_DEBUG, "WARNING: No CMOS option '%s'.\n", name); - rdev_munmap(&rdev, ct); UNLOCK_NVRAM_CBFS_SPINLOCK(); return CB_CMOS_OPTION_NOT_FOUND; } if (!cmos_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END, LB_CKS_LOC)) { - rdev_munmap(&rdev, ct); UNLOCK_NVRAM_CBFS_SPINLOCK(); return CB_CMOS_CHECKSUM_INVALID; } if (get_cmos_value(ce->bit, ce->length, dest) != CB_SUCCESS) { - rdev_munmap(&rdev, ct); UNLOCK_NVRAM_CBFS_SPINLOCK(); return CB_CMOS_ACCESS_ERROR; } - rdev_munmap(&rdev, ct); UNLOCK_NVRAM_CBFS_SPINLOCK(); return CB_SUCCESS; } @@ -380,7 +347,6 @@ enum cb_err set_option(const char *name, void *value) { struct cmos_option_table *ct; - struct region_device rdev; struct cmos_entries *ce; unsigned long length; size_t namelen; @@ -392,20 +358,14 @@ /* Figure out how long name is */ namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); - if (locate_cmos_layout(&rdev) != CB_SUCCESS) { - UNLOCK_NVRAM_CBFS_SPINLOCK(); - return CB_CMOS_LAYOUT_NOT_FOUND; - } - ct = rdev_mmap_full(&rdev); - if (!ct) { - printk(BIOS_ERR, "RTC: cmos_layout.bin could not be mapped. " - "Options are disabled\n"); - - UNLOCK_NVRAM_CBFS_SPINLOCK(); - return CB_CMOS_LAYOUT_NOT_FOUND; - } - /* find the requested entry record */ + ct = cbfs_boot_map_with_leak("cmos_layout.bin", + CBFS_COMPONENT_CMOS_LAYOUT, NULL); + if (!ct) { + printk(BIOS_ERR, "cmos_layout.bin could not be found. " + "Options are disabled\n"); + return CB_CMOS_LAYOUT_NOT_FOUND; + } ce = (struct cmos_entries *)((unsigned char *)ct + ct->header_length); for (; ce->tag == LB_TAG_OPTION; ce = (struct cmos_entries *)((unsigned char *)ce + ce->size)) { @@ -416,7 +376,6 @@ } if (!found) { printk(BIOS_DEBUG, "WARNING: No CMOS option '%s'.\n", name); - rdev_munmap(&rdev, ct); return CB_CMOS_OPTION_NOT_FOUND; } @@ -425,18 +384,13 @@ length = MAX(strlen((const char *)value) * 8, ce->length - 8); /* make sure the string is null terminated */ if (set_cmos_value(ce->bit + ce->length - 8, 8, &(u8[]){0}) - != CB_SUCCESS) { - rdev_munmap(&rdev, ct); + != CB_SUCCESS) return CB_CMOS_ACCESS_ERROR; - } } - if (set_cmos_value(ce->bit, length, value) != CB_SUCCESS) { - rdev_munmap(&rdev, ct); + if (set_cmos_value(ce->bit, length, value) != CB_SUCCESS) return CB_CMOS_ACCESS_ERROR; - } - rdev_munmap(&rdev, ct); return CB_SUCCESS; } diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index ca1fc84..9938e6a 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -321,11 +321,6 @@ static const struct cbfs_locator *locators[] = { #if IS_ENABLED(CONFIG_VBOOT) - /* - * NOTE: Does not link in SMM, as the vboot_locator isn't compiled. - * ATM there's no need for VBOOT functionality in SMM and it's not - * a problem. - */ &vboot_locator, #endif &cbfs_master_header_locator, diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index 75c2a9e..6f18a35 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -154,8 +154,6 @@ font.bin \ vbgfx.bin \ rmu.bin \ - cmos_layout.bin \ - cmos.default \ $(call strip_quotes,$(CONFIG_RO_REGION_ONLY)) \ ,$(1)),COREBOOT,COREBOOT FW_MAIN_A FW_MAIN_B))) -- To view, visit https://review.coreboot.org/c/coreboot/+/30904 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a13be56d47dc8373d9c6d556505bb2e3674d4a8 Gerrit-Change-Number: 30904 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph Gerrit-MessageType: newchange

5 23

Change in ...coreboot[master]: [WIP]drivers/cavium: Add UART PCI driver
by Patrick Rudolph (Code Review) 22 Feb '19

22 Feb '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30608 Change subject: [WIP]drivers/cavium: Add UART PCI driver ...................................................................... [WIP]drivers/cavium: Add UART PCI driver Move PCI handling from cn81xx/soc to its own pci driver. Change-Id: I0fa2f086aba9b4f9c6dba7a35a84ea61c5fa64e4 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- A src/drivers/cavium/pci-cn8xxx/Kconfig A src/drivers/cavium/pci-cn8xxx/Makefile.inc A src/drivers/cavium/pci-cn8xxx/uart.c M src/include/device/pci_ids.h M src/soc/cavium/cn81xx/soc.c 5 files changed, 57 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/30608/1 diff --git a/src/drivers/cavium/pci-cn8xxx/Kconfig b/src/drivers/cavium/pci-cn8xxx/Kconfig new file mode 100644 index 0000000..1de774f --- /dev/null +++ b/src/drivers/cavium/pci-cn8xxx/Kconfig @@ -0,0 +1,7 @@ +config DRIVERS_CAVIUM + bool + depends on SOC_CAVIUM_COMMON + default y if SOC_CAVIUM_COMMON + default n + help + When enabled, adds PCI drivers for Cavium SoCs. diff --git a/src/drivers/cavium/pci-cn8xxx/Makefile.inc b/src/drivers/cavium/pci-cn8xxx/Makefile.inc new file mode 100644 index 0000000..d85fc3e --- /dev/null +++ b/src/drivers/cavium/pci-cn8xxx/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_CAVIUM) += uart.c diff --git a/src/drivers/cavium/pci-cn8xxx/uart.c b/src/drivers/cavium/pci-cn8xxx/uart.c new file mode 100644 index 0000000..2230d5d --- /dev/null +++ b/src/drivers/cavium/pci-cn8xxx/uart.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Facebook, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <device/device.h> +#include <console/console.h> +#include <soc/uart.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +static void cavium_uart_init(struct device *dev) +{ + printk(BIOS_ERR, "UART: debug\n"); + + /* using device enable state from devicetree.cb */ + if (dev->enabled) { + const u8 fn = PCI_FUNC(dev->path.pci.devfn); + + /* Calling uart_setup with no baudrate will do minimal HW + * enough for the kernel to not panic */ + if (!uart_is_enabled(fn)) + uart_setup(fn, 0); + } +} + +static struct device_operations device_ops = { + .init = cavium_uart_init, +}; + +static const struct pci_driver soc_cavium_uart __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_CAVIUM, + .device = PCI_DEVICE_ID_CAVIUM_THUNDERX_UART, +}; diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 751cca0..ba55f1d 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -132,6 +132,9 @@ #define PCI_DEVICE_ID_BERKOM_A4T 0xffa4 #define PCI_DEVICE_ID_BERKOM_SCITEL_QUADRO 0xffa8 +#define PCI_VENDOR_CAVIUM 0x177d +#define PCI_DEVICE_ID_CAVIUM_THUNDERX_UART 0xa00f + #define PCI_VENDOR_ID_COMPAQ 0x0e11 #define PCI_DEVICE_ID_COMPAQ_TOKENRING 0x0508 #define PCI_DEVICE_ID_COMPAQ_1280 0x3033 diff --git a/src/soc/cavium/cn81xx/soc.c b/src/soc/cavium/cn81xx/soc.c index 2046d21..0748096 100644 --- a/src/soc/cavium/cn81xx/soc.c +++ b/src/soc/cavium/cn81xx/soc.c @@ -388,18 +388,6 @@ } } - /* Init UARTs */ - size_t i; - struct device *uart_dev; - for (i = 0; i <= 3; i++) { - uart_dev = dev_find_slot(1, PCI_DEVFN(8, i)); - /* using device enable state from devicetree.cb */ - if (uart_dev && uart_dev->enabled) { - if (!uart_is_enabled(i)) - uart_setup(i, 0); - } - } - if (IS_ENABLED(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE)) soc_init_atf(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/30608 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fa2f086aba9b4f9c6dba7a35a84ea61c5fa64e4 Gerrit-Change-Number: 30608 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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