Change in ...coreboot[master]: mainboard/hp: Add HP Elitebook 8760w as a variant of 8460p - coreboot-gerrit

15 Jan 2019

Hello Iru Cai,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/30936
to review the following change.
Change subject: mainboard/hp: Add HP Elitebook 8760w as a variant of 8460p
......................................................................
mainboard/hp: Add HP Elitebook 8760w as a variant of 8460p
Tested:
- i7-2630QM, 4G
- boots Arch Linux on USB drive from SeaBIOS payload with VGA option
  ROM added
Issues:
- it takes longer time to boot, and the fan is noisier in the boot
  process
Change-Id: Icd49f5c9e17cf8f5ef8c73e73bea111188427590
Signed-off-by: Iru Cai mytbk920423@gmail.com
---
M src/mainboard/hp/8460p/Kconfig
M src/mainboard/hp/8460p/Kconfig.name
M src/mainboard/hp/8460p/Makefile.inc
M src/mainboard/hp/8460p/romstage.c
R src/mainboard/hp/8460p/variants/8460p/devicetree.cb
R src/mainboard/hp/8460p/variants/8460p/gpio.c
A src/mainboard/hp/8460p/variants/8460p/romstage.c
A src/mainboard/hp/8460p/variants/8760w/board_info.txt
A src/mainboard/hp/8460p/variants/8760w/devicetree.cb
A src/mainboard/hp/8460p/variants/8760w/gpio.c
A src/mainboard/hp/8460p/variants/8760w/romstage.c
11 files changed, 495 insertions(+), 34 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/30936/1

diff --git a/src/mainboard/hp/8460p/Kconfig b/src/mainboard/hp/8460p/Kconfig
index 57e6268..5f0d827 100644
--- a/src/mainboard/hp/8460p/Kconfig
+++ b/src/mainboard/hp/8460p/Kconfig
@@ -13,45 +13,57 @@
 # GNU General Public License for more details.
 #
-if BOARD_HP_8460P
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
+config BOARD_HP_BASEBOARD_8460P
+	def_bool n
    select BOARD_ROMSIZE_KB_8192
    select CPU_INTEL_SOCKET_RPGA989
    select HAVE_ACPI_RESUME
    select HAVE_ACPI_TABLES
    select INTEL_INT15
    select NORTHBRIDGE_INTEL_SANDYBRIDGE
-	select SANDYBRIDGE_IVYBRIDGE_LVDS
+	select SANDYBRIDGE_IVYBRIDGE_LVDS if !BOARD_HP_8760W
    select SERIRQ_CONTINUOUS_MODE
    select SOUTHBRIDGE_INTEL_BD82X6X
    select SYSTEM_TYPE_LAPTOP
    select USE_NATIVE_RAMINIT
-	select MAINBOARD_HAS_LIBGFXINIT
+	select MAINBOARD_HAS_LIBGFXINIT if !BOARD_HP_8760W
    select MAINBOARD_HAS_LPC_TPM
    select MAINBOARD_HAS_TPM1
-	select GFX_GMA_INTERNAL_IS_LVDS
+	select GFX_GMA_INTERNAL_IS_LVDS if !BOARD_HP_8760W
    select EC_HP_KBC1126
    select SUPERIO_SMSC_LPC47N217
    select HAVE_OPTION_TABLE
    select HAVE_CMOS_DEFAULT
+if BOARD_HP_BASEBOARD_8460P
+
+config VARIANT_DIR
+	string
+	default "8460p" if BOARD_HP_8460P
+	default "8760w" if BOARD_HP_8760W
+
 config MAINBOARD_DIR
    string
    default hp/8460p
+config DEVICETREE
+	string
+	default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
+
 config MAINBOARD_PART_NUMBER
    string
-	default "EliteBook 8460p"
+	default "EliteBook 8460p" if BOARD_HP_8460P
+	default "EliteBook 8760w" if BOARD_HP_8760W
config VGA_BIOS_FILE
    string
-	default "pci8086,0116.rom"
+	default "pci8086,0116.rom" if BOARD_HP_8460P
+	default "pci10de,0e3a.rom" if BOARD_HP_8760W
config VGA_BIOS_ID
    string
-	default "8086,0116"
+	default "8086,0116" if BOARD_HP_8460P
+	default "10de,0e3a" if BOARD_HP_8760W
config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
    hex
diff --git a/src/mainboard/hp/8460p/Kconfig.name b/src/mainboard/hp/8460p/Kconfig.name
index 94f2fe9..8d48d43 100644
--- a/src/mainboard/hp/8460p/Kconfig.name
+++ b/src/mainboard/hp/8460p/Kconfig.name
@@ -1,2 +1,7 @@
 config BOARD_HP_8460P
    bool "EliteBook 8460p"
+	select BOARD_HP_BASEBOARD_8460P
+
+config BOARD_HP_8760W
+	bool "EliteBook 8760w"
+	select BOARD_HP_BASEBOARD_8460P
diff --git a/src/mainboard/hp/8460p/Makefile.inc b/src/mainboard/hp/8460p/Makefile.inc
index 7a00cce..5819ac0 100644
--- a/src/mainboard/hp/8460p/Makefile.inc
+++ b/src/mainboard/hp/8460p/Makefile.inc
@@ -13,6 +13,7 @@
 ## GNU General Public License for more details.
 ##
-romstage-y += gpio.c
+romstage-y += variants/$(VARIANT_DIR)/gpio.c
+romstage-y += variants/$(VARIANT_DIR)/romstage.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/hp/8460p/romstage.c b/src/mainboard/hp/8460p/romstage.c
index b97d5e4..899ffab 100644
--- a/src/mainboard/hp/8460p/romstage.c
+++ b/src/mainboard/hp/8460p/romstage.c
@@ -42,23 +42,6 @@
 {
 }
-const struct southbridge_usb_port mainboard_usb_ports[] = {
-	{ 1, 1, 0 }, /* USB0, eSATA */
-	{ 1, 0, 0 }, /* USB charger */
-	{ 0, 1, 1 },
-	{ 1, 1, 1 }, /* camera */
-	{ 1, 0, 2 }, /* USB4 expresscard */
-	{ 1, 0, 2 }, /* bluetooth */
-	{ 0, 0, 3 },
-	{ 1, 0, 3 }, /* smartcard */
-	{ 1, 1, 4 }, /* fingerprint */
-	{ 1, 1, 4 }, /* WWAN */
-	{ 1, 0, 5 }, /* CONN */
-	{ 1, 0, 5 }, /* docking */
-	{ 1, 0, 6 }, /* CONN */
-	{ 1, 0, 6 }, /* docking */
-};
-
 void mainboard_early_init(int s3resume)
 {
 }
@@ -73,9 +56,3 @@
    kbc1126_pm1_init();
    kbc1126_exit_conf();
 }
-
-void mainboard_get_spd(spd_raw_data *spd, bool id_only)
-{
-	read_spd(&spd[0], 0x50, id_only);
-	read_spd(&spd[2], 0x52, id_only);
-}
diff --git a/src/mainboard/hp/8460p/devicetree.cb b/src/mainboard/hp/8460p/variants/8460p/devicetree.cb
similarity index 100%
rename from src/mainboard/hp/8460p/devicetree.cb
rename to src/mainboard/hp/8460p/variants/8460p/devicetree.cb
diff --git a/src/mainboard/hp/8460p/gpio.c b/src/mainboard/hp/8460p/variants/8460p/gpio.c
similarity index 100%
rename from src/mainboard/hp/8460p/gpio.c
rename to src/mainboard/hp/8460p/variants/8460p/gpio.c
diff --git a/src/mainboard/hp/8460p/variants/8460p/romstage.c b/src/mainboard/hp/8460p/variants/8460p/romstage.c
new file mode 100644
index 0000000..2221046
--- /dev/null
+++ b/src/mainboard/hp/8460p/variants/8460p/romstage.c
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Iru Cai mytbk920423@gmail.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+	{ 1, 1, 0 }, /* USB0, eSATA */
+	{ 1, 0, 0 }, /* USB charger */
+	{ 0, 1, 1 },
+	{ 1, 1, 1 }, /* camera */
+	{ 1, 0, 2 }, /* USB4 expresscard */
+	{ 1, 0, 2 }, /* bluetooth */
+	{ 0, 0, 3 },
+	{ 1, 0, 3 }, /* smartcard */
+	{ 1, 1, 4 }, /* fingerprint */
+	{ 1, 1, 4 }, /* WWAN */
+	{ 1, 0, 5 }, /* CONN */
+	{ 1, 0, 5 }, /* docking */
+	{ 1, 0, 6 }, /* CONN */
+	{ 1, 0, 6 }, /* docking */
+};
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+	read_spd(&spd[0], 0x50, id_only);
+	read_spd(&spd[2], 0x52, id_only);
+}
diff --git a/src/mainboard/hp/8460p/variants/8760w/board_info.txt b/src/mainboard/hp/8460p/variants/8760w/board_info.txt
new file mode 100644
index 0000000..887ec7b
--- /dev/null
+++ b/src/mainboard/hp/8460p/variants/8760w/board_info.txt
@@ -0,0 +1,7 @@
+Category: laptop
+Board URL: https://support.hp.com/us-en/product/hp-elitebook-8760w-mobile-workstation/5...
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: n
+Release year: 2011
diff --git a/src/mainboard/hp/8460p/variants/8760w/devicetree.cb b/src/mainboard/hp/8460p/variants/8760w/devicetree.cb
new file mode 100644
index 0000000..7d4ba42
--- /dev/null
+++ b/src/mainboard/hp/8460p/variants/8760w/devicetree.cb
@@ -0,0 +1,139 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2019 Iru Cai mytbk920423@gmail.com
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+
+chip northbridge/intel/sandybridge
+	device cpu_cluster 0x0 on
+		chip cpu/intel/socket_rPGA989
+			device lapic 0x0 on
+			end
+		end
+		chip cpu/intel/model_206ax
+			register "c1_acpower" = "1"
+			register "c1_battery" = "1"
+			register "c2_acpower" = "3"
+			register "c2_battery" = "3"
+			register "c3_acpower" = "5"
+			register "c3_battery" = "5"
+			device lapic 0xacac off
+			end
+		end
+	end
+	device domain 0x0 on
+		device pci 00.0 on # Host bridge
+			subsystemid 0x103c 0x1630
+		end
+		device pci 01.0 on # PCIe Bridge for discrete graphics
+			subsystemid 0x8086 0x2010
+		end
+		device pci 02.0 off # Internal graphics
+		end
+		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+			register "c2_latency" = "0x0065"
+			register "docking_supported" = "0"
+			register "gen1_dec" = "0x007c0201"
+			register "gen2_dec" = "0x000c0101"
+			register "gen3_dec" = "0x00fcfe01"
+			register "gen4_dec" = "0x000402e9"
+			register "p_cnt_throttling_supported" = "1"
+			register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
+			register "pcie_port_coalesce" = "1"
+			register "sata_interface_speed_support" = "0x3"
+			# HDD(0, 1), ODD(2), eSATA(4)
+			register "sata_port_map" = "0x3f"
+			register "spi_uvscc" = "0x2005"
+			register "spi_lvscc" = "0"
+			device pci 16.0 on # Management Engine Interface 1
+				subsystemid 0x103c 0x1630
+			end
+			device pci 16.1 off # Management Engine Interface 2
+			end
+			device pci 16.2 off # Management Engine IDE-R
+			end
+			device pci 16.3 off # Management Engine KT
+			end
+			device pci 19.0 on # Intel Gigabit Ethernet
+				subsystemid 0x103c 0x1630
+			end
+			device pci 1a.0 on # USB2 EHCI #2
+				subsystemid 0x103c 0x1630
+			end
+			device pci 1b.0 on # High Definition Audio Audio controller
+				subsystemid 0x103c 0x1630
+			end
+			device pci 1c.0 on # PCIe Port #1, WWAN
+				subsystemid 0x103c 0x1630
+			end
+			device pci 1c.1 on # PCIe Port #2
+				subsystemid 0x103c 0x1630
+			end
+			device pci 1c.2 on # PCIe Port #3, SD/MMC
+				subsystemid 0x103c 0x1630
+			end
+			device pci 1c.3 on # PCIe Port #4, WLAN
+				subsystemid 0x103c 0x1630
+			end
+			device pci 1c.4 off # PCIe Port #5
+			end
+			device pci 1c.5 off # PCIe Port #6
+			end
+			device pci 1c.6 off # PCIe Port #7
+			end
+			device pci 1c.7 on # PCIe Port #8, NEC USB 3.0 Host Controller
+				subsystemid 0x103c 0x1630
+			end
+			device pci 1d.0 on # USB2 EHCI #1
+				subsystemid 0x103c 0x1630
+			end
+			device pci 1e.0 off # PCI bridge
+			end
+			device pci 1f.0 on # LPC bridge PCI-LPC bridge
+				subsystemid 0x103c 0x1630
+				chip ec/hp/kbc1126
+					register "ec_data_port" = "0x60"
+					register "ec_cmd_port" = "0x64"
+					register "ec_ctrl_reg" = "0xca"
+					register "ec_fan_ctrl_value" = "0x9a"
+					device pnp ff.1 off end
+				end # kbc1126
+				chip superio/smsc/lpc47n217
+					device pnp 4e.3 on #  Parallel
+						io 0x60 = 0x378
+						irq 0x70 = 7
+					end
+					device pnp 4e.4 on  #  Com1
+						io 0x60 = 0x3f8
+						irq 0x70 = 4
+					end
+					device pnp 4e.5 off #  Com2
+					end
+				end	#chip superio/smsc/lpc47n217
+
+				chip drivers/pc80/tpm
+					device pnp 0c31.0 on end
+				end
+			end
+			device pci 1f.2 on # SATA Controller 1
+				subsystemid 0x103c 0x1630
+			end
+			device pci 1f.3 off # SMBus
+			end
+			device pci 1f.5 off # SATA Controller 2
+			end
+			device pci 1f.6 off # Thermal
+			end
+		end
+	end
+end
diff --git a/src/mainboard/hp/8460p/variants/8760w/gpio.c b/src/mainboard/hp/8460p/variants/8760w/gpio.c
new file mode 100644
index 0000000..bed7996
--- /dev/null
+++ b/src/mainboard/hp/8460p/variants/8760w/gpio.c
@@ -0,0 +1,236 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Iru Cai mytbk920423@gmail.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0 = GPIO_MODE_GPIO,
+	.gpio1 = GPIO_MODE_GPIO,
+	.gpio2 = GPIO_MODE_GPIO,
+	.gpio3 = GPIO_MODE_GPIO,
+	.gpio4 = GPIO_MODE_GPIO,
+	.gpio5 = GPIO_MODE_NATIVE,
+	.gpio6 = GPIO_MODE_GPIO,
+	.gpio7 = GPIO_MODE_GPIO,
+	.gpio8 = GPIO_MODE_GPIO,
+	.gpio9 = GPIO_MODE_NATIVE,
+	.gpio10 = GPIO_MODE_GPIO,
+	.gpio11 = GPIO_MODE_GPIO,
+	.gpio12 = GPIO_MODE_NATIVE,
+	.gpio13 = GPIO_MODE_GPIO,
+	.gpio14 = GPIO_MODE_GPIO,
+	.gpio15 = GPIO_MODE_GPIO,
+	.gpio16 = GPIO_MODE_GPIO,
+	.gpio17 = GPIO_MODE_GPIO,
+	.gpio18 = GPIO_MODE_NATIVE,
+	.gpio19 = GPIO_MODE_GPIO,
+	.gpio20 = GPIO_MODE_NATIVE,
+	.gpio21 = GPIO_MODE_GPIO,
+	.gpio22 = GPIO_MODE_GPIO,
+	.gpio23 = GPIO_MODE_GPIO,
+	.gpio24 = GPIO_MODE_GPIO,
+	.gpio25 = GPIO_MODE_NATIVE,
+	.gpio26 = GPIO_MODE_NATIVE,
+	.gpio27 = GPIO_MODE_GPIO,
+	.gpio28 = GPIO_MODE_GPIO,
+	.gpio29 = GPIO_MODE_GPIO,
+	.gpio30 = GPIO_MODE_NATIVE,
+	.gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio0 = GPIO_DIR_OUTPUT,
+	.gpio1 = GPIO_DIR_INPUT,
+	.gpio2 = GPIO_DIR_INPUT,
+	.gpio3 = GPIO_DIR_INPUT,
+	.gpio4 = GPIO_DIR_INPUT,
+	.gpio6 = GPIO_DIR_INPUT,
+	.gpio7 = GPIO_DIR_INPUT,
+	.gpio8 = GPIO_DIR_INPUT,
+	.gpio10 = GPIO_DIR_INPUT,
+	.gpio11 = GPIO_DIR_OUTPUT,
+	.gpio13 = GPIO_DIR_INPUT,
+	.gpio14 = GPIO_DIR_INPUT,
+	.gpio15 = GPIO_DIR_INPUT,
+	.gpio16 = GPIO_DIR_INPUT,
+	.gpio17 = GPIO_DIR_OUTPUT,
+	.gpio19 = GPIO_DIR_INPUT,
+	.gpio21 = GPIO_DIR_INPUT,
+	.gpio22 = GPIO_DIR_OUTPUT,
+	.gpio23 = GPIO_DIR_INPUT,
+	.gpio24 = GPIO_DIR_OUTPUT,
+	.gpio27 = GPIO_DIR_OUTPUT,
+	.gpio28 = GPIO_DIR_OUTPUT,
+	.gpio29 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio0 = GPIO_LEVEL_LOW,
+	.gpio11 = GPIO_LEVEL_LOW,
+	.gpio17 = GPIO_LEVEL_HIGH,
+	.gpio22 = GPIO_LEVEL_HIGH,
+	.gpio24 = GPIO_LEVEL_HIGH,
+	.gpio27 = GPIO_LEVEL_LOW,
+	.gpio28 = GPIO_LEVEL_LOW,
+	.gpio29 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+	.gpio24 = GPIO_RESET_RSMRST,
+	.gpio30 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio1 = GPIO_INVERT,
+	.gpio3 = GPIO_INVERT,
+	.gpio6 = GPIO_INVERT,
+	.gpio7 = GPIO_INVERT,
+	.gpio10 = GPIO_INVERT,
+	.gpio13 = GPIO_INVERT,
+	.gpio14 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio32 = GPIO_MODE_NATIVE,
+	.gpio33 = GPIO_MODE_GPIO,
+	.gpio34 = GPIO_MODE_GPIO,
+	.gpio35 = GPIO_MODE_GPIO,
+	.gpio36 = GPIO_MODE_NATIVE,
+	.gpio37 = GPIO_MODE_GPIO,
+	.gpio38 = GPIO_MODE_GPIO,
+	.gpio39 = GPIO_MODE_GPIO,
+	.gpio40 = GPIO_MODE_NATIVE,
+	.gpio41 = GPIO_MODE_NATIVE,
+	.gpio42 = GPIO_MODE_NATIVE,
+	.gpio43 = GPIO_MODE_NATIVE,
+	.gpio44 = GPIO_MODE_GPIO,
+	.gpio45 = GPIO_MODE_NATIVE,
+	.gpio46 = GPIO_MODE_GPIO,
+	.gpio47 = GPIO_MODE_NATIVE,
+	.gpio48 = GPIO_MODE_GPIO,
+	.gpio49 = GPIO_MODE_GPIO,
+	.gpio50 = GPIO_MODE_GPIO,
+	.gpio51 = GPIO_MODE_GPIO,
+	.gpio52 = GPIO_MODE_GPIO,
+	.gpio53 = GPIO_MODE_GPIO,
+	.gpio54 = GPIO_MODE_GPIO,
+	.gpio55 = GPIO_MODE_GPIO,
+	.gpio56 = GPIO_MODE_NATIVE,
+	.gpio57 = GPIO_MODE_GPIO,
+	.gpio58 = GPIO_MODE_NATIVE,
+	.gpio59 = GPIO_MODE_NATIVE,
+	.gpio60 = GPIO_MODE_GPIO,
+	.gpio61 = GPIO_MODE_GPIO,
+	.gpio62 = GPIO_MODE_NATIVE,
+	.gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio33 = GPIO_DIR_OUTPUT,
+	.gpio34 = GPIO_DIR_INPUT,
+	.gpio35 = GPIO_DIR_OUTPUT,
+	.gpio37 = GPIO_DIR_OUTPUT,
+	.gpio38 = GPIO_DIR_INPUT,
+	.gpio39 = GPIO_DIR_INPUT,
+	.gpio44 = GPIO_DIR_INPUT,
+	.gpio46 = GPIO_DIR_INPUT,
+	.gpio48 = GPIO_DIR_INPUT,
+	.gpio49 = GPIO_DIR_OUTPUT,
+	.gpio50 = GPIO_DIR_INPUT,
+	.gpio51 = GPIO_DIR_INPUT,
+	.gpio52 = GPIO_DIR_INPUT,
+	.gpio53 = GPIO_DIR_OUTPUT,
+	.gpio54 = GPIO_DIR_INPUT,
+	.gpio55 = GPIO_DIR_INPUT,
+	.gpio57 = GPIO_DIR_OUTPUT,
+	.gpio60 = GPIO_DIR_OUTPUT,
+	.gpio61 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio33 = GPIO_LEVEL_LOW,
+	.gpio35 = GPIO_LEVEL_LOW,
+	.gpio37 = GPIO_LEVEL_LOW,
+	.gpio49 = GPIO_LEVEL_LOW,
+	.gpio53 = GPIO_LEVEL_HIGH,
+	.gpio57 = GPIO_LEVEL_HIGH,
+	.gpio60 = GPIO_LEVEL_HIGH,
+	.gpio61 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+	.gpio64 = GPIO_MODE_NATIVE,
+	.gpio65 = GPIO_MODE_NATIVE,
+	.gpio66 = GPIO_MODE_NATIVE,
+	.gpio67 = GPIO_MODE_NATIVE,
+	.gpio68 = GPIO_MODE_GPIO,
+	.gpio69 = GPIO_MODE_GPIO,
+	.gpio70 = GPIO_MODE_GPIO,
+	.gpio71 = GPIO_MODE_NATIVE,
+	.gpio72 = GPIO_MODE_GPIO,
+	.gpio73 = GPIO_MODE_GPIO,
+	.gpio74 = GPIO_MODE_GPIO,
+	.gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+	.gpio68 = GPIO_DIR_OUTPUT,
+	.gpio69 = GPIO_DIR_INPUT,
+	.gpio70 = GPIO_DIR_OUTPUT,
+	.gpio72 = GPIO_DIR_OUTPUT,
+	.gpio73 = GPIO_DIR_OUTPUT,
+	.gpio74 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+	.gpio68 = GPIO_LEVEL_HIGH,
+	.gpio70 = GPIO_LEVEL_HIGH,
+	.gpio72 = GPIO_LEVEL_LOW,
+	.gpio73 = GPIO_LEVEL_HIGH,
+	.gpio74 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+	.set1 = {
+		.mode		= &pch_gpio_set1_mode,
+		.direction	= &pch_gpio_set1_direction,
+		.level		= &pch_gpio_set1_level,
+		.blink		= &pch_gpio_set1_blink,
+		.invert		= &pch_gpio_set1_invert,
+		.reset		= &pch_gpio_set1_reset,
+	},
+	.set2 = {
+		.mode		= &pch_gpio_set2_mode,
+		.direction	= &pch_gpio_set2_direction,
+		.level		= &pch_gpio_set2_level,
+		.reset		= &pch_gpio_set2_reset,
+	},
+	.set3 = {
+		.mode		= &pch_gpio_set3_mode,
+		.direction	= &pch_gpio_set3_direction,
+		.level		= &pch_gpio_set3_level,
+		.reset		= &pch_gpio_set3_reset,
+	},
+};
diff --git a/src/mainboard/hp/8460p/variants/8760w/romstage.c b/src/mainboard/hp/8460p/variants/8760w/romstage.c
new file mode 100644
index 0000000..7648c12
--- /dev/null
+++ b/src/mainboard/hp/8460p/variants/8760w/romstage.c
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Iru Cai mytbk920423@gmail.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+	{ 1, 1, 0 }, /* USB charger */
+	{ 1, 1, 0 }, /* CONN */
+	{ 1, 1, 1 }, /* eSATA */
+	{ 1, 1, 1 }, /* camera */
+	{ 1, 0, 2 },
+	{ 1, 0, 2 }, /* bluetooth */
+	{ 0, 0, 3 },
+	{ 1, 0, 3 },
+	{ 1, 1, 4 }, /* fingerprint */
+	{ 1, 1, 4 }, /* WWAN */
+	{ 1, 0, 5 },
+	{ 1, 0, 5 },
+	{ 1, 0, 6 },
+	{ 1, 0, 6 },
+};
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+	read_spd(&spd[0], 0x50, id_only);
+	read_spd(&spd[1], 0x51, id_only);
+	read_spd(&spd[2], 0x52, id_only);
+	read_spd(&spd[3], 0x53, id_only);
+}
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Icd49f5c9e17cf8f5ef8c73e73bea111188427590
Gerrit-Change-Number: 30936
Gerrit-PatchSet: 1
Gerrit-Owner: Iru Cai (vimacs) mytbk920423@gmail.com
Gerrit-Reviewer: Iru Cai mytbk920423@gmail.com
Gerrit-MessageType: newchange



    