coreboot-gerrit January 2019

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Change in ...coreboot[master]: nb/intel/i945: Use macro instead of magic number
by HAOUAS Elyes (Code Review) 11 Apr '19

11 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30993 Change subject: nb/intel/i945: Use macro instead of magic number ...................................................................... nb/intel/i945: Use macro instead of magic number Aslo add comments on Read/Write-Once bits. ULBA register is 64bits, so maybe there is a typo on RCBA(0x114) and it should be 0x11b insted. Change-Id: I3f2199d6da22ce9995496c2a81363710edde81f3 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M 3rdparty/blobs M src/northbridge/intel/i945/early_init.c 2 files changed, 8 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/30993/1 diff --git a/3rdparty/blobs b/3rdparty/blobs index 16058e5..998982d 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit 16058e552279b4884b1f671e7a78752d28abd1cc +Subproject commit 998982d714a08481bb4944f456929be06b5e696f diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 6bfa1c7..70b8152 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -883,10 +883,13 @@ static void ich7_setup_root_complex_topology(void) { - RCBA32(0x104) = 0x00000802; - RCBA32(0x110) = 0x00000001; - RCBA32(0x114) = 0x00000000; - RCBA32(0x118) = 0x00000000; + /* FIXME: ESD [23:16] is R/WO */ + RCBA32(ESD) = 0x00000802; + /* FIXME: ULD [31:16] is R/WO */ + RCBA32(ULD) = 0x00000001; + /* FIXME: ULBA [63:0] is R/WO */ + RCBA32(0x114) = 0x00000000; // RCBA32(0x11b) ? + RCBA32(ULBA) = 0x00000000; } static void ich7_setup_pci_express(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/30993 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f2199d6da22ce9995496c2a81363710edde81f3 Gerrit-Change-Number: 30993 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 18

Change in ...coreboot[master]: Qcs405: Add SPI chip select assert/de-assert in claim/release bus
by Name of user not set (Code Review) 09 Apr '19

09 Apr '19

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31177 Change subject: Qcs405: Add SPI chip select assert/de-assert in claim/release bus ...................................................................... Qcs405: Add SPI chip select assert/de-assert in claim/release bus Add SPI chip select assert/de-assert in claim/release bus. Configure IO in SPI write function and the keep QUP into run state. Add timeout condition in both SPI write and read functions. Change-Id: Ib8fce5f1890ed3693ee0620cbc0e665d82ce3204 Signed-off-by: Prudhvi Yarlagadda <pyarlaga(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/clock.c M src/soc/qualcomm/qcs405/include/soc/qup.h M src/soc/qualcomm/qcs405/spi.c 3 files changed, 97 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/31177/1 diff --git a/src/soc/qualcomm/qcs405/clock.c b/src/soc/qualcomm/qcs405/clock.c index 41f74be..bccefa7 100644 --- a/src/soc/qualcomm/qcs405/clock.c +++ b/src/soc/qualcomm/qcs405/clock.c @@ -63,6 +63,16 @@ }; struct clock_config spi_cfg[] = { + { + .hz = 1000000, + .hw_ctl = 0x0, + .src = SRC_XO_19_2MHZ, + .div = DIV(48), + //.m = 1, + //.n = 2, + //.d_2 = 4, + }, + { .hz = 19200000, .hw_ctl = 0x0, @@ -210,7 +220,7 @@ REG(GCC_APCS_CLOCK_BRANCH_ENA_VOTE), BLSP1_AHB_CLK_ENA); - clock_configure(blsp1_qup4_spi_clk, spi_cfg, 50000000, + clock_configure(blsp1_qup4_spi_clk, spi_cfg, 1000000, ARRAY_SIZE(spi_cfg)); clock_enable(REG(GCC_BLSP1_QUP4_SPI_APPS_CBCR)); clock_enable_vote(REG(GCC_BLSP1_AHB_CBCR), diff --git a/src/soc/qualcomm/qcs405/include/soc/qup.h b/src/soc/qualcomm/qcs405/include/soc/qup.h index 211b44e..5c1c429 100644 --- a/src/soc/qualcomm/qcs405/include/soc/qup.h +++ b/src/soc/qualcomm/qcs405/include/soc/qup.h @@ -71,6 +71,8 @@ #define OUTPUT_FIFO_FULL (1<<6) #define INPUT_FIFO_NOT_EMPTY (1<<5) #define OUTPUT_FIFO_NOT_EMPTY (1<<4) +#define MAX_OUTPUT_DONE_FLAG (1<<10) +#define MAX_INPUT_DONE_FLAG (1<<11) #define INPUT_SERVICE_FLAG (1<<9) #define OUTPUT_SERVICE_FLAG (1<<8) #define QUP_UNPACK_EN (1<<14) diff --git a/src/soc/qualcomm/qcs405/spi.c b/src/soc/qualcomm/qcs405/spi.c index bd88462..1038881 100644 --- a/src/soc/qualcomm/qcs405/spi.c +++ b/src/soc/qualcomm/qcs405/spi.c @@ -36,6 +36,7 @@ #include <stdlib.h> #include <string.h> #include <spi_flash.h> +#include <timer.h> static const struct blsp_spi spi_reg[] = { /* BLSP0 registers for SPI interface */ @@ -320,47 +321,6 @@ return SUCCESS; } -static int spi_ctrlr_claim_bus(const struct spi_slave *slave) -{ - struct ipq_spi_slave *ds = to_ipq_spi(slave); - unsigned int ret; - - ret = spi_hw_init(ds); - if (ret) - return -EIO; - switch(slave->bus) { - case 5: - - gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); - gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); - gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); - gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); - - break; - case 4: - gpio_configure(GPIO(37), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); - gpio_configure(GPIO(38), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); - gpio_configure(GPIO(117), 2, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); - gpio_configure(GPIO(118), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); - break; - default: - printk(BIOS_ERR, "SPI error: unsupported bus %d (Supported busses 0, 1, 2, 3, 4, 5) ", slave->bus); - break; - } - - - return SUCCESS; -} - -static void spi_ctrlr_release_bus(const struct spi_slave *slave) -{ - struct ipq_spi_slave *ds = to_ipq_spi(slave); - - /* Reset the SPI hardware */ - spi_reset(ds); - ds->initialized = 0; -} - static void write_force_cs(const struct spi_slave *slave, int assert) { struct ipq_spi_slave *ds = to_ipq_spi(slave); @@ -380,6 +340,56 @@ return; } + +static int spi_ctrlr_claim_bus(const struct spi_slave *slave) +{ + struct ipq_spi_slave *ds = to_ipq_spi(slave); + unsigned int ret; + + ret = spi_hw_init(ds); + if (ret) + return -EIO; + switch(slave->bus) { + case 4: + gpio_configure(GPIO(37), 2, + GPIO_PULL_DOWN, GPIO_6MA, GPIO_INPUT); //MISO - IN + gpio_configure(GPIO(38), 2, + GPIO_PULL_DOWN, GPIO_6MA, GPIO_OUTPUT); //MOSI - Out + gpio_configure(GPIO(117), 2, + GPIO_NO_PULL, GPIO_6MA, GPIO_OUTPUT); //SCLK - out + gpio_configure(GPIO(118), 2, + GPIO_PULL_DOWN, GPIO_6MA, GPIO_OUTPUT); //CS_0 - out + + break; + case 5: + + gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); + gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); + gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); + gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); + + break; + default: + printk(BIOS_ERR, "SPI error: unsupported bus %d (Supported busses 0, 1, 2, 3, 4, 5) ", slave->bus); + break; + } + + write_force_cs(slave, 1); + + + return SUCCESS; +} + +static void spi_ctrlr_release_bus(const struct spi_slave *slave) +{ + struct ipq_spi_slave *ds = to_ipq_spi(slave); + + /* Reset the SPI hardware */ + write_force_cs(slave, 0); + spi_reset(ds); + ds->initialized = 0; +} + /* * Function to write data to OUTPUT FIFO */ @@ -465,6 +475,7 @@ unsigned int fifo_count; int ret = SUCCESS; int state_config; + struct stopwatch sw; /* Configure no of bytes to read */ state_config = config_spi_state(ds, QUP_STATE_RESET); @@ -505,6 +516,18 @@ } } + stopwatch_init_msecs_expire(&sw, 10); + + do { + val = read32(ds->regs->qup_operational); + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "SPI FIFO read timeout \n"); + ret = -ETIMEDOUT; + goto out; + } + + }while(!(val & MAX_INPUT_DONE_FLAG)); + out: /* * Put the SPI Core back in the Reset State @@ -542,15 +565,18 @@ uint32_t val; unsigned int i; unsigned int write_len = bytes; - unsigned int read_len = 3; //bytes; hack for now + unsigned int read_len = bytes; //hack for now unsigned int fifo_count; int ret = SUCCESS; int state_config; + struct stopwatch sw; state_config = config_spi_state(ds, QUP_STATE_RESET); if (state_config) return state_config; + /* Configure input and output enable */ + enable_io_config(ds, write_len, read_len); /* No of bytes to be written in Output FIFO */ write32(ds->regs->qup_mx_output_count, bytes); write32(ds->regs->qup_mx_input_count, bytes); @@ -558,9 +584,6 @@ if (state_config) return state_config; - /* Configure input and output enable */ - enable_io_config(ds, write_len, read_len); - /* * read_len considered to ensure that we read the dummy data for the * write we performed. This is needed to ensure with WR-RD transaction @@ -620,6 +643,18 @@ } } + stopwatch_init_msecs_expire(&sw, 10); + + do { + val = read32(ds->regs->qup_operational); + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "SPI FIFO write timeout \n"); + ret = -ETIMEDOUT; + goto out; + } + + }while(!(val & MAX_OUTPUT_DONE_FLAG)); + out: /* * Put the SPI Core back in the Reset State @@ -639,8 +674,10 @@ length = (bytes < MAX_COUNT_SIZE) ? bytes : MAX_COUNT_SIZE; ret = __blsp_spi_write(ds, cmd_buffer, length); - if (ret != SUCCESS) + if (ret != SUCCESS) { + printk(BIOS_ERR, "SPI:DBG write not success \n"); return ret; + } cmd_buffer += length; bytes -= length; @@ -670,8 +707,6 @@ if (ret != SUCCESS) return ret; - write_force_cs(slave, 1); - if (dout != NULL) { ret = blsp_spi_write(ds, txp, (unsigned int) out_bytes); if (ret != SUCCESS) @@ -685,7 +720,6 @@ } out: - write_force_cs(slave, 0); /* * Put the SPI Core back in the Reset State @@ -750,7 +784,7 @@ .setup = spi_ctrlr_setup, .claim_bus = spi_ctrlr_claim_bus, .release_bus = spi_ctrlr_release_bus, - //.xfer = spi_ctrlr_xfer, + .xfer = spi_ctrlr_xfer, .xfer_vector = xfer_vectors, .max_xfer_size = MAX_PACKET_COUNT, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/31177 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8fce5f1890ed3693ee0620cbc0e665d82ce3204 Gerrit-Change-Number: 31177 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

3 8

Change in ...coreboot[master]: qcs405: Reduce the reserved memory size
by Name of user not set (Code Review) 09 Apr '19

09 Apr '19

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31176 Change subject: qcs405: Reduce the reserved memory size ...................................................................... qcs405: Reduce the reserved memory size Lets us reserve only for ATF use and give the rest back to Kernel Change-Id: Ibe576b4934e9aa3e5bf1bda71d65c496b42e10f0 Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/include/soc/memlayout.ld 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/31176/1 diff --git a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld index 46d4673..ace2e70 100644 --- a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld +++ b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld @@ -56,7 +56,7 @@ DRAM_START(0x80000000) /* Various hardware/software subsystems make use of this area */ - REGION(dram_reserved, 0x85000000, 0x1A800000, 4096) + REGION(dram_reserved, 0x86000000, 0x400000, 4096) POSTRAM_CBFS_CACHE(0x9F800000, 384K) RAMSTAGE(0x9F860000, 128K) } -- To view, visit https://review.coreboot.org/c/coreboot/+/31176 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe576b4934e9aa3e5bf1bda71d65c496b42e10f0 Gerrit-Change-Number: 31176 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

2 4

Change in ...coreboot[master]: Qcs405: Add SPI chip select assert/de-assert in claim/release bus
by Name of user not set (Code Review) 09 Apr '19

09 Apr '19

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31142 Change subject: Qcs405: Add SPI chip select assert/de-assert in claim/release bus ...................................................................... Qcs405: Add SPI chip select assert/de-assert in claim/release bus Add SPI chip select assert/de-assert in claim/release bus. Configure IO in SPI write function and the keep QUP into run state. Add timeout condition in both SPI write and read functions. Change-Id: Iaeb9046f6c4f89c0c1bfa72374b5134eafd1a9dd Signed-off-by: Prudhvi Yarlagadda <pyarlaga(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/clock.c M src/soc/qualcomm/qcs405/include/soc/qup.h M src/soc/qualcomm/qcs405/spi.c 3 files changed, 97 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/31142/1 diff --git a/src/soc/qualcomm/qcs405/clock.c b/src/soc/qualcomm/qcs405/clock.c index 41f74be..bccefa7 100644 --- a/src/soc/qualcomm/qcs405/clock.c +++ b/src/soc/qualcomm/qcs405/clock.c @@ -63,6 +63,16 @@ }; struct clock_config spi_cfg[] = { + { + .hz = 1000000, + .hw_ctl = 0x0, + .src = SRC_XO_19_2MHZ, + .div = DIV(48), + //.m = 1, + //.n = 2, + //.d_2 = 4, + }, + { .hz = 19200000, .hw_ctl = 0x0, @@ -210,7 +220,7 @@ REG(GCC_APCS_CLOCK_BRANCH_ENA_VOTE), BLSP1_AHB_CLK_ENA); - clock_configure(blsp1_qup4_spi_clk, spi_cfg, 50000000, + clock_configure(blsp1_qup4_spi_clk, spi_cfg, 1000000, ARRAY_SIZE(spi_cfg)); clock_enable(REG(GCC_BLSP1_QUP4_SPI_APPS_CBCR)); clock_enable_vote(REG(GCC_BLSP1_AHB_CBCR), diff --git a/src/soc/qualcomm/qcs405/include/soc/qup.h b/src/soc/qualcomm/qcs405/include/soc/qup.h index 211b44e..5c1c429 100644 --- a/src/soc/qualcomm/qcs405/include/soc/qup.h +++ b/src/soc/qualcomm/qcs405/include/soc/qup.h @@ -71,6 +71,8 @@ #define OUTPUT_FIFO_FULL (1<<6) #define INPUT_FIFO_NOT_EMPTY (1<<5) #define OUTPUT_FIFO_NOT_EMPTY (1<<4) +#define MAX_OUTPUT_DONE_FLAG (1<<10) +#define MAX_INPUT_DONE_FLAG (1<<11) #define INPUT_SERVICE_FLAG (1<<9) #define OUTPUT_SERVICE_FLAG (1<<8) #define QUP_UNPACK_EN (1<<14) diff --git a/src/soc/qualcomm/qcs405/spi.c b/src/soc/qualcomm/qcs405/spi.c index bd88462..1038881 100644 --- a/src/soc/qualcomm/qcs405/spi.c +++ b/src/soc/qualcomm/qcs405/spi.c @@ -36,6 +36,7 @@ #include <stdlib.h> #include <string.h> #include <spi_flash.h> +#include <timer.h> static const struct blsp_spi spi_reg[] = { /* BLSP0 registers for SPI interface */ @@ -320,47 +321,6 @@ return SUCCESS; } -static int spi_ctrlr_claim_bus(const struct spi_slave *slave) -{ - struct ipq_spi_slave *ds = to_ipq_spi(slave); - unsigned int ret; - - ret = spi_hw_init(ds); - if (ret) - return -EIO; - switch(slave->bus) { - case 5: - - gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); - gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); - gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); - gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); - - break; - case 4: - gpio_configure(GPIO(37), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); - gpio_configure(GPIO(38), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); - gpio_configure(GPIO(117), 2, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); - gpio_configure(GPIO(118), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); - break; - default: - printk(BIOS_ERR, "SPI error: unsupported bus %d (Supported busses 0, 1, 2, 3, 4, 5) ", slave->bus); - break; - } - - - return SUCCESS; -} - -static void spi_ctrlr_release_bus(const struct spi_slave *slave) -{ - struct ipq_spi_slave *ds = to_ipq_spi(slave); - - /* Reset the SPI hardware */ - spi_reset(ds); - ds->initialized = 0; -} - static void write_force_cs(const struct spi_slave *slave, int assert) { struct ipq_spi_slave *ds = to_ipq_spi(slave); @@ -380,6 +340,56 @@ return; } + +static int spi_ctrlr_claim_bus(const struct spi_slave *slave) +{ + struct ipq_spi_slave *ds = to_ipq_spi(slave); + unsigned int ret; + + ret = spi_hw_init(ds); + if (ret) + return -EIO; + switch(slave->bus) { + case 4: + gpio_configure(GPIO(37), 2, + GPIO_PULL_DOWN, GPIO_6MA, GPIO_INPUT); //MISO - IN + gpio_configure(GPIO(38), 2, + GPIO_PULL_DOWN, GPIO_6MA, GPIO_OUTPUT); //MOSI - Out + gpio_configure(GPIO(117), 2, + GPIO_NO_PULL, GPIO_6MA, GPIO_OUTPUT); //SCLK - out + gpio_configure(GPIO(118), 2, + GPIO_PULL_DOWN, GPIO_6MA, GPIO_OUTPUT); //CS_0 - out + + break; + case 5: + + gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); + gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); + gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); + gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); + + break; + default: + printk(BIOS_ERR, "SPI error: unsupported bus %d (Supported busses 0, 1, 2, 3, 4, 5) ", slave->bus); + break; + } + + write_force_cs(slave, 1); + + + return SUCCESS; +} + +static void spi_ctrlr_release_bus(const struct spi_slave *slave) +{ + struct ipq_spi_slave *ds = to_ipq_spi(slave); + + /* Reset the SPI hardware */ + write_force_cs(slave, 0); + spi_reset(ds); + ds->initialized = 0; +} + /* * Function to write data to OUTPUT FIFO */ @@ -465,6 +475,7 @@ unsigned int fifo_count; int ret = SUCCESS; int state_config; + struct stopwatch sw; /* Configure no of bytes to read */ state_config = config_spi_state(ds, QUP_STATE_RESET); @@ -505,6 +516,18 @@ } } + stopwatch_init_msecs_expire(&sw, 10); + + do { + val = read32(ds->regs->qup_operational); + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "SPI FIFO read timeout \n"); + ret = -ETIMEDOUT; + goto out; + } + + }while(!(val & MAX_INPUT_DONE_FLAG)); + out: /* * Put the SPI Core back in the Reset State @@ -542,15 +565,18 @@ uint32_t val; unsigned int i; unsigned int write_len = bytes; - unsigned int read_len = 3; //bytes; hack for now + unsigned int read_len = bytes; //hack for now unsigned int fifo_count; int ret = SUCCESS; int state_config; + struct stopwatch sw; state_config = config_spi_state(ds, QUP_STATE_RESET); if (state_config) return state_config; + /* Configure input and output enable */ + enable_io_config(ds, write_len, read_len); /* No of bytes to be written in Output FIFO */ write32(ds->regs->qup_mx_output_count, bytes); write32(ds->regs->qup_mx_input_count, bytes); @@ -558,9 +584,6 @@ if (state_config) return state_config; - /* Configure input and output enable */ - enable_io_config(ds, write_len, read_len); - /* * read_len considered to ensure that we read the dummy data for the * write we performed. This is needed to ensure with WR-RD transaction @@ -620,6 +643,18 @@ } } + stopwatch_init_msecs_expire(&sw, 10); + + do { + val = read32(ds->regs->qup_operational); + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "SPI FIFO write timeout \n"); + ret = -ETIMEDOUT; + goto out; + } + + }while(!(val & MAX_OUTPUT_DONE_FLAG)); + out: /* * Put the SPI Core back in the Reset State @@ -639,8 +674,10 @@ length = (bytes < MAX_COUNT_SIZE) ? bytes : MAX_COUNT_SIZE; ret = __blsp_spi_write(ds, cmd_buffer, length); - if (ret != SUCCESS) + if (ret != SUCCESS) { + printk(BIOS_ERR, "SPI:DBG write not success \n"); return ret; + } cmd_buffer += length; bytes -= length; @@ -670,8 +707,6 @@ if (ret != SUCCESS) return ret; - write_force_cs(slave, 1); - if (dout != NULL) { ret = blsp_spi_write(ds, txp, (unsigned int) out_bytes); if (ret != SUCCESS) @@ -685,7 +720,6 @@ } out: - write_force_cs(slave, 0); /* * Put the SPI Core back in the Reset State @@ -750,7 +784,7 @@ .setup = spi_ctrlr_setup, .claim_bus = spi_ctrlr_claim_bus, .release_bus = spi_ctrlr_release_bus, - //.xfer = spi_ctrlr_xfer, + .xfer = spi_ctrlr_xfer, .xfer_vector = xfer_vectors, .max_xfer_size = MAX_PACKET_COUNT, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/31142 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaeb9046f6c4f89c0c1bfa72374b5134eafd1a9dd Gerrit-Change-Number: 31142 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

2 2

Change in ...coreboot[master]: mistral: qcs405: Updated the layout info as in Gale
by Name of user not set (Code Review) 09 Apr '19

09 Apr '19

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30902 Change subject: mistral: qcs405: Updated the layout info as in Gale ...................................................................... mistral: qcs405: Updated the layout info as in Gale Changed the Mistral's layout as in Gale. Change-Id: I61a82bd8dc6a2f86b72beb8efedaee35897fd66f Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/mainboard/google/mistral/chromeos.fmd 1 file changed, 24 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/30902/1 diff --git a/src/mainboard/google/mistral/chromeos.fmd b/src/mainboard/google/mistral/chromeos.fmd index e8b9978..a9bdd7b 100644 --- a/src/mainboard/google/mistral/chromeos.fmd +++ b/src/mainboard/google/mistral/chromeos.fmd @@ -1,52 +1,33 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2018, The Linux Foundation. All rights reserved. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License version 2 and -## only version 2 as published by the Free Software Foundation. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - FLASH@0x0 0x800000 { - WP_RO@0x0 0x300000 { - RO_SECTION@0x0 0x2FE000 { - BOOTBLOCK@0 248K - COREBOOT(CBFS)@0x3E000 0x1E0000 - FMAP@0x21E000 0x1000 - GBB@0x21F000 0xDEF00 - RO_FRID@0x2FDF00 0x100 + WP_RO@0x0 0x400000 { + RO_SECTION@0x0 0x3e0000 { + BOOTBLOCK@0 128K + COREBOOT(CBFS)@0x20000 0x2e0000 + FMAP@0x300000 0x1000 + GBB@0x301000 0xdef00 + RO_FRID@0x3dff00 0x100 } - RO_VPD@0x2FE000 0x2000 + RO_VPD@0x3e0000 0x20000 } - - RW_NVRAM@0x300000 0x8000 - RW_ELOG@0x308000 0x8000 - RW_VPD@0x310000 0x8000 - RW_CDT@0x318000 0x8000 - - RW_SECTION_A@0x320000 0x268000 { + RW_SECTION_A@0x400000 0x160000 { VBLOCK_A@0x0 0x2000 - FW_MAIN_A(CBFS)@0x2000 0x1E1F00 - RW_FWID_A@0x1E3F00 0x100 - RW_DDR_TRAINING_A@0x1E4000 0x4000 - RW_XBL_BUFFER_A@0x1E8000 0x4000 + FW_MAIN_A(CBFS)@0x2000 0x14df00 + RW_FWID_A@0x14ff00 0x100 + RW_SHARED@0x150000 0x10000 { + SHARED_DATA@0x0 0x10000 + } } - - RW_SHARED@0x588000 0x10000 { - SHARED_DATA@0x0 0x10000 + RW_GPT@0x560000 0x20000 { + RW_GPT_PRIMARY@0x0 0x10000 + RW_GPT_SECONDARY@0x10000 0x10000 } - - RW_SECTION_B@0x598000 0x268000 { + RW_SECTION_B@0x580000 0x160000 { VBLOCK_B@0x0 0x2000 - FW_MAIN_B(CBFS)@0x2000 0x1E1F00 - RW_FWID_B@0x1E3F00 0x100 - RW_DDR_TRAINING_B@0x1E4000 0x4000 - RW_XBL_BUFFER_B@0x1E8000 0x4000 + FW_MAIN_B(CBFS)@0x2000 0x14df00 + RW_FWID_B@0x14ff00 0x100 } + RW_VPD@0x6e0000 0x8000 + RW_ELOG@0x6e8000 0x8000 + RW_NVRAM@0x6f0000 0x10000 + RW_LEGACY(CBFS)@0x700000 0x100000 } -- To view, visit https://review.coreboot.org/c/coreboot/+/30902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61a82bd8dc6a2f86b72beb8efedaee35897fd66f Gerrit-Change-Number: 30902 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Little bit more helpful, giving back the lines for each file if any
by Balázs Vinarz (Code Review) 02 Apr '19

02 Apr '19

Balázs Vinarz has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30988 Change subject: Little bit more helpful, giving back the lines for each file if any ...................................................................... Little bit more helpful, giving back the lines for each file if any Change-Id: I8ae13f62c6e2cd87278fefab8de5faf0d1bc0a90 --- M util/lint/lint-stable-003-whitespace 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/30988/1 diff --git a/util/lint/lint-stable-003-whitespace b/util/lint/lint-stable-003-whitespace index f9b7891..b2011e7 100755 --- a/util/lint/lint-stable-003-whitespace +++ b/util/lint/lint-stable-003-whitespace @@ -20,7 +20,7 @@ # shellcheck disable=SC2086,SC2046 if uname | grep -qi "linux"; then - grep -l "[[:space:]][[:space:]]*$" \ + grep -n -H "[[:space:]][[:space:]]*$" \ $(git ls-files $INCLUDELIST | \ grep -Ev "($EXCLUDELIST)" ) | \ sed -e "s,^.*$,File & has lines ending with whitespace.," -- To view, visit https://review.coreboot.org/c/coreboot/+/30988 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ae13f62c6e2cd87278fefab8de5faf0d1bc0a90 Gerrit-Change-Number: 30988 Gerrit-PatchSet: 1 Gerrit-Owner: Balázs Vinarz <vinibali1(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/qualcomm/qcs405: Define a Kconfig variable that the code is missing
by Patrick Georgi (Code Review) 27 Mar '19

27 Mar '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30964 Change subject: soc/qualcomm/qcs405: Define a Kconfig variable that the code is missing ...................................................................... soc/qualcomm/qcs405: Define a Kconfig variable that the code is missing It's used in the code but never defined, which trips up the linter. We need to sort it out before the patch train gets in, but until then, the linter is mostly creating noise. Change-Id: Ib04d5b6d2cb03cc8ee6ef0275e1b201c0fc9eb6d Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/soc/qualcomm/qcs405/Kconfig 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/30964/1 diff --git a/src/soc/qualcomm/qcs405/Kconfig b/src/soc/qualcomm/qcs405/Kconfig index b24dc9e..ea1cee4 100644 --- a/src/soc/qualcomm/qcs405/Kconfig +++ b/src/soc/qualcomm/qcs405/Kconfig @@ -21,6 +21,13 @@ select VBOOT_OPROM_MATTERS select VBOOT_STARTS_IN_BOOTBLOCK +config QC_SDI_ENABLE + bool + default n + help + dummy entry because that variable isn't _really_ used yet. + todo(pgeorgi): check if used before merging + config QC_SOC_SIMULATE bool prompt "Build for Early Simulation Environment" -- To view, visit https://review.coreboot.org/c/coreboot/+/30964 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib04d5b6d2cb03cc8ee6ef0275e1b201c0fc9eb6d Gerrit-Change-Number: 30964 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

1 2

Change in ...coreboot[master]: mistral: qcs405: copy calibration data to CBMEM
by Name of user not set (Code Review) 20 Mar '19

20 Mar '19

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30714 Change subject: mistral: qcs405: copy calibration data to CBMEM ...................................................................... mistral: qcs405: copy calibration data to CBMEM This pacth adds support to copy the wifi calibration data to CBMEM so that the depthcharge can use it to populate the data into wifi dt node. Change-Id: Ia8184e48a7176bb3b52e4d43866b7d065952c13e Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/mainboard/google/mistral/mainboard.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/30714/1 diff --git a/src/mainboard/google/mistral/mainboard.c b/src/mainboard/google/mistral/mainboard.c index f4fc31e..3605fba 100644 --- a/src/mainboard/google/mistral/mainboard.c +++ b/src/mainboard/google/mistral/mainboard.c @@ -17,6 +17,7 @@ #include <bootblock_common.h> #include <timestamp.h> #include <soc/usb.h> +#include <vendorcode/google/chromeos/chromeos.h> #if 0 static struct usb_board_data usb0_board_data = { @@ -46,6 +47,10 @@ static void mainboard_init(device_t dev) { setup_usb(); + if (IS_ENABLED(CONFIG_CHROMEOS)) { + /* Copy WIFI calibration data into CBMEM. */ + cbmem_add_vpd_calibration_data(); + } } static void mainboard_enable(device_t dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/30714 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8184e48a7176bb3b52e4d43866b7d065952c13e Gerrit-Change-Number: 30714 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

2 5

Change in ...coreboot[master]: util/autoport: Rewrite readme.md
by Angel Pons (Code Review) 18 Mar '19

18 Mar '19

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30969 Change subject: util/autoport: Rewrite readme.md ...................................................................... util/autoport: Rewrite readme.md The last part of the file has not been modified much. Change-Id: Icc45824d5d1298146f459d75f0a5121dbdd70d41 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/autoport/readme.md 1 file changed, 195 insertions(+), 144 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/30969/1 diff --git a/util/autoport/readme.md b/util/autoport/readme.md index 226fcda..4683d8d 100644 --- a/util/autoport/readme.md +++ b/util/autoport/readme.md @@ -6,23 +6,27 @@ For any Sandy Bridge or Ivy Bridge platform the generated result should be bootable, possibly with minor fixes. -### EC +### EC / SuperIO EC support is likely to work on Intel-based thinkpads. Other laptops are -likely to miss EC support. +likely to miss EC support. SuperIO support on desktops is more likely to +work out of the box than any EC. -## How to use +## How to use autoport -* Go into BIOS setup on the target machine and enable all devices. -This will allow autoport to detect as much as possible. -* Boot into target machine under GNU/Linux -* Make sure that the following components are installed: - * GCC - * golang - * lspci - * dmidecode - * acpidump -* Grab coreboot tree -* Execute following commands starting from coreboot tree +Enable as many devices as possible in the firmware setup of your system. +This is useful to detect as many devices as possible and make the port +more complete, as disabled devices cannot be detected. + +Boot into target machine under any Linux-based distribution and install +the following tools on it: +* `gcc` +* `golang` +* `lspci` +* `dmidecode` +* `acpidump` (part of `acpica` on some distros) + +Clone the coreboot tree and `cd` into it. For more detailed steps, refer +to Rookie Guide, Lesson 1. Afterwards, run these commands: cd util/ectool make @@ -34,60 +38,89 @@ go build sudo ./autoport --input_log=logs --make_logs --coreboot_dir=../.. - Note: in case you have problems getting gcc and golang to target machine - you can just compile on another machine and transfer the binaries - `autoport`, `inteltool` and `ectool`. You'll still need other prerequisites - but you may place them in the same directory as autoport. + Note: in case you have problems getting gcc and golang on the target + machine, you can compile the utilities on another computer and copy + the binaries to the target machine. You will still need the other + listed programs on the target machine, but you may place them in the + same directory as autoport. -* Look for output unknown PCI devices. E.g. +Check for unknown detected PCI devices, e.g.: Unknown PCI device 8086:0085, assuming removable -If autoport says `assuming removable` then you're fine. If it doesn't -then you may want to add relevant PCIIDs to autoport. When rerunning -you can skip argument `--make_logs` to reuse the same logs +If autoport says `assuming removable`, you are fine. If it doesn't, +you may want to add the relevant PCI IDs to autoport. Run `lspci -nn` +and check which device this is using the PCI ID. Devices which are not +part of the chipset, such as GPUs or network cards, can be considered +removable, whereas devices inside the CPU or the PCH such as integrated +GPUs and bus controllers (SATA, USB, LPC, SMBus...) are non-removable. -* At this point the new board is added to the tree but don't flash it -yet as it will brick your machine. Instead keep this new port and the logs -from `util/autoport/logs` somewhere safe. +Your board has now been added to the tree. However, do not flash it +in its current state. It can brick your machine. Instead, keep this +new port and the logs from `util/autoport/logs` somewhere safe. The +following steps will back up your current firmware, which is always +recommended, since coreboot may not boot on the first try. -* Disassemble your laptop and locate flash chip <http://flashrom.org/Technology> -is a great resource. The flash chip is usually in `SOIC-8` (2x4 pins) or `SOIC-16` -(2x8 chips). You'll probably have several candidates. Look up what's written on -them and look up what's this chip on the web. +Disassemble your computer and find the flash chip(s). Since there could be +more than one, this guide will refer to "flash chips" as one or more chips. +Refer to <http://flashrom.org/Technology> as a reference. The flash chip is +usually in a `SOIC-8` (2x4 pins, 200mil) or `SOIC-16` (2x8 pins) package. As +it can be seen on flashrom's wiki, the former package is like any other 8-pin +chip on the mainboard, but it is slightly larger. The latter package is much +easier to locate. Always make sure it is a flash chip by looking up what its +model, printed on it, refers to. -* Once you know what's the chip is, get an external flasher and read it. Twice. Compare -the results and retry if they differ. Save the result somewhere safe, in preference -copy it to read-only storage as backup. +There may be a smaller flash chip for the EC on some laptops, and other chips +such as network cards may use similar flash chips. These should be left as-is. +If in doubt, ask! -* Compile coreboot with console enabled (EHCI debug or serial if present are recommended) +Once located, use an external flasher to read the flash chips with `flashrom -r`. +Verify with `flashrom -v` several times that reading is consistent. If it is not, +troubleshoot your flashing setup. Save the results somewhere safe, preferably on +media that cannot be easily overwritten and on several devices. You may need this +later. The write process erases the flash chips first, and erased data on a flash +chip is lost for a very long time, usually forever! -* For recent Intel chipsets you need to avoid overwriting ME firmware. Recommended procedure is -(replace 8 with your flash size in MiB): +Compile coreboot for your ported mainboard with some console enabled. The most +common ones are EHCI debug, serial port and SPI flash console as a last resort. +If your system is a laptop and has a dedicated video card, you may need to add +a video BIOS (VBIOS) to coreboot to be able to see any video output. Desktop +video cards, as well as some MXM video cards, have this VBIOS on a flash chip +on the card's PCB, so this step is not necessary for them. - cp backup.rom flash.rom - dd if=coreboot/build/coreboot.rom skip=$[8-1] seek=$[8-1] bs=1M of=flash.rom +Flash coreboot on the machine. On recent Intel chipsets, the flash space is split +in several regions. Only the one known as "BIOS region" should be flashed. If +there is only one flash chip present, this is best done by adding the `--ifd` +and `-i bios` parameters flashrom has (from v1.0 onwards) to specify what flash +descriptor region it should operate on. If the ME (Management Engine) region is +not readable, which is the case on most systems, use the `--noverify-all` +parameter as well. -* Flash the result -* Boot and grab the log and fix the issues. See next section for useful info. -* grep your board for FIXME. autoport adds comments when it's unsure. Sometimes it's just -a minor check and sometimes it needs more involvment. See next section. -* Send new board to review.coreboot.org. I mean it, your effort is very appreciated. +For systems with two flash chips, this is not so easy. It is probably better to +ask in coreboot or flashrom communication channels, such as via IRC or on the +mailing lists. + +Once flashed, try to boot. Anything is possible. If a log is generated, save it +and use it to address any issues. See the next section for useful information. +Find all the sections marked with `FIXME` and correct them. + +Send your work to review.coreboot.org. I mean it, your effort is very appreciated. +Refer to Rookie Guide, Lesson 2 for instructions on how to submit a patch. ## Manual fixes ### SPD -If you're able to use full memory with any combination of inserted modules than this is -most likely correct. In order to initialize the memory coreboot needs to know RAM timings. -For socketed RAM it's stored in a small EEPROM chip which can be accessed through SPD. Unfortunately -mapping between SPD addresses and RAM slots differs and cannot always be detected automatically. -Resulting SPD map is encoded in function `mainboard_get_spd` in `romstage.c`. -autoport uses the most common map `0x50, 0x51, 0x52, 0x53` except for lenovos which are -known to use `0x50, 0x52, 0x51, 0x53`. To detect the correct memory map the easiest way is with -vendor BIOS to boot with just one module in channel 0 slot 0 and then see where does it show -up in SPD. Under Linux you can see present SPD addresses with following commands: +In order to initialize the RAM memory, coreboot needs to know its timings, which vary between +modules. Socketed RAM has a small EEPROM chip, which is accessible via SMBus and contains the +timing data. This data is usually known as SPD. Unfortunately, the SMBus addresses may not +correlate with the RAM slots and cannot always be detected automatically. The address map is +encoded in function `mainboard_get_spd` in `romstage.c`. By default, autoport uses the most +common map `0x50, 0x51, 0x52, 0x53` on everything except for Lenovo systems, which are known +to use `0x50, 0x52, 0x51, 0x53`. To detect the correct memory map, the easiest way is to boot +on the vendor firmware with just one module in channel 0, slot 0, and check the SMBus address +the EEPROM has. Under Linux, you can use these commands to see what is on SMBus: - phcoder@sid:~/coreboot/util/autoport$ sudo modprobe i2c-dev - phcoder@sid:~/coreboot/util/autoport$ sudo i2cdetect -l + $ sudo modprobe i2c-dev + $ sudo i2cdetect -l i2c-0 i2c i915 gmbus ssc I2C adapter i2c-1 i2c i915 gmbus vga I2C adapter i2c-2 i2c i915 gmbus panel I2C adapter @@ -98,7 +131,8 @@ i2c-7 i2c DPDDC-C I2C adapter i2c-8 i2c DPDDC-D I2C adapter i2c-9 smbus SMBus I801 adapter at 0400 SMBus adapter - phcoder@sid:~/coreboot/util/autoport$ sudo i2cdetect 9 + + $ sudo i2cdetect 9 WARNING! This program can confuse your I2C bus, cause data loss and worse! I will probe file /dev/i2c-9. I will probe address range 0x03-0x77. @@ -113,10 +147,11 @@ 60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 70: -- -- -- -- -- -- -- -- -Make sure to replace `9` with whatever bus is marked as SMBus. Here in an example -you see SPD at address `0x50`. Since we've booted with just the module in C0S0, so -the first entry in SPD map has to be `0x50`. Once you have SPD map your -`mainboard_get_spd` should look something like: +Make sure to replace the `9` on the last command with the bus number for SMBus on +your system. Here, there is a module at address `0x50`. Since only one module was +installed on the first slot of the first channel, we know the first position of +the SPD array must be `0x50`. After testing all the slots, your `mainboard_get_spd` +should look similar to this: void mainboard_get_spd(spd_raw_data *spd) { read_spd (&spd[0], 0x50); @@ -125,18 +160,20 @@ read_spd (&spd[3], 0x53); } -You can and should omit lines which correspond to -slots not present on your machine. +Note that there should be one line per memory slot on the mainboard. Note: slot labelling may be missing or unreliable. Use `inteltool` to see which slots have modules in them. -This way works well if your RAM is socketed. For soldered RAM if you see -its SPD, you're in luck and can proceed the same way although you may have to -guess some entries due to RAM not being removable. +This procedure is ideal, if your RAM is socketed. If you have soldered RAM, +remove any socketed memory modules and check if any EEPROM appears on SMBus. +If this is the case, you can proceed as if the RAM was socketed. However, +you may have to guess some entries if there multiple EEPROMs appear. -Most cases of soldered RAM don't have EEPROM chip. In this case you'd have to create -fake SPD. Look in `inteltool.log`. You'll see something like: +Most of the time, soldered RAM does not have an EEPROM. Instead, the SPD data is +inside the main flash chip where the firmware is. If this is the case, you need +to generate the SPD data to use with coreboot. Look at `inteltool.log`. There +should be something like this: /* SPD matching current mode: */ /* CH0S0 */ @@ -174,12 +211,12 @@ e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -This is not completely exact represantation of RAM -capablities as it lists only the mode currently used -and lacks minor info like serial number. Using `xxd` -you can create binary represantation of this SPD: +This is not a full-fledged SPD dump, as it only lists +the currently-used speed configuration, and lacks info +such as a serial number, vendor and model. Use `xxd` +to create a binary file with this SPD data: - cat | xxd -r > spd.bin <<EOF + $ cat | xxd -r > spd.bin <<EOF 00: 92 11 0b 03 04 00 00 09 03 52 01 08 0a 00 80 00 10: 6e 78 6e 32 6e 11 18 81 20 08 3c 3c 00 f0 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 @@ -196,109 +233,114 @@ d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - EOF + EOF (press Ctrl + D) -Then you can place this file into mainboard directory -and hook it up into build system by adding following -lines to `Makefile.inc` (creating a new file if needed) +Then, move the generated file into your mainboard's directory +and hook it up to the build system by adding the following +lines to `Makefile.inc`: cbfs-files-y += spd.bin spd.bin-file := spd.bin spd.bin-type := raw -And then make coreboot actually use this SPD. Following -example shows a hybrid situation with one module -soldered and another is socketed: +Now we need coreboot to use this SPD file. The following example +shows a hybrid configuration, in which one module is soldered and +the other one is socketed: void mainboard_get_spd(spd_raw_data *spd) { void *spd_file; size_t spd_file_len = 0; - /* C0S0 is a soldered RAM with no real SPD. Use stored SPD. */ - spd_file = cbfs_boot_map_with_leak( "spd.bin", CBFS_TYPE_RAW, + /* C0S0 is a soldered RAM with no real SPD. Use stored SPD. */ + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_RAW, &spd_file_len); if (spd_file && spd_file_len >= 128) memcpy(&spd[0], spd_file, 128); - /* C0S0 is a DIMM slot. */ - read_spd(&spd[1], 0x51); + + /* C1S0 is a physical slot. */ + read_spd(&spd[2], 0x52); } -If several slots are soldered there are 3 ways of doing things: +If several slots are soldered there are two ways to handle them: -* If all of them are the same use the same file. Don't forget to copy -it to all array elements. -* Use several files (recommended). Name them e.g. spd1, spd2,... -* Concatenate it into a single file and split into several -array elements on runtime. Not recommended +* If all use the same SPD data, use the same file for all the slots. Do + not forget to copy the data on all the array elements that need it. +* If they use different data, use several files. ### `board_info.txt` -`board_info.txt` is a simple text file used to generate wiki page -listing supported boards. Some of the info can't be detected automatically. +`board_info.txt` is a text file used in the board status page to list all +the supported boards and their specifications. Most of the information +cannot be detected by autoport. Common entries are: -As this is used only to present information to users then when it matches -your board and definitions it is correct. +* `ROM package`, `ROM protocol` and `ROM socketed`: + These refer to the flash chips you found earlier. You can visit + <http://flashrom.org/Technology> for more information. -* Which package is used for ROM and whether it's socketed, as well -as release year. For ROM package refer to <http://flashrom.org/Technology> -and compare it with ROM you found at the beginning of the port. Set -`ROM package`, `ROM socketed` and other variables mentioned in FIXME. -* Release year, just go to web and find that information. -* Category. It's difficult to make difference between desktop and similar -categories from inside the computer. Valid categories are: - * `desktop`. Desktops and workstations. - * `server`. Servers - * `laptop`. Laptops. - * `half`. Embedded / PC/104 / Half-size boards. - * `mini`. Mini-ITX / Micro-ITX / Nano-ITX - * `settop`. Set-top-boxes / Thin clients. - * `eval`. Devel/Eval Boards - * `sbc`. Single-Board computer. - * `emulation`. Virtual machines and emulators. May require especial care - as they often behave differently from real counterparts. - * `misc`. Anything not fitting the categories above. You probably shouldn't use - this. +* `Release year`: Use the power of Internet to find that information. +* `Category`: This describes the type of mainboard you have. + Valid categories are: + * `desktop`. Desktops and workstations. + * `server`. Servers. + * `laptop`. Laptops, notebooks and netbooks. + * `half`. Embedded / PC/104 / Half-size boards. + * `mini`. Mini-ITX / Micro-ITX / Nano-ITX + * `settop`. Set-top-boxes / Thin clients. + * `eval`. Development / Evaluation Boards. + * `sbc`. Single-Board computer. + * `emulation`: Virtual machines and emulators. May require especial care + as they often behave differently from real counterparts. + * `misc`. Anything not fitting the categories above. Not recommended. + +* `Flashrom support`: This means whether the internal programmer is usable. + If flashing coreboot internally works, this should be set to `y`. Else, + feel free to investigate why it is not working. ### `USBDEBUG_HCD_INDEX` -Which controller the most easily accessible USB debug port is. On intel -1 is for `00:1d.0` and 2 is `00:1a.0` (yes, it's reversed). See +Which controller the most easily accessible USB debug port is. On Intel, +1 is for `00:1d.0` and 2 is for `00:1a.0` (yes, it's reversed). Refer to <https://www.coreboot.org/EHCI_Debug_Port> for more info. -If you're able to use EHCI debug port without setting HCD index manually -in config this is correct. +If you are able to use EHCI debug without setting the HCD index manually, +this is correct. ### `BOARD_ROMSIZE_KB_2048` -Default rom size should be detected automatically but sometimes isn't. -If yours weren't detected put correct rom size here to serve as sane -default when configuring coreboot. +This parameter refers to the total size of the flash chips coreboot will be in. +This value must be correct for S3 resume to work properly. This parameter also +defines the size of the generated coreboot image, but that is not a major issue +since tools like `dd` can be used to cut fragments of a coreboot image to flash +on smaller chips. -If default ROM size when slecting the board is right one than this value -is correct. +This should be detected automatically, but it may not be detected properly in +some cases. If it was not detected, put the correct total size here to serve +as a sane default when configuring coreboot. ### `DRAM_RESET_GATE_GPIO` -When machine is going to S3 in order not to reset the RAM modules, the -reset signal must be filtered out from reachin RAM. This is done by -powering down a special gate. Most manufacturers put this gate on -GPIO 60 but Lenovo is knowon to put it on GPIO 10. If you're able to -go to S3 and back than this value is correct. +When the computer is suspended to RAM (ACPI S3), the RAM reset signal must not +reach the RAM modules. Otherwise, the computer will not resume and any opened +programs will be lost. This is done by powering down a MOSFET, which disconnects +the reset signal from the RAM modules. Most manufacturers put this gate on GPIO +60 but Lenovo is known to put it on GPIO 10. If suspending and resuming works, +this value is correct. This can also be determined from the board's schematics. ## GNVS -`acpi_create_gnvs` sets values in GNVS which in turn is used by ACPI for -various power-related functions. Normally there is no need to modify it -but it makes sense to proofread it. +`acpi_create_gnvs` sets values in GNVS, which then ACPI makes use of for +various power-related functions. Normally, there is no need to modify it +on laptops (desktops have no "lid"!) but it makes sense to proofread it. ## `gfx.ndid` and `gfx.did` Those describe which video outputs are declared in ACPI tables. -Normally there is no need to adjust but if you miss some nonstandard output -you can declare it there. Bit 31 is set to indicate presence of the output. -Byte 1 is the type and byte 0 is used for disambigution so that ID composed of -byte 1 and 0 is unique. Types are +Normally, there is no need to adjust these values, but if you miss some +non-standard video output, you can declare it there. Bit 31 is set to +indicate the presence of the output. Byte 1 is the type and byte 0 is +used for disambigution so that ID composed of byte 1 and 0 is unique. +Types are: * 1 = VGA * 2 = TV * 3 = DVI @@ -306,22 +348,31 @@ ## `c*_acpower` and `c*_battery` -Which mwait states to match to which ACPI levels. Normally no need to modify unless -your device has very special power saving requirements. +Which mwait states to match to which ACPI levels. Normall, there is no +need to modify anything unless your device has very special power +saving requirements. ## `install_intel_vga_int15_handler` -This is used to configure int15 hook used by vgabios. Parameters 2 and 3 usually -shouldn't be modified as vgabios is quite ok to figure panel fit and active -output by itself. Last number is the numerical ID of display type. If you -don't get any output with vgabios you should try different values for 4th -parameter. If it doesn't help try different values for first parameter as well +This is used with the Intel VGA BIOS, which is not the default option. +It is more error-prone than open-source graphics initialization, so do +not bother with this until your mainboard boots. This is a function +which takes four parameters: +1. Which type of LCD panel is connected. +2. Panel fit. +3. Boot display. +4. Display type. + +Refer to `src/drivers/intel/gma/int15.h` to see which values can be used. +For desktops, there is no LCD panel directly connected to the Intel GPU, +so the first parameter should be `GMA_INT15_ACTIVE_LFP_NONE`. On other +mainboards, it depends. ## CMOS options -Due to horrible state of CMOS support in coreboot tree, autoport doesn't support it and -this probably won't change until format in the tree improves. If you really care about -CMOS options: +Due to the poor state of CMOS support in coreboot, autoport does not +support it and this probably won't change until the format in the tree +improves. If you really care about CMOS options: * Create files `cmos.layout` and `cmos.default` * Enable `HAVE_OPTION_TABLE` and `HAVE_CMOS_DEFAULT` in `Kconfig` @@ -355,9 +406,9 @@ ## EC (generic laptop) -Almost any laptop has an embedded controller. In nutshell it's a small -low-powered computer specialised on managing power for laptop. Exact -functionality differs between macines but of interest to us is mainly: +Almost any laptop has an embedded controller. In a nutshell, it's a +small, low-powered computer designed to be used on laptops. Exact +functionality differs between machines. Its main functions include: * Control of power and rfkill to different component * Keyboard (PS/2) interface implementation -- To view, visit https://review.coreboot.org/c/coreboot/+/30969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc45824d5d1298146f459d75f0a5121dbdd70d41 Gerrit-Change-Number: 30969 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/autoport: Trim gfx.did to size
by Angel Pons (Code Review) 18 Mar '19

18 Mar '19

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30963 Change subject: util/autoport: Trim gfx.did to size ...................................................................... util/autoport: Trim gfx.did to size Since the values are hardcoded, we might as well hardcode values that make sense. Change-Id: I3ac0e2d74a42c1fe55b1cdc3e2a970ae80cc9f37 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/autoport/sandybridge.go 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/30963/1 diff --git a/util/autoport/sandybridge.go b/util/autoport/sandybridge.go index cf2b859..79b0714 100644 --- a/util/autoport/sandybridge.go +++ b/util/autoport/sandybridge.go @@ -53,7 +53,7 @@ "gfx.link_frequency_270_mhz": FormatBool(link_frequency > 200000), /* FIXME:XX hardcoded. */ "gfx.ndid": "3", - "gfx.did": "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }", + "gfx.did": "{ 0x80000100, 0x80000240, 0x80000410 }", }, Children: []DevTreeNode{ { -- To view, visit https://review.coreboot.org/c/coreboot/+/30963 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ac0e2d74a42c1fe55b1cdc3e2a970ae80cc9f37 Gerrit-Change-Number: 30963 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit January 2019