coreboot-gerrit January 2019

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Change in ...coreboot[master]: mb/lenovo/z61t/acpi_tables: Add critical and passive threshold
by Peter Lemenkov (Code Review) 27 May '19

27 May '19

Hello Patrick Rudolph, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31114 to review the following change. Change subject: mb/lenovo/z61t/acpi_tables: Add critical and passive threshold ...................................................................... mb/lenovo/z61t/acpi_tables: Add critical and passive threshold Add critical and passive threshold to be advertised in thermal zone 0. This commit follows up on commit afa627db with Change-Id Ic75a80994b27ac19651ed52b7fc3c00c65cd9c01. Change-Id: I7d645818d2b2f6b7c16d2d813bf982a55774561d Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/z61t/acpi_tables.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/31114/1 diff --git a/src/mainboard/lenovo/z61t/acpi_tables.c b/src/mainboard/lenovo/z61t/acpi_tables.c index 3e9a810..183b7fe 100644 --- a/src/mainboard/lenovo/z61t/acpi_tables.c +++ b/src/mainboard/lenovo/z61t/acpi_tables.c @@ -23,4 +23,7 @@ gnvs->cmap = 0x01; gnvs->cmbp = 0x01; + /* Set thermal levels */ + gnvs->tcrt = 100; + gnvs->tpsv = 90; } -- To view, visit https://review.coreboot.org/c/coreboot/+/31114 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d645818d2b2f6b7c16d2d813bf982a55774561d Gerrit-Change-Number: 31114 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: [UNTESTED]nb/intel/pineview: Move to C_ENVIRONMENT_BOOTBLOCK
by Arthur Heymans (Code Review) 25 May '19

25 May '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30939 Change subject: [UNTESTED]nb/intel/pineview: Move to C_ENVIRONMENT_BOOTBLOCK ...................................................................... [UNTESTED]nb/intel/pineview: Move to C_ENVIRONMENT_BOOTBLOCK Not yet tested. Change-Id: I7e74838b0d5e9c192082084cfd9821996f0e4c50 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/socket_FCBGA559/Kconfig M src/cpu/intel/socket_FCBGA559/Makefile.inc M src/mainboard/foxconn/d41s/Makefile.inc A src/mainboard/foxconn/d41s/bootblock.c M src/mainboard/foxconn/d41s/romstage.c M src/mainboard/intel/d510mo/Makefile.inc A src/mainboard/intel/d510mo/bootblock.c M src/mainboard/intel/d510mo/romstage.c M src/northbridge/intel/pineview/Kconfig M src/northbridge/intel/pineview/Makefile.inc M src/northbridge/intel/pineview/bootblock.c M src/northbridge/intel/pineview/pineview.h M src/northbridge/intel/pineview/romstage.c M src/southbridge/intel/i82801gx/Makefile.inc A src/southbridge/intel/i82801gx/bootblock_gcc.c 15 files changed, 149 insertions(+), 56 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/30939/1 diff --git a/src/cpu/intel/socket_FCBGA559/Kconfig b/src/cpu/intel/socket_FCBGA559/Kconfig index 6566a01..e6e904d 100644 --- a/src/cpu/intel/socket_FCBGA559/Kconfig +++ b/src/cpu/intel/socket_FCBGA559/Kconfig @@ -20,4 +20,11 @@ hex default 0x4000 +config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + help + The amount of anticipated stack usage in CAR by bootblock and + other stages. + endif diff --git a/src/cpu/intel/socket_FCBGA559/Makefile.inc b/src/cpu/intel/socket_FCBGA559/Makefile.inc index 868f6e5..c95e135 100644 --- a/src/cpu/intel/socket_FCBGA559/Makefile.inc +++ b/src/cpu/intel/socket_FCBGA559/Makefile.inc @@ -8,7 +8,9 @@ subdirs-y += ../hyperthreading subdirs-y += ../speedstep -cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S +bootblock-y += ../car/bootblock.c +bootblock-y += ../car/non-evict/cache_as_ram.S + postcar-y += ../car/non-evict/exit_car.S romstage-y += ../car/romstage.c diff --git a/src/mainboard/foxconn/d41s/Makefile.inc b/src/mainboard/foxconn/d41s/Makefile.inc index f3d7e76..abfc473 100644 --- a/src/mainboard/foxconn/d41s/Makefile.inc +++ b/src/mainboard/foxconn/d41s/Makefile.inc @@ -1,2 +1,3 @@ +bootblock-y += bootblock.c ramstage-y += cstates.c romstage-y += gpio.c diff --git a/src/mainboard/foxconn/d41s/bootblock.c b/src/mainboard/foxconn/d41s/bootblock.c new file mode 100644 index 0000000..86abba4 --- /dev/null +++ b/src/mainboard/foxconn/d41s/bootblock.c @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * Copyright (C) 2018 Arthur Heymans <arthur(a)aheymans.xyz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <southbridge/intel/i82801gx/i82801gx.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/it8721f/it8721f.h> + +#define SERIAL_DEV PNP_DEV(0x2e, IT8721F_SP1) + +void bootblock_mainboard_early_init(void) +{ + /* Disable Serial IRQ */ + pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); + /* Decode range */ + pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, + pci_read_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC) | 0x0010); + pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | KBC_LPC_EN + | FDD_LPC_EN | LPT_LPC_EN | COMB_LPC_EN + | COMA_LPC_EN); + + /* Environment Controller */ + pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x00fc0a01); + + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/foxconn/d41s/romstage.c b/src/mainboard/foxconn/d41s/romstage.c index ade85e6..c7e6e55 100644 --- a/src/mainboard/foxconn/d41s/romstage.c +++ b/src/mainboard/foxconn/d41s/romstage.c @@ -15,31 +15,7 @@ * GNU General Public License for more details. */ -#include <arch/io.h> -#include <device/pnp_def.h> -#include <southbridge/intel/i82801gx/i82801gx.h> #include <northbridge/intel/pineview/pineview.h> -#include <superio/ite/common/ite.h> -#include <superio/ite/it8721f/it8721f.h> - -#define SERIAL_DEV PNP_DEV(0x2e, IT8721F_SP1) - -void mb_enable_lpc(void) -{ - /* Disable Serial IRQ */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); - /* Decode range */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, - pci_read_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC) | 0x0010); - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | KBC_LPC_EN - | FDD_LPC_EN | LPT_LPC_EN | COMB_LPC_EN - | COMA_LPC_EN); - - /* Environment Controller */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x00fc0a01); - - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -} void get_mb_spd_addrmap(u8 *spd_addrmap) { diff --git a/src/mainboard/intel/d510mo/Makefile.inc b/src/mainboard/intel/d510mo/Makefile.inc index f3d7e76..abfc473 100644 --- a/src/mainboard/intel/d510mo/Makefile.inc +++ b/src/mainboard/intel/d510mo/Makefile.inc @@ -1,2 +1,3 @@ +bootblock-y += bootblock.c ramstage-y += cstates.c romstage-y += gpio.c diff --git a/src/mainboard/intel/d510mo/bootblock.c b/src/mainboard/intel/d510mo/bootblock.c new file mode 100644 index 0000000..b66164e --- /dev/null +++ b/src/mainboard/intel/d510mo/bootblock.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <southbridge/intel/i82801gx/i82801gx.h> +#include <superio/winbond/w83627thg/w83627thg.h> +#include <superio/winbond/common/winbond.h> + +#define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1) +#define SUPERIO_DEV PNP_DEV(0x4e, 0) + +void bootblock_mainboard_early_init(void) +{ + /* Disable Serial IRQ */ + pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0x00); + /* Decode range */ + pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, + pci_read_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC) | 0x0010); + pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN + | CNF2_LPC_EN | KBC_LPC_EN | COMA_LPC_EN + | COMB_LPC_EN); + + pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x7c0291); + + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c index 28e2e25..d9ec66b 100644 --- a/src/mainboard/intel/d510mo/romstage.c +++ b/src/mainboard/intel/d510mo/romstage.c @@ -14,31 +14,8 @@ * GNU General Public License for more details. */ -#include <arch/io.h> -#include <device/pnp_def.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <northbridge/intel/pineview/pineview.h> -#include <superio/winbond/w83627thg/w83627thg.h> -#include <superio/winbond/common/winbond.h> - -#define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1) -#define SUPERIO_DEV PNP_DEV(0x4e, 0) - -void mb_enable_lpc(void) -{ - /* Disable Serial IRQ */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0x00); - /* Decode range */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, - pci_read_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC) | 0x0010); - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN - | CNF2_LPC_EN | KBC_LPC_EN | COMA_LPC_EN - | COMB_LPC_EN); - - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x7c0291); - - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -} void mb_pirq_setup(void) { diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig index 6168305..773f1db 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig @@ -31,6 +31,7 @@ select POSTCAR_STAGE select POSTCAR_CONSOLE select SMM_TSEG + select C_ENVIRONMENT_BOOTBLOCK config BOOTBLOCK_NORTHBRIDGE_INIT string diff --git a/src/northbridge/intel/pineview/Makefile.inc b/src/northbridge/intel/pineview/Makefile.inc index 524bcae..6323391 100644 --- a/src/northbridge/intel/pineview/Makefile.inc +++ b/src/northbridge/intel/pineview/Makefile.inc @@ -16,6 +16,8 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_PINEVIEW),y) +bootblock-y += bootblock.c + ramstage-y += ram_calc.c ramstage-y += northbridge.c ramstage-y += gma.c diff --git a/src/northbridge/intel/pineview/bootblock.c b/src/northbridge/intel/pineview/bootblock.c index 1fab845..373d476 100644 --- a/src/northbridge/intel/pineview/bootblock.c +++ b/src/northbridge/intel/pineview/bootblock.c @@ -12,11 +12,13 @@ */ #include <arch/io.h> -#define PCIEXBAR 0x60 +#include <cpu/intel/car/bootblock.h> +#include "pineview.h" + #define MMCONF_256_BUSSES 16 #define ENABLE 1 -static void bootblock_northbridge_init(void) +void bootblock_early_northbridge_init(void) { pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS | MMCONF_256_BUSSES | ENABLE); diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h index 65d21cf..f53ff17 100644 --- a/src/northbridge/intel/pineview/pineview.h +++ b/src/northbridge/intel/pineview/pineview.h @@ -236,7 +236,6 @@ u8 decode_pciebar(u32 *const base, u32 *const len); /* Mainboard romstage callback functions */ -void mb_enable_lpc(void); void get_mb_spd_addrmap(u8 *spd_addr_map); void mb_pirq_setup(void); /* optional */ diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c index 10ac0f5..b25c36e 100644 --- a/src/northbridge/intel/pineview/romstage.c +++ b/src/northbridge/intel/pineview/romstage.c @@ -55,17 +55,12 @@ if (bist == 0) enable_lapic(); - /* Disable watchdog timer */ - RCBA32(GCS) = RCBA32(GCS) | 0x20; - /* Enable GPIOs */ pci_write_config32(LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10); setup_pch_gpios(&mainboard_gpio_map); - mb_enable_lpc(); // nm10_enable_lpc - /* Initialize console device(s) */ console_init(); diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc index 290794b..0864786 100644 --- a/src/southbridge/intel/i82801gx/Makefile.inc +++ b/src/southbridge/intel/i82801gx/Makefile.inc @@ -15,6 +15,8 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801GX),y) +bootblock-y += bootblock_gcc.c + ramstage-y += i82801gx.c ramstage-y += ac97.c ramstage-y += azalia.c diff --git a/src/southbridge/intel/i82801gx/bootblock_gcc.c b/src/southbridge/intel/i82801gx/bootblock_gcc.c new file mode 100644 index 0000000..8b9826a --- /dev/null +++ b/src/southbridge/intel/i82801gx/bootblock_gcc.c @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <cpu/intel/car/bootblock.h> +#include "i82801gx.h" + +static void enable_spi_prefetch(void) +{ + u8 reg8; + pci_devfn_t dev; + + dev = PCI_DEV(0, 0x1f, 0); + + reg8 = pci_read_config8(dev, 0xdc); + reg8 &= ~(3 << 2); + reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ + pci_write_config8(dev, 0xdc, reg8); +} + +void bootblock_early_southbridge_init(void) +{ + enable_spi_prefetch(); + + /* Enable RCBA */ + pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1); + + /* Enable upper 128bytes of CMOS */ + RCBA32(0x3400) = (1 << 2); + + /* Disable watchdog timer */ + RCBA32(GCS) = RCBA32(GCS) | 0x20; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/30939 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e74838b0d5e9c192082084cfd9821996f0e4c50 Gerrit-Change-Number: 30939 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Documentation: Add HP EliteBook 8760w
by Iru Cai (vimacs) (Code Review) 25 May '19

25 May '19

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30950 to review the following change. Change subject: Documentation: Add HP EliteBook 8760w ...................................................................... Documentation: Add HP EliteBook 8760w Also add the HP EliteBook document from wiki. Change-Id: I189db9c279705af53d82af66d0c2e8afb6f84d73 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- A Documentation/mainboard/hp/8760w.md A Documentation/mainboard/hp/elitebook_series.md M Documentation/mainboard/index.md 3 files changed, 149 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/30950/1 diff --git a/Documentation/mainboard/hp/8760w.md b/Documentation/mainboard/hp/8760w.md new file mode 100644 index 0000000..ba4da7d --- /dev/null +++ b/Documentation/mainboard/hp/8760w.md @@ -0,0 +1,33 @@ +# HP EliteBook 8760w + +This page describes how to run coreboot on the [HP EliteBook 8760w]. + +## Required proprietary blobs + +- Intel Firmware Descriptor, ME and GbE firmware +- EC: please read [EliteBook Series](elitebook_series) + +## Flashing instructions + +HP EliteBook 8760w has an 8MB SOIC-8 flash chip on the bottom of the +mainboard. You just need to remove the service cover, and use an SOIC-8 +clip to read and flash the chip. + +## Untested + +- dock: serial port, parallel port, ... +- TPM +- S3 suspend/resume +- Gigabit Ethernet +- Using `me_cleaner` + +## Working + +- SeaBIOS payload +- EHCI debug: the port is at the right next to the charging port +- USB +- WLAN +- WWAN +- SATA + +[HP EliteBook 8760w]: https://support.hp.com/us-en/product/hp-elitebook-8760w-mobile-workstation/… diff --git a/Documentation/mainboard/hp/elitebook_series.md b/Documentation/mainboard/hp/elitebook_series.md new file mode 100644 index 0000000..6668928 --- /dev/null +++ b/Documentation/mainboard/hp/elitebook_series.md @@ -0,0 +1,111 @@ +# HP EliteBook series + +This document is about HP EliteBook series laptops up to Ivy Bridge era +which use SMSC KBC1126 as embedded controller. + +## EC + +SMSC KBC1098/KBC1126 has been used in HP EliteBooks for many generations. +They use similar EC firmware that will load other code and data from the +SPI flash chip, so we need to put some firmware blobs to the coreboot image. + +The following document takes EliteBook 2760p as an example. + +First, you need to extract the blobs needed by EC firmware using util/kbc1126. +You can extract them from your backup firmware image, or firmware update +provided by HP with [unar] as follows: + +```bash +wget https://ftp.hp.com/pub/softpaq/sp79501-80000/sp79710.exe +unar sp79710.exe +${COREBOOT_DIR}/util/kbc1126/kbc1126_ec_dump sp79710/Rompaq/68SOU.BIN +mv 68SOU.BIN.fw1 ${COREBOOT_DIR}/2760p-fw1.bin +mv 68SOU.BIN.fw2 ${COREBOOT_DIR}/2760p-fw2.bin +``` + +When you config coreboot, select: + +```text +Chipset ---> + [*] Add firmware images for KBC1126 EC + (2760p-fw1.bin) KBC1126 firmware #1 path and filename + (2760p-fw2.bin) KBC1126 filename #2 path and filename +``` + +## Super I/O + +EliteBook 8000 series laptops have SMSC LPC47n217 Super I/O to provide +a serial port and a parallel port, you can debug the laptop via this +serial port. + +## porting + +To port coreboot to an HP EliteBook laptop, you need to do the following: + +- select Kconfig option `EC_HP_KBC1126` +- select Kconfig option `SUPERIO_SMSC_LPC47N217` if there is LPC47n217 Super I/O +- initialize EC and Super I/O in romstage +- add EC and Super I/O support to devicetree.cb + +To get the related values for EC in devicetree.cb, you need to extract the EFI +module EcThermalInit from the vendor UEFI firmware with [UEFITool]. Usually, +`ec_data_port`, `ec_cmd_port` and `ec_ctrl_reg` has the following values: + +- For xx60 series: 0x60, 0x64, 0xca +- For xx70 series: 0x62, 0x66, 0x81 + +You can use [radare2] and the following [r2pipe] Python script to find +these values from the EcThermalInit EFI module: + +```python +#!/usr/bin/env python + +# install radare2 and use `pip3 install --user r2pipe` to install r2pipe + +import r2pipe +import sys + +if len(sys.argv) < 2: + fn = "ecthermalinit.efi" +else: + fn = sys.argv[1] + +r2 = r2pipe.open(fn) +r2.cmd("aa") +entryf = r2.cmdj("pdfj") + +for insn in entryf["ops"]: + if "lea r8" in insn["opcode"]: + _callback = insn["ptr"] + break + +r2.cmd("af @ {}".format(_callback)) +callbackf_insns = r2.cmdj("pdfj @ {}".format(_callback))["ops"] + +def find_port(addr): + ops = r2.cmdj("pdfj @ {}".format(addr))["ops"] + for insn in ops: + if "lea r8d" in insn["opcode"]: + return insn["ptr"] + +ctrl_reg_found = False + +for i in range(0, len(callbackf_insns)): + if not ctrl_reg_found and "mov cl" in callbackf_insns[i]["opcode"]: + ctrl_reg_found = True + ctrl_reg = callbackf_insns[i]["ptr"] + print("ec_ctrl_reg = 0x%02x" % ctrl_reg) + cmd_port = find_port(callbackf_insns[i+1]["jump"]) + data_port = find_port(callbackf_insns[i+3]["jump"]) + print("ec_cmd_port = 0x%02x\nec_data_port = 0x%02x" % (cmd_port, data_port)) + + if "mov bl" in callbackf_insns[i]["opcode"]: + ctrl_value = callbackf_insns[i]["ptr"] + print("ec_fan_ctrl_value = 0x%02x" % ctrl_value) +``` + + +[unar]: https://theunarchiver.com/command-line +[UEFITool]: https://github.com/LongSoft/UEFITool +[radare2]: https://radare.org/ +[r2pipe]: https://github.com/radare/radare2-r2pipe diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 4e2b742..606901f 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -46,6 +46,11 @@ - [Compaq 8200 Elite SFF](hp/compaq_8200_sff.md) +### EliteBook series + +- [EliteBook common](hp/elitebook_series.md) +- [EliteBook 8760w](hp/8760w.md) + ## Lenovo - [T4xx common](lenovo/t4xx_series.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/30950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I189db9c279705af53d82af66d0c2e8afb6f84d73 Gerrit-Change-Number: 30950 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-MessageType: newchange

2 5

Change in ...coreboot[master]: [WIP]soc/fsp1.1: Implement postcar stage
by Arthur Heymans (Code Review) 21 May '19

21 May '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30686 Change subject: [WIP]soc/fsp1.1: Implement postcar stage ...................................................................... [WIP]soc/fsp1.1: Implement postcar stage TODO cleanup, test Change-Id: I2330993842aae9c1365230f0c6bd8a2449dc73a5 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/intel/fsp1_1/Kconfig M src/drivers/intel/fsp1_1/Makefile.inc M src/drivers/intel/fsp1_1/after_raminit.S M src/drivers/intel/fsp1_1/cache_as_ram.inc M src/drivers/intel/fsp1_1/romstage.c M src/soc/intel/braswell/Makefile.inc M src/soc/intel/skylake/romstage/car_stage.S 7 files changed, 86 insertions(+), 159 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/30686/1 diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index 69fa8df..53a993c 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -18,6 +18,8 @@ bool select UEFI_2_4_BINDING select INTEL_GMA_ADD_VBT if RUN_FSP_GOP + select POSTCAR_STAGE + select POSTCAR_CONSOLE help Does the code require the Intel Firmware Support Package? diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc index 953d1e4..62dc663 100644 --- a/src/drivers/intel/fsp1_1/Makefile.inc +++ b/src/drivers/intel/fsp1_1/Makefile.inc @@ -28,7 +28,6 @@ romstage-y += hob.c romstage-y += raminit.c romstage-y += romstage.c -romstage-y += stack.c romstage-y += stage_cache.c romstage-$(CONFIG_MMA) += mma_core.c @@ -45,6 +44,9 @@ cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_1/cache_as_ram.inc +postcar-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += after_raminit.S +postcar-y += stage_cache.c + # Add the FSP binary to the cbfs image ifeq ($(CONFIG_HAVE_FSP_BIN),y) cbfs-files-y += fsp.bin diff --git a/src/drivers/intel/fsp1_1/after_raminit.S b/src/drivers/intel/fsp1_1/after_raminit.S index cdc8e93..05c4425 100644 --- a/src/drivers/intel/fsp1_1/after_raminit.S +++ b/src/drivers/intel/fsp1_1/after_raminit.S @@ -20,151 +20,10 @@ #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> -/* - * This is the common entry point after DRAM has been initialized. - */ - /* - * eax: New stack address - */ - - /* Switch to the stack in RAM */ - movl %eax, %esp - -#if IS_ENABLED(CONFIG_SKIP_FSP_CAR) - - /* chipset_teardown_car() is expected to disable cache-as-ram. */ - call chipset_teardown_car - -#else -.extern fih_car +.text +.global chipset_teardown_car +chipset_teardown_car: post_code(POST_FSP_TEMP_RAM_EXIT) - - /* Calculate TempRamExit entry into FSP */ - movl fih_car, %ebp - mov 0x40(%ebp), %eax - add 0x1c(%ebp), %eax - - /* Build the call frame */ - pushl $0 - - /* Call TempRamExit */ - call *%eax - add $4, %esp - cmp $0, %eax - jz 1f - /* - * Failures for post code BC - failed in TempRamExit - * - * 0x00 - FSP_SUCCESS: Temp RAM Exit completed successfully. - * 0x02 - FSP_INVALID_PARAMETER: Input parameters are invalid. - * 0x03 - FSP_UNSUPPORTED: The FSP calling conditions were not met. - * 0x07 - FSP_DEVICE_ERROR: Temp RAM Exit failed. - */ - movb $0xBC, %ah - jmp .Lhlt -1: -#endif - /* Display the MTRRs */ - call display_mtrrs - - /* - * The stack contents are initialized in src/soc/intel/common/stack.c - * to be the following: - * - * * - * * - * * - * +36: MTRR mask 1 63:32 - * +32: MTRR mask 1 31:0 - * +28: MTRR base 1 63:32 - * +24: MTRR base 1 31:0 - * +20: MTRR mask 0 63:32 - * +16: MTRR mask 0 31:0 - * +12: MTRR base 0 63:32 - * +8: MTRR base 0 31:0 - * +4: Number of MTRRs to setup (described above) - * +0: Number of variable MTRRs to clear - */ - -#if IS_ENABLED(CONFIG_SOC_SETS_MSRS) - push %esp - call soc_set_mtrrs - - /* eax: new top_of_stack with setup_stack_and_mtrrs data removed */ - movl %eax, %esp -#else - /* Clear all of the variable MTRRs. */ - popl %ebx - movl $MTRR_PHYS_BASE(0), %ecx - clr %eax - clr %edx - -1: - testl %ebx, %ebx - jz 1f - wrmsr /* Write MTRR base. */ - inc %ecx - wrmsr /* Write MTRR mask. */ - inc %ecx - dec %ebx - jmp 1b - -1: - /* Get number of MTRRs. */ - popl %ebx - movl $MTRR_PHYS_BASE(0), %ecx -2: - testl %ebx, %ebx - jz 2f - - /* Low 32 bits of MTRR base. */ - popl %eax - /* Upper 32 bits of MTRR base. */ - popl %edx - /* Write MTRR base. */ - wrmsr - inc %ecx - /* Low 32 bits of MTRR mask. */ - popl %eax - /* Upper 32 bits of MTRR mask. */ - popl %edx - /* Write MTRR mask. */ - wrmsr - inc %ecx - - dec %ebx - jmp 2b -2: -#endif /* CONFIG_SOC_SETS_MSRS */ - - post_code(0x39) - - /* And enable cache again after setting MTRRs. */ - movl %cr0, %eax - andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax - movl %eax, %cr0 - - post_code(0x3a) - -#if IS_ENABLED(CONFIG_SOC_SETS_MSRS) - call soc_enable_mtrrs -#else - /* Enable MTRR. */ - movl $MTRR_DEF_TYPE_MSR, %ecx - rdmsr - orl $MTRR_DEF_TYPE_EN, %eax - wrmsr -#endif /* CONFIG_SOC_SETS_MSRS */ - - post_code(0x3b) - - /* Invalidate the cache again. */ - invd - - post_code(0x3c) - -__main: - post_code(POST_PREPARE_RAMSTAGE) - cld /* Clear direction flag. */ - call after_cache_as_ram + pop %ebx + jmp *%ebx diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc index 934ae67..2a4e47c 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.inc +++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc @@ -140,11 +140,6 @@ /* Call cache_as_ram_main(struct cache_as_ram_params *) */ call cache_as_ram_main -/* One will never return from cache_as_ram_main() in verstage so there's - * no such thing as after RAM init. */ -#if !ENV_VERSTAGE -#include "after_raminit.S" -#endif movb $0x69, %ah jmp .Lhlt diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index c1bcd84..d362b44 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -30,6 +30,7 @@ #include <ec/google/chromeec/ec_commands.h> #include <elog.h> #include <fsp/romstage.h> +#include <fsp/memmap.h> #include <mrc_cache.h> #include <program_loading.h> #include <romstage_handoff.h> @@ -39,9 +40,77 @@ #include <timestamp.h> #include <vendorcode/google/chromeos/chromeos.h> +#define ROMSTAGE_RAM_STACK_SIZE 0x5000 + +/* platform_enter_postcar() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use, + * and continues execution in postcar stage. */ +static void platform_enter_postcar(void) +{ + struct postcar_frame pcf; + size_t alignment; + uint32_t aligned_ram; + + if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + die("Unable to initialize postcar frame.\n"); + /* Cache the ROM as WP just below 4GiB. */ + postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, + MTRR_TYPE_WRPROT); + + /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ + postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); + + /* + * +-------------------------+ Top of RAM (aligned) + * | System Management Mode | + * | code and data | Length: CONFIG_TSEG_SIZE + * | (TSEG) | + * +-------------------------+ SMM base (aligned) + * | | + * | Chipset Reserved Memory | Length: Multiple of CONFIG_TSEG_SIZE + * | | + * +-------------------------+ top_of_ram (aligned) + * | | + * | CBMEM Root | + * | | + * +-------------------------+ + * | | + * | FSP Reserved Memory | + * | | + * +-------------------------+ + * | | + * | Various CBMEM Entries | + * | | + * +-------------------------+ top_of_stack (8 byte aligned) + * | | + * | stack (CBMEM Entry) | + * | | + * +-------------------------+ + */ + + alignment = mmap_region_granularity(); + aligned_ram = ALIGN_DOWN(romstage_ram_stack_bottom(), alignment); + postcar_frame_add_mtrr(&pcf, aligned_ram, aligned_ram + alignment, MTRR_TYPE_WRBACK); + +#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) + uintptr_t smm_base; + size_t smm_size; + + /* + * Cache the TSEG region at the top of ram. This region is not + * restricted to SMM mode until SMM has been relocated. By setting + * the region to cacheable it provides faster access when relocating + * the SMM handler as well as using the TSEG region for other purposes. + */ + smm_region(&smm_base, &smm_size); + postcar_frame_add_mtrr(&pcf, smm_base, alignment, MTRR_TYPE_WRBACK); +#endif + + run_postcar_phase(&pcf); +} + asmlinkage void *romstage_main(FSP_INFO_HEADER *fih) { - void *top_of_stack; struct pei_data pei_data; struct romstage_params params = { .pei_data = &pei_data, @@ -78,11 +147,9 @@ soc_after_ram_init(&params); post_code(0x38); - top_of_stack = setup_stack_and_mtrrs(); + platform_enter_postcar(); - printk(BIOS_DEBUG, "Calling FspTempRamExit API\n"); - timestamp_add_now(TS_FSP_TEMP_RAM_EXIT_START); - return top_of_stack; + return NULL; } void *cache_as_ram_stage_main(FSP_INFO_HEADER *fih) diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index fabbc2b..3296331 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -16,6 +16,9 @@ romstage-y += pmutil.c romstage-y += tsc_freq.c +postcar-y += memmap.c +postcar-y += iosf.c + ramstage-y += acpi.c ramstage-y += chip.c ramstage-y += cpu.c diff --git a/src/soc/intel/skylake/romstage/car_stage.S b/src/soc/intel/skylake/romstage/car_stage.S index 9482456..1c5857b 100644 --- a/src/soc/intel/skylake/romstage/car_stage.S +++ b/src/soc/intel/skylake/romstage/car_stage.S @@ -20,9 +20,8 @@ .global car_stage_entry car_stage_entry: call romstage_c_entry - #include "src/drivers/intel/fsp1_1/after_raminit.S" - + /* we don't return here */ movb $0x69, %ah jmp .Lhlt -- To view, visit https://review.coreboot.org/c/coreboot/+/30686 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2330993842aae9c1365230f0c6bd8a2449dc73a5 Gerrit-Change-Number: 30686 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

9 29

Change in ...coreboot[master]: src/superio/ite/common: Prepare for new SuperIO
by Michał Żygowski (Code Review) 15 May '19

15 May '19

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30553 Change subject: src/superio/ite/common: Prepare for new SuperIO ...................................................................... src/superio/ite/common: Prepare for new SuperIO Introduce 7bit Slope PWM registers. New ITE SuperIO may have contiguous 7bit values for PWM slope. Add option to enable External Sensor SMBus Host. Allow early SuperIO serial init in bootblock for platforms supporting C_ENVIRONMENT_BOOTBLOCK. Update/add registers macros for IT8786E-F which are not backwards compatible. Change-Id: I68fbfe62dfa05d0c166abaefbdc2ab873114b236 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/superio/ite/Makefile.inc M src/superio/ite/common/Kconfig M src/superio/ite/common/env_ctrl.c M src/superio/ite/common/env_ctrl.h M src/superio/ite/common/env_ctrl_chip.h 5 files changed, 53 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/30553/1 diff --git a/src/superio/ite/Makefile.inc b/src/superio/ite/Makefile.inc index 382dbd7..a54db6f 100644 --- a/src/superio/ite/Makefile.inc +++ b/src/superio/ite/Makefile.inc @@ -14,7 +14,11 @@ ## ## include generic ite pre-ram stage driver -romstage-$(CONFIG_SUPERIO_ITE_COMMON_ROMSTAGE) += common/early_serial.c + +ifeq ($(CONFIG_SUPERIO_ITE_COMMON_ROMSTAGE),y) +bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += common/early_serial.c +romstage-y += common/early_serial.c +endif ## include generic ite environment controller driver ramstage-$(CONFIG_SUPERIO_ITE_ENV_CTRL) += common/env_ctrl.c diff --git a/src/superio/ite/common/Kconfig b/src/superio/ite/common/Kconfig index 162b7f1..fd6a699 100644 --- a/src/superio/ite/common/Kconfig +++ b/src/superio/ite/common/Kconfig @@ -41,4 +41,10 @@ help The second FAN controller has a separate frequency setting. +config SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG + bool + help + Slope PWM registers have no separate BIT6 and are set directly by + 7-bit values instead. + endif diff --git a/src/superio/ite/common/env_ctrl.c b/src/superio/ite/common/env_ctrl.c index 1dc5bb6..fb347de 100644 --- a/src/superio/ite/common/env_ctrl.c +++ b/src/superio/ite/common/env_ctrl.c @@ -3,6 +3,7 @@ * * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * Copyright (C) 2016 secunet Security Networks AG + * Copyright (C) 2018 Libretrend LDA * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -164,9 +165,14 @@ pwm_ctrl |= ITE_EC_FAN_CTL_TEMPIN(conf->tmpin); pwm_start = ITE_EC_FAN_CTL_PWM_START_DUTY(conf->pwm_start); - pwm_start |= ITE_EC_FAN_CTL_PWM_SLOPE_BIT6(conf->slope); - pwm_auto = ITE_EC_FAN_CTL_PWM_SLOPE_LOWER(conf->slope); + if (IS_ENABLED(CONFIG_SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG)) { + pwm_auto = conf->slope & 0x7f; + } else { + pwm_start |= ITE_EC_FAN_CTL_PWM_SLOPE_BIT6(conf->slope); + pwm_auto = ITE_EC_FAN_CTL_PWM_SLOPE_LOWER(conf->slope); + } + if (conf->smoothing) pwm_auto |= ITE_EC_FAN_CTL_AUTO_SMOOTHING_EN; @@ -213,7 +219,7 @@ ite_ec_write(base, ITE_EC_FAN_CTL_MODE, reg); } - if (IS_ENABLED(SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG) + if (IS_ENABLED(CONFIG_SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG) && conf->mode >= FAN_MODE_ON) { reg = ite_ec_read(base, ITE_EC_FAN_TAC_COUNTER_ENABLE); reg |= ITE_EC_FAN_TAC_16BIT_ENABLE(fan); @@ -271,6 +277,13 @@ for (i = 0; i < ITE_EC_TMPIN_CNT; ++i) enable_tmpin(base, i + 1, &conf->tmpin[i]); + /* Enable External Sensor SMBus Host if configured */ + if (conf->smbus_en) { + ite_ec_write(base, ITE_EC_INTERFACE_SELECT, + ite_ec_read(base, ITE_EC_INTERFACE_SELECT) | + ITE_EC_INTERFACE_SMB_ENABLE); + } + /* Enable reading of voltage pins */ ite_ec_write(base, ITE_EC_ADC_VOLTAGE_CHANNEL_ENABLE, conf->vin_mask); diff --git a/src/superio/ite/common/env_ctrl.h b/src/superio/ite/common/env_ctrl.h index 11316db..06a41a5 100644 --- a/src/superio/ite/common/env_ctrl.h +++ b/src/superio/ite/common/env_ctrl.h @@ -3,6 +3,7 @@ * * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * Copyright (C) 2016 secunet Security Networks AG + * Copyright (C) 2018 Libretrend LDA * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -48,13 +49,34 @@ #define ITE_EC_FAN_PWM_SMOOTHING_1KHZ (0 << 6) #define ITE_EC_FAN_PWM_SMOOTHING_256HZ (1 << 6) #define ITE_EC_FAN_PWM_SMOOTHING_64HZ (2 << 6) +#if IS_ENABLED(CONFIG_SUPERIO_ITE_IT8786E) +#define ITE_EC_FAN_PWM_SMOOTHING_16HZ (1 << 6) +#else #define ITE_EC_FAN_PWM_SMOOTHING_16HZ (3 << 6) +#endif +/* SUPERIO_ITE_IT8786E PWM_SMOOTHING_FREQ contents */ +#define ITE_EC_FAN_PWM_SMOOTHING_1HZ (0 << 6) +#define ITE_EC_FAN_PWM_SMOOTHING_8HZ (2 << 6) +#define ITE_EC_FAN_PWM_SMOOTHING_4HZ (3 << 6) +#define ITE_EC_FAN_CTL5_SEL(x) ((((x)-1) & 3) << 2) +#define ITE_EC_FAN_CTL5_SEL_NONE (3 << 2) +#define ITE_EC_FAN_CTL4_SEL(x) (((x)-1) & 3) +#define ITE_EC_FAN_CTL4_SEL_NONE (3 << 0) #define ITE_EC_FAN_TAC_COUNTER_ENABLE 0x0c #define ITE_EC_FAN_TAC_16BIT_ENABLE(x) (1 << ((x)-1)) #define ITE_EC_FAN_TAC_LIMIT(x) (0x10 + ((x)-1)) #define ITE_EC_FAN_TAC_EXT_LIMIT(x) (0x1b + ((x)-1)) +/* SUPERIO_ITE_IT8786E FAN_TAC_CNTRL register content */ +#define ITE_EC_FAN_TAC_CNTRL 0x0c +#define ITE_EC_TMPIN3_ENHANCED_INT_MODE (1 << 7) +#define ITE_EC_TMPIN2_ENHANCED_INT_MODE (1 << 6) +#define ITE_EC_FAN_TAC5_EN (1 << 5) +#define ITE_EC_FAN_TAC4_EN (1 << 4) +#define ITE_EC_TMPIN1_ENHANCED_INT_MODE (1 << 3) +#define ITE_EC_AMDTSI_ERR_EN (1 << 0) + #define ITE_EC_FAN_MAIN_CTL 0x13 #define ITE_EC_FAN_MAIN_CTL_TAC_EN(x) (1 << ((x)+3)) #define ITE_EC_FAN_MAIN_CTL_COLL_FULL_SPEED (1 << 3) @@ -130,6 +152,8 @@ #define ITE_EC_FAN_CTL_PWM_SLOPE_LOWER(s) ((s) & 0x3f) #define ITE_EC_FAN_CTL_DELTA_TEMP(x) (0x65 + ((x)-1) * 8) #define ITE_EC_FAN_CTL_DELTA_TEMP_INTRVL(c) ((c) & 0x1f) +#define ITE_EC_FAN_CTL_TARGET_ZONE(x) (0x66 + ((x)-1) * 8) +#define ITE_EC_FAN_CTL_TARGET_ZONE_MASK 0x0f #define ITE_EC_EXTEMP_STATUS 0x88 #define ITE_EC_EXTEMP_STATUS_HOST_BUSY (1 << 0) diff --git a/src/superio/ite/common/env_ctrl_chip.h b/src/superio/ite/common/env_ctrl_chip.h index f8f2e1e..4df9b01 100644 --- a/src/superio/ite/common/env_ctrl_chip.h +++ b/src/superio/ite/common/env_ctrl_chip.h @@ -3,6 +3,7 @@ * * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * Copyright (C) 2016 secunet Security Networks AG + * Copyright (C) 2018 Libretrend LDA * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -95,6 +96,7 @@ bool tmpin_beep; bool fan_beep; bool vin_beep; + bool smbus_en; }; /* Some shorthands for device trees */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68fbfe62dfa05d0c166abaefbdc2ab873114b236 Gerrit-Change-Number: 30553 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

4 7

Change in ...coreboot[master]: Update chromeec submodule to upstream master
by Patrick Georgi (Code Review) 13 May '19

13 May '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30915 Change subject: Update chromeec submodule to upstream master ...................................................................... Update chromeec submodule to upstream master Updating from commit id 11bd4c0f4: 2018-05-22 21:57:16 -0700 - (bip: enabled PPC interrupts) to commit id 860fe2962: 2018-12-29 05:45:29 -0800 - (mt_scp/ipi: Support host command.) This brings in 1420 new commits. Change-Id: Ib7fef556696d6ea6547ec680124e0e13b4c3bfb8 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M 3rdparty/chromeec 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/30915/1 diff --git a/3rdparty/chromeec b/3rdparty/chromeec index 11bd4c0..860fe29 160000 --- a/3rdparty/chromeec +++ b/3rdparty/chromeec @@ -1 +1 @@ -Subproject commit 11bd4c0f4d11357ab830982d7dec164813c886dd +Subproject commit 860fe2962d40ee901369d1dc67f4aa7a7a42ba4d -- To view, visit https://review.coreboot.org/c/coreboot/+/30915 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7fef556696d6ea6547ec680124e0e13b4c3bfb8 Gerrit-Change-Number: 30915 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 2

Change in ...coreboot[master]: Update arm-trusted-firmware submodule to upstream master
by Patrick Georgi (Code Review) 13 May '19

13 May '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30916 Change subject: Update arm-trusted-firmware submodule to upstream master ...................................................................... Update arm-trusted-firmware submodule to upstream master Updating from commit id 693e278e: 2018-02-01 18:15:53 +0000 - (Merge pull request #1245 from antonio-nino-diaz-arm/an/checkpatch) to commit id c8765826: 2018-12-19 15:08:23 +0100 - (Merge pull request #1730 from antonio-nino-diaz-arm/an/spdx) This brings in 1583 new commits. Change-Id: Ief895b0bbaf80d0825e38975ba44f77c05d1dded Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M 3rdparty/arm-trusted-firmware 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/30916/1 diff --git a/3rdparty/arm-trusted-firmware b/3rdparty/arm-trusted-firmware index 693e278..c876582 160000 --- a/3rdparty/arm-trusted-firmware +++ b/3rdparty/arm-trusted-firmware @@ -1 +1 @@ -Subproject commit 693e278e308441d716f7f5116c43aa150955da31 +Subproject commit c8765826f4c2d10db0b660defccc84f7bce11af0 -- To view, visit https://review.coreboot.org/c/coreboot/+/30916 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief895b0bbaf80d0825e38975ba44f77c05d1dded Gerrit-Change-Number: 30916 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: mb/google/nami: Add VBT blobs and include them in cbfs
by Arthur Heymans (Code Review) 10 May '19

10 May '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30427 Change subject: mb/google/nami: Add VBT blobs and include them in cbfs ...................................................................... mb/google/nami: Add VBT blobs and include them in cbfs Change-Id: Iaf49bdee7ae82a0a61192327351267f098eb5ab1 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/google/poppy/variants/nami/Makefile.inc R src/mainboard/google/poppy/variants/nami/akali-data.vbt A src/mainboard/google/poppy/variants/nami/data.vbt A src/mainboard/google/poppy/variants/nami/patheon-data.vbt A src/mainboard/google/poppy/variants/nami/vayne-data.vbt 5 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/30427/1 diff --git a/src/mainboard/google/poppy/variants/nami/Makefile.inc b/src/mainboard/google/poppy/variants/nami/Makefile.inc index 7f86bb7..8f4ef0c 100644 --- a/src/mainboard/google/poppy/variants/nami/Makefile.inc +++ b/src/mainboard/google/poppy/variants/nami/Makefile.inc @@ -41,3 +41,15 @@ cbfs-files-y += oem.bin oem.bin-file := $(call strip_quotes,$(CONFIG_OEM_BIN_FILE)) oem.bin-type := raw + +add_vbt_to_cbfs= \ + $(eval cbfs-files-y += $1) \ + $(eval $1-file := $2) \ + $(eval $1-type := raw) \ + $(eval $1-compression := lzma) + +$(call add_vbt_to_cbfs, akali-data.vbt, akali-vbt.bin) +$(call add_vbt_to_cbfs, pantheon-data.vbt, pantheon-vbt.bin) +$(call add_vbt_to_cbfs, pantheon-data.vbt, pantheon-vbt.bin) +$(call add_vbt_to_cbfs, vayne-data.vbt, vayne-vbt.bin) +$(call add_vbt_to_cbfs, data.vbt, vbt.bin) diff --git a/src/mainboard/google/poppy/variants/nami/vbt-akali.bin b/src/mainboard/google/poppy/variants/nami/akali-data.vbt similarity index 100% rename from src/mainboard/google/poppy/variants/nami/vbt-akali.bin rename to src/mainboard/google/poppy/variants/nami/akali-data.vbt Binary files differ diff --git a/src/mainboard/google/poppy/variants/nami/data.vbt b/src/mainboard/google/poppy/variants/nami/data.vbt new file mode 100644 index 0000000..8406362 --- /dev/null +++ b/src/mainboard/google/poppy/variants/nami/data.vbt Binary files differ diff --git a/src/mainboard/google/poppy/variants/nami/patheon-data.vbt b/src/mainboard/google/poppy/variants/nami/patheon-data.vbt new file mode 100644 index 0000000..7e4fb0a --- /dev/null +++ b/src/mainboard/google/poppy/variants/nami/patheon-data.vbt Binary files differ diff --git a/src/mainboard/google/poppy/variants/nami/vayne-data.vbt b/src/mainboard/google/poppy/variants/nami/vayne-data.vbt new file mode 100644 index 0000000..7e4fb0a --- /dev/null +++ b/src/mainboard/google/poppy/variants/nami/vayne-data.vbt Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/30427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf49bdee7ae82a0a61192327351267f098eb5ab1 Gerrit-Change-Number: 30427 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 3

Change in ...coreboot[master]: nb/intel/i945: Use macro instead of magic number
by HAOUAS Elyes (Code Review) 10 May '19

10 May '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31027 Change subject: nb/intel/i945: Use macro instead of magic number ...................................................................... nb/intel/i945: Use macro instead of magic number Change-Id: I028013bd7511b5b9fc80e5f744fcad584cb25fd3 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/i945/raminit.c 2 files changed, 14 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/31027/1 diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 09a18e3..bc2f6f9 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -160,10 +160,10 @@ pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1); pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, 0x80); /* ACPI_CNTL: Enable ACPI BAR */ + pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x80); /* ACPI_CNTL: Enable ACPI BAR */ pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c, 0x10); /* GC: Enable GPIOs */ + pci_write_config8(PCI_DEV(0, 0x1f, 0), GPIO_CNTL, 0x10); /* GC: Enable GPIOs */ setup_pch_gpios(&mainboard_gpio_map); printk(BIOS_DEBUG, " done.\n"); diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 64c87da..ff866aa 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -246,13 +246,13 @@ u8 reg8; u8 do_reset = 0; - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2); if (reg8 & ((1<<7)|(1<<2))) { if (reg8 & (1<<2)) { printk(BIOS_DEBUG, "SLP S4# Assertion Width Violation.\n"); /* Write back clears bit 2 */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); do_reset = 1; } @@ -260,14 +260,14 @@ if (reg8 & (1<<7)) { printk(BIOS_DEBUG, "DRAM initialization was interrupted.\n"); reg8 &= ~(1<<7); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); do_reset = 1; } /* Set SLP_S3# Assertion Stretch Enable */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); /* GEN_PMCON_3 */ + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); reg8 |= (1 << 3); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); if (do_reset) { printk(BIOS_DEBUG, "Reset required.\n"); @@ -278,9 +278,9 @@ } /* Set DRAM initialization bit in ICH7 */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2); reg8 |= (1<<7); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); /* clear self refresh status if check is disabled or not a resume */ if (!CONFIG_CHECK_SLFRCS_ON_RESUME @@ -1810,9 +1810,9 @@ */ goto cache_code; vco_update: - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2); reg8 &= ~(1 << 7); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); clkcfg &= ~(1 << 10); MCHBAR32(CLKCFG) = clkcfg; @@ -2415,7 +2415,7 @@ MCHBAR32(REPC) |= (1 << 0); /* enable upper CMOS */ - RCBA32(0x3400) = (1 << 2); + RCBA32(RC) = (1 << 2); /* Program Receive Enable Timings */ if (sysinfo->boot_path == BOOT_PATH_RESUME) { @@ -2829,9 +2829,9 @@ sdram_enable_rcomp(); /* Tell ICH7 that we're done */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2); reg8 &= ~(1 << 7); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); printk(BIOS_DEBUG, "RAM initialization finished.\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/31027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I028013bd7511b5b9fc80e5f744fcad584cb25fd3 Gerrit-Change-Number: 31027 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

6 11

Change in ...coreboot[master]: soc/intel/cannonlake: Enable options for wakeup
by Lijian Zhao (Code Review) 10 May '19

10 May '19

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30447 Change subject: soc/intel/cannonlake: Enable options for wakeup ...................................................................... soc/intel/cannonlake: Enable options for wakeup Cannonlake FSP silicon init have dedicated wake up capability settings for several IP, expose the selection into coreboot. Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: I260e655417ca79d458784c9ec0e8e35d03b02e06 --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/fsp_params.c 2 files changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/30447/1 diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 3a723d2..e5a3ae1 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -302,6 +302,13 @@ /* SATA Power Optimizer */ uint8_t satapwroptimize; + + /* Wake Up Capability */ + uint8_t codec_wake_sx; + uint8_t pcie_wake_deepsx; + uint8_t wlan_wake_sx; + uint8_t wlan_wake_deepsx; + uint8_t glan_wake_deepsx; }; typedef struct soc_intel_cannonlake_config config_t; diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 78b27e9..9a24242 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -225,6 +225,14 @@ /* Power Optimizer */ params->PchPwrOptEnable = config->dmipwroptimize; params->SataPwrOptEnable = config->satapwroptimize; + + /* Wakeup Capability */ + params->PchHdaCodecSxWakeCapability = config->codec_wake_sx; + params->PchPmWoWlanEnable = config->wlan_wake_sx; + params->PchPmPcieWakeFromDeepSx = config->pcie_wake_deepsx; + params->PchPmWoWlanDeepSxEnable = config->wlan_wake_deepsx; + params->PchPmLanWakeFromDeepSx = config->glan_wake_deepsx; + } /* Mainboard GPIO Configuration */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30447 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I260e655417ca79d458784c9ec0e8e35d03b02e06 Gerrit-Change-Number: 30447 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit January 2019