coreboot-gerrit January 2019

coreboot-gerrit@coreboot.org

1 participants
1296 discussions

Change in ...coreboot[master]: google/buddy: adjust CID for realtek audio codec
by Matt DeVillier (Code Review) 30 Aug '19

30 Aug '19

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30564 Change subject: google/buddy: adjust CID for realtek audio codec ...................................................................... google/buddy: adjust CID for realtek audio codec Adjust CID to allow for Windows driver to attach without breaking functionality under Linux. Same change made as to google/cyan (which uses same Realtek RT5650 codec) in commit 607d72b. Test: build/boot Windowns 10 on google/buddy, observe audio drivers correctly attached to codec and Intel SST devices. Change-Id: I839acc8427ee9b5c425885858a513e9b0b9d0f93 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/30564/1 diff --git a/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl b/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl index 788fbdc..f4ed69e 100644 --- a/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl @@ -19,7 +19,7 @@ Device (RTEK) { Name (_HID, "10EC5650") - Name (_CID, "10EC5650") + Name (_CID, "INTCCFFD") Name (_DDN, "RTEK Codec Controller ") Name (_UID, 1) -- To view, visit https://review.coreboot.org/c/coreboot/+/30564 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I839acc8427ee9b5c425885858a513e9b0b9d0f93 Gerrit-Change-Number: 30564 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: soc/sifive/fu540: add support boot from sdcard
by Xiang Wang (Code Review) 27 Aug '19

27 Aug '19

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30901 Change subject: soc/sifive/fu540: add support boot from sdcard ...................................................................... soc/sifive/fu540: add support boot from sdcard Change-Id: Id97d293aee33082191cfaf47844769bdfa3d7a1b Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/mainboard/sifive/hifive-unleashed/Makefile.inc D src/mainboard/sifive/hifive-unleashed/bootblock.c A src/mainboard/sifive/hifive-unleashed/media.c M src/soc/sifive/fu540/Makefile.inc M src/soc/sifive/fu540/include/soc/memlayout.ld A src/soc/sifive/fu540/include/soc/sd.h D src/soc/sifive/fu540/media.c A src/soc/sifive/fu540/sd.c 8 files changed, 490 insertions(+), 58 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/30901/1 diff --git a/src/mainboard/sifive/hifive-unleashed/Makefile.inc b/src/mainboard/sifive/hifive-unleashed/Makefile.inc index 2dac283..54d97f7 100644 --- a/src/mainboard/sifive/hifive-unleashed/Makefile.inc +++ b/src/mainboard/sifive/hifive-unleashed/Makefile.inc @@ -11,12 +11,26 @@ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. +bootblock-y += memlayout.ld bootblock-y += flash.c -bootblock-y += bootblock.c +bootblock-y += media.c +romstage-y += memlayout.ld romstage-y += flash.c +romstage-y += media.c romstage-y += romstage.c -bootblock-y += memlayout.ld -romstage-y += memlayout.ld ramstage-y += memlayout.ld +ramstage-y += flash.c +ramstage-y += media.c + + +DTB=build/hifive-unleashed.dtb +DTS=src/mainboard/sifive/hifive-unleashed/hifive-unleashed.dts +$(DTB): $(DTS) + dtc -I dts -O dtb -o $(DTB) $(DTS) + +cbfs-files-y += fallback/DTB +fallback/DTB-file := $(DTB) +fallback/DTB-type := raw + diff --git a/src/mainboard/sifive/hifive-unleashed/bootblock.c b/src/mainboard/sifive/hifive-unleashed/bootblock.c deleted file mode 100644 index 777b2aa..0000000 --- a/src/mainboard/sifive/hifive-unleashed/bootblock.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 HardenedLinux - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <soc/addressmap.h> -#include <soc/spi.h> -#include <soc/spi_flash.h> -#include <soc/clock.h> - -extern void flash_init(void); -extern void bootblock_mainboard_init(void); - -void bootblock_mainboard_init(void) -{ - flash_init(); -} diff --git a/src/mainboard/sifive/hifive-unleashed/media.c b/src/mainboard/sifive/hifive-unleashed/media.c new file mode 100644 index 0000000..4a8f463 --- /dev/null +++ b/src/mainboard/sifive/hifive-unleashed/media.c @@ -0,0 +1,123 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 HardenedLinux + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boot_device.h> +#include <symbols.h> +#include <cbfs.h> +#include <arch/io.h> +#include <soc/addressmap.h> +#include <soc/spi.h> +#include <soc/sd.h> +#include <soc/clock.h> +#include <console/console.h> +#include <string.h> + +void flash_init(void); +// void boot_device_init(void); +// const struct region_device *boot_device_ro(void); + +/* At 0x20000000: A 256MiB long memory-mapped view of the flash at QSPI0 */ +static struct mem_region_device spi_mdev = + MEM_REGION_DEV_RO_INIT((void *)0x20000000, CONFIG_ROM_SIZE); + +static ssize_t unleashed_sd_readat(const struct region_device *rdev, void *dest, + size_t offset, size_t count) +{ + if (offset / 512 == (offset + count - 1) / 512) { + size_t lba = offset / 512; + size_t o = offset % 512; + size_t l = count; + uint8_t tmp[512]; + if (sd_copy((spi_ctrl*)FU540_QSPI2, tmp, lba, 1) != 0) { + return -1; + } + memcpy(dest, tmp + o, l); + } else { + int has_begin = !!(offset % 512); + int has_end = !!((offset + count) % 512); + size_t first_lba = offset / 512; + size_t last_lba = (offset + count - 1) / 512; + if (has_begin) { + size_t lba = first_lba; + size_t o = offset % 512; + size_t l = 512 - o; + uint8_t tmp[512]; + if (sd_copy((spi_ctrl*)FU540_QSPI2, tmp, lba, 1) != 0) { + return -1; + } + memcpy(dest, tmp + o, l); + } + if (first_lba + has_begin <= last_lba - has_end) { + size_t lba = first_lba + has_begin; + size_t size = (last_lba - has_end) - (first_lba + has_begin) + 1; + size_t o = 512 - offset % 512; + if (sd_copy((spi_ctrl*)FU540_QSPI2, dest + o, lba, size) != 0) { + return -1; + } + } + if (has_end) { + size_t lba = last_lba; + size_t o = 0; + size_t l = (offset + count) % 512; + uint8_t tmp[512]; + if (sd_copy((spi_ctrl*)FU540_QSPI2, tmp, lba, 1) != 0) { + return -1; + } + memcpy(dest + count - l, tmp + o, l); + } + } + return count; +} + +static const struct region_device_ops unleashed_sd_ops = { + .mmap = mmap_helper_rdev_mmap, + .munmap = mmap_helper_rdev_munmap, + .readat = unleashed_sd_readat, +}; + + +static struct mmap_helper_region_device sd_mdev = + MMAP_HELPER_REGION_INIT(&unleashed_sd_ops, 0, CONFIG_ROM_SIZE); + + +const struct region_device *boot_device_ro() +{ + switch(read32((uint32_t *)FU540_MSEL)) { + case 6: + case 10: + case 15: + return &spi_mdev.rdev; + case 11: + return &sd_mdev.rdev; + } + return NULL; +} + +void boot_device_init() +{ + switch(read32((uint32_t *)FU540_MSEL)) { + case 6: + case 10: + case 15: + flash_init(); + break; + case 11: + sd_init((spi_ctrl*)FU540_QSPI2, clock_get_tlclk_khz()); + mmap_helper_device_init(&sd_mdev, _cbfs_cache, _cbfs_cache_size); + break; + default: + die("Wrong configuration of MSEL"); + } +} diff --git a/src/soc/sifive/fu540/Makefile.inc b/src/soc/sifive/fu540/Makefile.inc index 83c7b1c..866267e 100644 --- a/src/soc/sifive/fu540/Makefile.inc +++ b/src/soc/sifive/fu540/Makefile.inc @@ -15,28 +15,31 @@ bootblock-y += uart.c bootblock-y += clint.c -bootblock-y += media.c +# bootblock-y += media.c bootblock-y += bootblock.c bootblock-y += clock.c bootblock-y += spi.c +bootblock-y += sd.c romstage-y += uart.c romstage-y += clint.c -romstage-y += media.c +# romstage-y += media.c romstage-y += sdram.c romstage-y += cbmem.c romstage-y += otp.c romstage-y += clock.c romstage-y += spi.c +romstage-y += sd.c ramstage-y += uart.c ramstage-y += clint.c -ramstage-y += media.c +# ramstage-y += media.c ramstage-y += sdram.c ramstage-y += cbmem.c ramstage-y += otp.c ramstage-y += clock.c ramstage-y += spi.c +ramstage-y += sd.c CPPFLAGS_common += -Isrc/soc/sifive/fu540/include diff --git a/src/soc/sifive/fu540/include/soc/memlayout.ld b/src/soc/sifive/fu540/include/soc/memlayout.ld index b9b9c47..81a7f9b 100644 --- a/src/soc/sifive/fu540/include/soc/memlayout.ld +++ b/src/soc/sifive/fu540/include/soc/memlayout.ld @@ -28,9 +28,11 @@ CAR_STACK(FU540_L2LIM + 64K, 20K) PRERAM_CBMEM_CONSOLE(FU540_L2LIM + 84K, 8K) ROMSTAGE(FU540_L2LIM + 128K, 128K) + PRERAM_CBFS_CACHE(FU540_L2LIM + 256K, 128K) L2LIM_END(FU540_L2LIM + 2M) DRAM_START(FU540_DRAM) RAMSTAGE(FU540_DRAM, 256K) MEM_STACK(FU540_DRAM + 256K, 20K) + POSTRAM_CBFS_CACHE(FU540_DRAM + 512K, 32M - 512K) } diff --git a/src/soc/sifive/fu540/include/soc/sd.h b/src/soc/sifive/fu540/include/soc/sd.h new file mode 100644 index 0000000..679d0f4 --- /dev/null +++ b/src/soc/sifive/fu540/include/soc/sd.h @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 SiFive, Inc + * Copyright (C) 2019 HardenedLinux + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#ifndef _LIBRARIES_SD_H +#define _LIBRARIES_SD_H + +#define SD_INIT_ERROR_CMD0 1 +#define SD_INIT_ERROR_CMD8 2 +#define SD_INIT_ERROR_ACMD41 3 +#define SD_INIT_ERROR_CMD58 4 +#define SD_INIT_ERROR_CMD16 5 + +#define SD_COPY_ERROR_CMD18 1 +#define SD_COPY_ERROR_CMD18_CRC 2 + +#ifndef __ASSEMBLER__ + +#include <stdint.h> +#include <stddef.h> + +int sd_init(spi_ctrl* spi, unsigned int input_clk_hz); +int sd_copy(spi_ctrl* spi, void* dst, uint32_t src_lba, size_t size); + +#endif /* !__ASSEMBLER__ */ + +#endif /* _LIBRARIES_SD_H */ diff --git a/src/soc/sifive/fu540/media.c b/src/soc/sifive/fu540/media.c deleted file mode 100644 index 7b9ccb0..0000000 --- a/src/soc/sifive/fu540/media.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Jonathan Neuschäfer - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <boot_device.h> - -/* At 0x20000000: A 256MiB long memory-mapped view of the flash at QSPI0 */ -static struct mem_region_device mdev = - MEM_REGION_DEV_RO_INIT((void *)0x20000000, CONFIG_ROM_SIZE); - -const struct region_device *boot_device_ro(void) -{ - return &mdev.rdev; -} diff --git a/src/soc/sifive/fu540/sd.c b/src/soc/sifive/fu540/sd.c new file mode 100644 index 0000000..3af26ad --- /dev/null +++ b/src/soc/sifive/fu540/sd.c @@ -0,0 +1,302 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 SiFive, Inc + * Copyright (C) 2019 HardenedLinux + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <mcall.h> +#include <arch/io.h> +#include <soc/spi.h> +#include <soc/sd.h> + + +#define SPI_DIR_RX 0 +#define SPI_DIR_TX 1 + +#define SPI_ENDIAN_MSB 0 +#define SPI_ENDIAN_LSB 1 + +#define SPI_CSMODE_AUTO 0 +#define SPI_CSMODE_HOLD 2 +#define SPI_CSMODE_OFF 3 + +#define SPI_PROTO_S 0 +#define SPI_PROTO_D 1 +#define SPI_PROTO_Q 2 + +#define SD_CMD_GO_IDLE_STATE 0 +#define SD_CMD_SEND_IF_COND 8 +#define SD_CMD_STOP_TRANSMISSION 12 +#define SD_CMD_SET_BLOCKLEN 16 +#define SD_CMD_READ_BLOCK_MULTIPLE 18 +#define SD_CMD_APP_SEND_OP_COND 41 +#define SD_CMD_APP_CMD 55 +#define SD_CMD_READ_OCR 58 +#define SD_RESPONSE_IDLE 0x1 +// Data token for commands 17, 18, 24 +#define SD_DATA_TOKEN 0xfe + + +// SD card initialization must happen at 100-400kHz +#define SD_POWER_ON_FREQ_KHZ 400L +// SD cards normally support reading/writing at 20MHz +#define SD_POST_INIT_CLK_KHZ 20000L + + +// Command frame starts by asserting low and then high for first two clock edges +#define SD_CMD(cmd) (0x40 | (cmd)) + + +/** + * Send dummy byte (all ones). + * + * Used in many cases to read one byte from SD card, since SPI is a full-duplex + * protocol and it is necessary to send a byte in order to read a byte. + */ +static inline uint8_t sd_dummy(spi_ctrl* spi) +{ + return spi_txrx(spi, 0xFF); +} + + +static int sd_cmd(spi_ctrl* spi, uint8_t cmd, uint32_t arg, uint8_t crc) +{ + unsigned long n; + uint8_t r; + + spi->csmode.mode = SPI_CSMODE_HOLD; + sd_dummy(spi); + spi_txrx(spi, cmd); + spi_txrx(spi, arg >> 24); + spi_txrx(spi, arg >> 16); + spi_txrx(spi, arg >> 8); + spi_txrx(spi, arg); + spi_txrx(spi, crc); + + n = 1000; + do { + r = sd_dummy(spi); + if (!(r & 0x80)) { + break; + } + } while (--n > 0); + return r; +} + + +static inline void sd_cmd_end(spi_ctrl* spi) +{ + sd_dummy(spi); + spi->csmode.mode = SPI_CSMODE_AUTO; +} + + +static void sd_poweron(spi_ctrl* spi, unsigned int input_clk_khz) +{ + // Initialize SPI controller + spi->fmt.raw_bits = ((spi_reg_fmt) { + .proto = SPI_PROTO_S, + .dir = SPI_DIR_RX, + .endian = SPI_ENDIAN_MSB, + .len = 8, + }).raw_bits; + spi->csdef |= 0x1; + spi->csid = 0; + + spi->sckdiv = spi_min_clk_divisor(input_clk_khz, SD_POWER_ON_FREQ_KHZ); + spi->csmode.mode = SPI_CSMODE_OFF; + + for (int i = 10; i > 0; i--) { + // Set SD card pin DI high for 74+ cycles + // SD CMD pin is the same pin as SPI DI, so CMD = 0xff means assert DI high + // for 8 cycles. + sd_dummy(spi); + } + + spi->csmode.mode = SPI_CSMODE_AUTO; +} + + +/** + * Reset card. + */ +static int sd_cmd0(spi_ctrl* spi) +{ + int rc; + rc = (sd_cmd(spi, SD_CMD(SD_CMD_GO_IDLE_STATE), 0, 0x95) != SD_RESPONSE_IDLE); + sd_cmd_end(spi); + return rc; +} + + +/** + * Check for SD version and supported voltages. + */ +static int sd_cmd8(spi_ctrl* spi) +{ + // Check for high capacity cards + // Fail if card does not support SDHC + int rc; + rc = (sd_cmd(spi, SD_CMD(SD_CMD_SEND_IF_COND), 0x000001AA, 0x87) != SD_RESPONSE_IDLE); + sd_dummy(spi); /* command version; reserved */ + sd_dummy(spi); /* reserved */ + rc |= ((sd_dummy(spi) & 0xF) != 0x1); /* voltage */ + rc |= (sd_dummy(spi) != 0xAA); /* check pattern */ + sd_cmd_end(spi); + return rc; +} + + +/** + * Send app command. Used as prefix to app commands (ACMD). + */ +static void sd_cmd55(spi_ctrl* spi) +{ + sd_cmd(spi, SD_CMD(SD_CMD_APP_CMD), 0, 0x65); + sd_cmd_end(spi); +} + + +/** + * Start SDC initialization process. + */ +static int sd_acmd41(spi_ctrl* spi) +{ + uint8_t r; + do { + sd_cmd55(spi); + r = sd_cmd(spi, SD_CMD(SD_CMD_APP_SEND_OP_COND), 0x40000000, 0x77); /* HCS = 1 */ + sd_cmd_end(spi); + } while (r == SD_RESPONSE_IDLE); + return (r != 0x00); +} + + +/** + * Read operation conditions register (OCR) to check for availability of block + * addressing mode. + */ +static int sd_cmd58(spi_ctrl* spi) +{ + // HACK: Disabled due to bugs. It is not strictly necessary + // to issue this command if we only support SD cards that support SDHC mode. + return 0; + // int rc; + // rc = (sd_cmd(spi, SD_CMD(SD_CMD_READ_OCR), 0, 0xFD) != 0x00); + // rc |= ((sd_dummy(spi) & 0x80) != 0x80); /* Power up status */ + // sd_dummy(spi); /* Supported voltages */ + // sd_dummy(spi); /* Supported voltages */ + // sd_dummy(spi); /* Supported voltages */ + // sd_cmd_end(spi); + // return rc; +} + + +/** + * Set block addressing mode. + */ +static int sd_cmd16(spi_ctrl* spi) +{ + int rc; + rc = (sd_cmd(spi, SD_CMD(SD_CMD_SET_BLOCKLEN), 0x200, 0x15) != 0x00); + sd_cmd_end(spi); + return rc; +} + + +static uint8_t crc7(uint8_t prev, uint8_t in) +{ + // CRC polynomial 0x89 + uint8_t remainder = prev & in; + remainder ^= (remainder >> 4) ^ (remainder >> 7); + remainder ^= remainder << 4; + return remainder & 0x7f; +} + + +static uint16_t crc16(uint16_t crc, uint8_t data) +{ + // CRC polynomial 0x11021 + crc = (uint8_t)(crc >> 8) | (crc << 8); + crc ^= data; + crc ^= (uint8_t)(crc >> 4) & 0xf; + crc ^= crc << 12; + crc ^= (crc & 0xff) << 5; + return crc; +} + + +//int sd_init(spi_ctrl* spi, unsigned int input_clk_khz, int skip_sd_init_commands) +int sd_init(spi_ctrl* spi, unsigned int input_clk_khz) +{ + sd_poweron(spi, input_clk_khz); + if (sd_cmd0(spi)) + return SD_INIT_ERROR_CMD0; + if (sd_cmd8(spi)) + return SD_INIT_ERROR_CMD8; + if (sd_acmd41(spi)) + return SD_INIT_ERROR_ACMD41; + if (sd_cmd58(spi)) + return SD_INIT_ERROR_CMD58; + if (sd_cmd16(spi)) + return SD_INIT_ERROR_CMD16; + + // Increase clock frequency after initialization for higher performance. + spi->sckdiv = spi_min_clk_divisor(input_clk_khz, SD_POST_INIT_CLK_KHZ); + return 0; +} + + +int sd_copy(spi_ctrl* spi, void* dst, uint32_t src_lba, size_t size) +{ + volatile uint8_t *p = dst; + long i = size; + int rc = 0; + + uint8_t c = 0; + c = crc7(c, SD_CMD(SD_CMD_READ_BLOCK_MULTIPLE)); + c = crc7(c, src_lba >> 24); + c = crc7(c, (src_lba >> 16) & 0xff); + c = crc7(c, (src_lba >> 8) & 0xff); + c = crc7(c, src_lba & 0xff); + c = (c << 1) | 1; + if (sd_cmd(spi, SD_CMD(SD_CMD_READ_BLOCK_MULTIPLE), src_lba, c) != 0x00) { + sd_cmd_end(spi); + return SD_COPY_ERROR_CMD18; + } + do { + uint16_t crc, crc_exp; + long n; + + crc = 0; + n = 512; + while (sd_dummy(spi) != SD_DATA_TOKEN); + do { + uint8_t x = sd_dummy(spi); + *p++ = x; + crc = crc16(crc, x); + } while (--n > 0); + + crc_exp = ((uint16_t)sd_dummy(spi) << 8); + crc_exp |= sd_dummy(spi); + + if (crc != crc_exp) { + rc = SD_COPY_ERROR_CMD18_CRC; + break; + } + } while (--i > 0); + + sd_cmd(spi, SD_CMD(SD_CMD_STOP_TRANSMISSION), 0, 0x01); + sd_cmd_end(spi); + return rc; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/30901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id97d293aee33082191cfaf47844769bdfa3d7a1b Gerrit-Change-Number: 30901 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-MessageType: newchange

4 25

Change in ...coreboot[master]: mediatek/mt8183: Add I2C driver code
by wang qii (Code Review) 07 Aug '19

07 Aug '19

wang qii has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30976 Change subject: mediatek/mt8183: Add I2C driver code ...................................................................... mediatek/mt8183: Add I2C driver code This patch implements i2c driver for MT8183. BUG=b:80501386 BRANCH=none TEST=Boot correctly on kukui. Change-Id: I0a4d78b494819f45951f78e5a618021000cf3463 Signed-off-by: qii wang <qii.wang(a)mediatek.com> --- M src/soc/mediatek/mt8183/Makefile.inc A src/soc/mediatek/mt8183/i2c.c M src/soc/mediatek/mt8183/include/soc/addressmap.h A src/soc/mediatek/mt8183/include/soc/i2c.h 4 files changed, 236 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/30976/1 diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index 9aa1733..b0a148f 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -5,6 +5,7 @@ bootblock-y += ../common/gpio.c gpio.c bootblock-y += ../common/pll.c pll.c bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c +bootblock-y += ../common/i2c.c i2c.c bootblock-y += ../common/timer.c bootblock-y += ../common/uart.c bootblock-y += ../common/wdt.c @@ -16,6 +17,7 @@ verstage-y += auxadc.c verstage-y += ../common/gpio.c gpio.c verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c +verstage-y += ../common/i2c.c i2c.c verstage-y += ../common/timer.c verstage-y += ../common/uart.c verstage-y += ../common/wdt.c @@ -31,6 +33,7 @@ romstage-y += ../common/mmu_operations.c mmu_operations.c romstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6358.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c +romstage-y += ../common/i2c.c i2c.c romstage-y += ../common/timer.c romstage-y += ../common/uart.c romstage-y += ../common/wdt.c @@ -42,6 +45,7 @@ ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-y += soc.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c +ramstage-y += ../common/i2c.c i2c.c ramstage-y += ../common/timer.c ramstage-y += ../common/uart.c ramstage-y += ../common/usb.c diff --git a/src/soc/mediatek/mt8183/i2c.c b/src/soc/mediatek/mt8183/i2c.c new file mode 100644 index 0000000..f389caf --- /dev/null +++ b/src/soc/mediatek/mt8183/i2c.c @@ -0,0 +1,171 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <arch/io.h> +#include <soc/pll.h> +#include <soc/i2c.h> +#include <soc/gpio.h> + +#define I2C_CLK_HZ (UNIVPLL_HZ / 30) + +struct mtk_i2c mtk_i2c_bus_controller[] = { + /* i2c0 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0x2000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE), + }, + + /* i2c1 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0xc000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x400), + }, + + /* i2c2 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0x4000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x200), + }, + + /* i2c3 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0xa000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x380), + }, + + /* i2c4 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0x3000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x80), + }, + + /* i2c5 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0x11000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x480), + }, + + /* i2c6 setting */ + { + .i2c_regs = (void *)(I2C_BASE), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x580), + }, + + /* i2c7 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0x15000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x600), + }, + + /* i2c8 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0x16000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x680), + } +}; + +#define I2C_BUS_NUMBER ARRAY_SIZE(mtk_i2c_bus_controller) + +struct pad_func { + gpio_t gpio; + u8 func; +}; + +#define PAD_FUNC(name, func) {GPIO(name), PAD_##name##_FUNC_##func} + +static const struct pad_func i2c_funcs[I2C_BUS_NUMBER][2] = { + { + PAD_FUNC(SDA0, SDA0), + PAD_FUNC(SCL0, SCL0), + }, + { + PAD_FUNC(SDA1, SDA1), + PAD_FUNC(SCL1, SCL1), + }, + { + PAD_FUNC(SDA2, SDA2), + PAD_FUNC(SCL2, SCL2), + }, + { + PAD_FUNC(SDA3, SDA3), + PAD_FUNC(SCL3, SCL3), + }, + { + PAD_FUNC(SDA4, SDA4), + PAD_FUNC(SCL4, SCL4), + }, + { + PAD_FUNC(SDA5, SDA5), + PAD_FUNC(SCL5, SCL5), + }, + { + PAD_FUNC(CONN_TOP_DATA, SDA6), + PAD_FUNC(CONN_TOP_CLK, SCL6), + }, + { + }, + { + PAD_FUNC(CAM_RST2, SDA8), + PAD_FUNC(CAM_CLK2, SCL8), + }, +}; + +static void mtk_i2c_set_gpio_pinmux(uint8_t bus) +{ + assert(bus < I2C_BUS_NUMBER && bus != 7); + + const struct pad_func *ptr = i2c_funcs[bus]; + for (size_t i = 0; i < 2; i++) { + gpio_set_mode(ptr[i].gpio, ptr[i].func); + gpio_set_pull(ptr[i].gpio, GPIO_PULL_ENABLE, GPIO_PULL_UP); + if (bus < 6) { + gpio_set_i2c_eh(ptr[i].gpio, 0); + gpio_set_i2c_rsel(ptr[i].gpio, 3); + } + } +} + +static void mtk_i2c_speed_init(uint8_t bus) +{ + uint8_t step_div; + const uint8_t clock_div = 5; + const uint8_t sample_div = 1; + uint32_t i2c_freq; + + assert(bus < ARRAY_SIZE(mtk_i2c_bus_controller)); + + /* Calculate i2c frequency */ + step_div = DIV_ROUND_UP(I2C_CLK_HZ, + (400 * KHz * sample_div * 2) * clock_div); + i2c_freq = I2C_CLK_HZ / (step_div * sample_div * 2 * clock_div); + assert(sample_div < 8 && step_div < 64 && i2c_freq <= 400 * KHz && + i2c_freq >= 380 * KHz); + + /* Init i2c bus Timing register */ + write32(&mtk_i2c_bus_controller[bus].i2c_regs->timing, + (sample_div - 1) << 8 | (step_div - 1)); + write32(&mtk_i2c_bus_controller[bus].i2c_regs->ltiming, + (sample_div - 1) << 6 | (step_div - 1)); + + /* Init i2c bus clock_div register */ + write32(&mtk_i2c_bus_controller[bus].i2c_regs->clock_div, clock_div - 1); +} + +void mtk_i2c_init(uint8_t bus) +{ + mtk_i2c_speed_init(bus); + mtk_i2c_set_gpio_pinmux(bus); +} diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h index d41b2b9..aaa77a3 100644 --- a/src/soc/mediatek/mt8183/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h @@ -34,8 +34,10 @@ EMI_BASE = IO_PHYS + 0x00219000, EMI_MPU_BASE = IO_PHYS + 0x00226000, DRAMC_CH_BASE = IO_PHYS + 0x00228000, + I2C_DMA_BASE = IO_PHYS + 0x01000080, AUXADC_BASE = IO_PHYS + 0x01001000, UART0_BASE = IO_PHYS + 0x01002000, + I2C_BASE = IO_PHYS + 0x01005000, SPI0_BASE = IO_PHYS + 0x0100A000, SPI1_BASE = IO_PHYS + 0x01010000, SPI2_BASE = IO_PHYS + 0x01012000, diff --git a/src/soc/mediatek/mt8183/include/soc/i2c.h b/src/soc/mediatek/mt8183/include/soc/i2c.h new file mode 100755 index 0000000..dbf9cbf --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/i2c.h @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_MEDIATEK_MT8183_I2C_H +#define SOC_MEDIATEK_MT8183_I2C_H + +#include <soc/i2c_common.h> + +/* I2C Register */ +struct mt_i2c_regs { + uint32_t data_port; + uint32_t slave_addr; + uint32_t intr_mask; + uint32_t intr_stat; + uint32_t control; + uint32_t transfer_len; + uint32_t transac_len; + uint32_t delay_len; + uint32_t timing; + uint32_t start; + uint32_t ext_conf; + uint32_t ltiming; + uint32_t hs; + uint32_t io_config; + uint32_t fifo_addr_clr; + uint32_t reserved0[2]; + uint32_t transfer_aux_len; + uint32_t clock_div; + uint32_t time_out; + uint32_t softreset; + uint32_t reserved1[36]; + uint32_t debug_stat; + uint32_t debug_ctrl; + uint32_t reserved2[2]; + uint32_t fifo_stat; + uint32_t fifo_thresh; + uint32_t reserved3[932]; + uint32_t multi_dma; + uint32_t reserved4[2]; + uint32_t rollback; +}; + +check_member(mt_i2c_regs, multi_dma, 0xf8c); + +void mtk_i2c_init(uint8_t bus); + +#endif /* SOC_MEDIATEK_MT8183_I2C_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30976 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a4d78b494819f45951f78e5a618021000cf3463 Gerrit-Change-Number: 30976 Gerrit-PatchSet: 1 Gerrit-Owner: wang qii <Qii.Wang(a)mediatek.com> Gerrit-MessageType: newchange

7 22

Change in ...coreboot[master]: mediatek: Refactor I2C code among similar SOCs
by wang qii (Code Review) 02 Aug '19

02 Aug '19

wang qii has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30975 Change subject: mediatek: Refactor I2C code among similar SOCs ...................................................................... mediatek: Refactor I2C code among similar SOCs Refactor I2C code which will be reused among similar SOCs. BUG=b:80501386 BRANCH=none TEST=emerge-elm coreboot Change-Id: I407d5e2a9eb29562b40bb300e39f206a94afe76c Signed-off-by: qii wang <qii.wang(a)mediatek.com> --- A src/soc/mediatek/common/i2c.c A src/soc/mediatek/common/include/soc/i2c_common.h M src/soc/mediatek/mt8173/Makefile.inc M src/soc/mediatek/mt8173/i2c.c M src/soc/mediatek/mt8173/include/soc/i2c.h 5 files changed, 390 insertions(+), 354 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/30975/1 diff --git a/src/soc/mediatek/common/i2c.c b/src/soc/mediatek/common/i2c.c new file mode 100644 index 0000000..73414ac --- /dev/null +++ b/src/soc/mediatek/common/i2c.c @@ -0,0 +1,273 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <assert.h> +#include <delay.h> +#include <timer.h> +#include <symbols.h> +#include <arch/io.h> +#include <soc/i2c.h> +#include <device/i2c_simple.h> + +static inline void i2c_dma_reset(struct mt_i2c_dma_regs *dma_regs) +{ + write32(&dma_regs->dma_rst, 0x1); + udelay(50); + write32(&dma_regs->dma_rst, 0x2); + udelay(50); + write32(&dma_regs->dma_rst, 0x0); + udelay(50); +} + +static inline void mtk_i2c_dump_info(uint8_t bus) +{ + struct mt_i2c_regs *regs; + + regs = mtk_i2c_bus_controller[bus].i2c_regs; + + printk(BIOS_ERR, "I2C register:\nSLAVE_ADDR %x\nINTR_MASK %x\n" + "INTR_STAT %x\nCONTROL %x\nTRANSFER_LEN %x\nTRANSAC_LEN %x\n" + "DELAY_LEN %x\nTIMING %x\nSTART %x\nFIFO_STAT %x\nIO_CONFIG %x\n" + "HS %x\nDEBUGSTAT %x\nEXT_CONF %x\n", + (read32(&regs->slave_addr)), + (read32(&regs->intr_mask)), + (read32(&regs->intr_stat)), + (read32(&regs->control)), + (read32(&regs->transfer_len)), + (read32(&regs->transac_len)), + (read32(&regs->delay_len)), + (read32(&regs->timing)), + (read32(&regs->start)), + (read32(&regs->fifo_stat)), + (read32(&regs->io_config)), + (read32(&regs->hs)), + (read32(&regs->debug_stat)), + (read32(&regs->ext_conf))); +} + +static uint32_t mtk_i2c_transfer(uint8_t bus, struct i2c_msg *seg, + enum i2c_modes read) +{ + uint32_t ret_code = I2C_OK; + uint16_t status; + uint32_t time_out_val = 0; + uint8_t addr; + uint32_t write_len = 0; + uint32_t read_len = 0; + uint8_t *write_buffer = NULL; + uint8_t *read_buffer = NULL; + struct mt_i2c_regs *regs; + struct mt_i2c_dma_regs *dma_regs; + struct stopwatch sw; + + regs = mtk_i2c_bus_controller[bus].i2c_regs; + dma_regs = mtk_i2c_bus_controller[bus].i2c_dma_regs; + + addr = seg[0].slave; + + switch (read) { + case I2C_WRITE_MODE: + assert(seg[0].len > 0 && seg[0].len <= 255); + write_len = seg[0].len; + write_buffer = seg[0].buf; + break; + + case I2C_READ_MODE: + assert(seg[0].len > 0 && seg[0].len <= 255); + read_len = seg[0].len; + read_buffer = seg[0].buf; + break; + + /* Must use special write-then-read mode for repeated starts. */ + case I2C_WRITE_READ_MODE: + assert(seg[0].len > 0 && seg[0].len <= 255); + assert(seg[1].len > 0 && seg[1].len <= 255); + write_len = seg[0].len; + read_len = seg[1].len; + write_buffer = seg[0].buf; + read_buffer = seg[1].buf; + break; + } + + /* Clear interrupt status */ + write32(&regs->intr_stat, I2C_TRANSAC_COMP | I2C_ACKERR | + I2C_HS_NACKERR); + + write32(&regs->fifo_addr_clr, 0x1); + + /* Enable interrupt */ + write32(&regs->intr_mask, I2C_HS_NACKERR | I2C_ACKERR | + I2C_TRANSAC_COMP); + + switch (read) { + case I2C_WRITE_MODE: + memcpy(_dma_coherent, write_buffer, write_len); + + /* control registers */ + write32(&regs->control, ASYNC_MODE | DMAACK_EN | + ACK_ERR_DET_EN | DMA_EN | CLK_EXT | + REPEATED_START_FLAG); + + /* Set transfer and transaction len */ + write32(&regs->transac_len, 1); + write32(&regs->transfer_len, write_len); + + /* set i2c write slave address*/ + write32(&regs->slave_addr, addr << 1); + + /* Prepare buffer data to start transfer */ + write32(&dma_regs->dma_con, I2C_DMA_CON_TX); + write32(&dma_regs->dma_tx_mem_addr, (uintptr_t)_dma_coherent); + write32(&dma_regs->dma_tx_len, write_len); + break; + + case I2C_READ_MODE: + /* control registers */ + write32(&regs->control, ASYNC_MODE | DMAACK_EN | + ACK_ERR_DET_EN | DMA_EN | CLK_EXT | + REPEATED_START_FLAG); + + /* Set transfer and transaction len */ + write32(&regs->transac_len, 1); + write32(&regs->transfer_len, read_len); + + /* set i2c read slave address*/ + write32(&regs->slave_addr, (addr << 1 | 0x1)); + + /* Prepare buffer data to start transfer */ + write32(&dma_regs->dma_con, I2C_DMA_CON_RX); + write32(&dma_regs->dma_rx_mem_addr, (uintptr_t)_dma_coherent); + write32(&dma_regs->dma_rx_len, read_len); + break; + + case I2C_WRITE_READ_MODE: + memcpy(_dma_coherent, write_buffer, write_len); + + /* control registers */ + write32(&regs->control, ASYNC_MODE | DMAACK_EN | + DIR_CHG | ACK_ERR_DET_EN | DMA_EN | + CLK_EXT | REPEATED_START_FLAG); + + /* Set transfer and transaction len */ + write32(&regs->transfer_len, write_len); + write32(&regs->transfer_aux_len, read_len); + write32(&regs->transac_len, 2); + + /* set i2c write slave address*/ + write32(&regs->slave_addr, addr << 1); + + /* Prepare buffer data to start transfer */ + write32(&dma_regs->dma_con, I2C_DMA_CLR_FLAG); + write32(&dma_regs->dma_tx_mem_addr, (uintptr_t)_dma_coherent); + write32(&dma_regs->dma_tx_len, write_len); + write32(&dma_regs->dma_rx_mem_addr, (uintptr_t)_dma_coherent); + write32(&dma_regs->dma_rx_len, read_len); + break; + } + + write32(&dma_regs->dma_int_flag, I2C_DMA_CLR_FLAG); + write32(&dma_regs->dma_en, I2C_DMA_START_EN); + + /* start transfer transaction */ + write32(&regs->start, 0x1); + + stopwatch_init_msecs_expire(&sw, 100); + + /* polling mode : see if transaction complete */ + while (1) { + status = read32(&regs->intr_stat); + if (status & I2C_HS_NACKERR) { + ret_code = I2C_TRANSFER_FAIL_HS_NACKERR; + printk(BIOS_ERR, "[i2c%d] transfer NACK error\n", bus); + mtk_i2c_dump_info(bus); + break; + } else if (status & I2C_ACKERR) { + ret_code = I2C_TRANSFER_FAIL_ACKERR; + printk(BIOS_ERR, "[i2c%d] transfer ACK error\n", bus); + mtk_i2c_dump_info(bus); + break; + } else if (status & I2C_TRANSAC_COMP) { + ret_code = I2C_OK; + memcpy(read_buffer, _dma_coherent, read_len); + break; + } + + if (stopwatch_expired(&sw)) { + ret_code = I2C_TRANSFER_FAIL_TIMEOUT; + printk(BIOS_ERR, "[i2c%d] transfer timeout:%d\n", bus, + time_out_val); + mtk_i2c_dump_info(bus); + break; + } + } + + write32(&regs->intr_stat, I2C_TRANSAC_COMP | I2C_ACKERR | + I2C_HS_NACKERR); + + /* clear bit mask */ + write32(&regs->intr_mask, I2C_HS_NACKERR | I2C_ACKERR | + I2C_TRANSAC_COMP); + + /* reset the i2c controller for next i2c transfer. */ + write32(&regs->softreset, 0x1); + + i2c_dma_reset(dma_regs); + + return ret_code; +} + +static uint8_t mtk_i2c_should_combine(struct i2c_msg *seg, int left_count) +{ + if (left_count >= 2 && + !(seg[0].flags & I2C_M_RD) && + (seg[1].flags & I2C_M_RD) && + seg[0].slave == seg[1].slave) + return 1; + else + return 0; +} + +int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segments, + int seg_count) +{ + int ret = 0; + int i; + int read; + + for (i = 0; i < seg_count; i++) { + if (mtk_i2c_should_combine(&segments[i], seg_count - i)) { + read = I2C_WRITE_READ_MODE; + } else { + read = (segments[i].flags & I2C_M_RD) ? + I2C_READ_MODE : I2C_WRITE_MODE; + } + + ret = mtk_i2c_transfer(bus, &segments[i], read); + + if (ret) + break; + + if (read == I2C_WRITE_READ_MODE) + i++; + } + + return ret; +} + +void mtk_i2c_bus_init(uint8_t bus) +{ + mtk_i2c_init(bus); +} diff --git a/src/soc/mediatek/common/include/soc/i2c_common.h b/src/soc/mediatek/common/include/soc/i2c_common.h new file mode 100755 index 0000000..e455f35 --- /dev/null +++ b/src/soc/mediatek/common/include/soc/i2c_common.h @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MTK_COMMON_I2C_H +#define MTK_COMMON_I2C_H + +/* I2C DMA Registers */ +struct mt_i2c_dma_regs { + uint32_t dma_int_flag; + uint32_t dma_int_en; + uint32_t dma_en; + uint32_t dma_rst; + uint32_t reserved1; + uint32_t dma_flush; + uint32_t dma_con; + uint32_t dma_tx_mem_addr; + uint32_t dma_rx_mem_addr; + uint32_t dma_tx_len; + uint32_t dma_rx_len; +}; + +check_member(mt_i2c_dma_regs, dma_tx_len, 0x24); + +/* I2C Configuration */ +enum { + I2C_HS_DEFAULT_VALUE = 0x0102, +}; + +enum i2c_modes { + I2C_WRITE_MODE = 0, + I2C_READ_MODE = 1, + I2C_WRITE_READ_MODE = 2, +}; + +enum { + I2C_DMA_CON_TX = 0x0, + I2C_DMA_CON_RX = 0x1, + I2C_DMA_START_EN = 0x1, + I2C_DMA_INT_FLAG_NONE = 0x0, + I2C_DMA_CLR_FLAG = 0x0, + I2C_DMA_FLUSH_FLAG = 0x1, +}; + +enum { + I2C_TRANS_LEN_MASK = (0xff), + I2C_TRANS_AUX_LEN_MASK = (0x1f << 8), + I2C_CONTROL_MASK = (0x3f << 1) +}; + +/* Register mask */ +enum { + I2C_HS_NACKERR = (1 << 2), + I2C_ACKERR = (1 << 1), + I2C_TRANSAC_COMP = (1 << 0), +}; + +/* i2c control bits */ +enum { + ASYNC_MODE = (1 << 9), + DMAACK_EN = (1 << 8), + ACK_ERR_DET_EN = (1 << 5), + DIR_CHG = (1 << 4), + CLK_EXT = (1 << 3), + DMA_EN = (1 << 2), + REPEATED_START_FLAG = (1 << 1), + STOP_FLAG = (0 << 1) +}; + +/* I2C Status Code */ + +enum { + I2C_OK = 0x0000, + I2C_SET_SPEED_FAIL_OVER_SPEED = 0xA001, + I2C_TRANSFER_INVALID_LENGTH = 0xA002, + I2C_TRANSFER_FAIL_HS_NACKERR = 0xA003, + I2C_TRANSFER_FAIL_ACKERR = 0xA004, + I2C_TRANSFER_FAIL_TIMEOUT = 0xA005, + I2C_TRANSFER_INVALID_ARGUMENT = 0xA006 +}; + +struct mtk_i2c { + struct mt_i2c_regs *i2c_regs; + struct mt_i2c_dma_regs *i2c_dma_regs; +}; + +extern struct mtk_i2c mtk_i2c_bus_controller[]; + +void mtk_i2c_bus_init(uint8_t bus); +#endif diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc index b004c27..5a54d6d 100644 --- a/src/soc/mediatek/mt8173/Makefile.inc +++ b/src/soc/mediatek/mt8173/Makefile.inc @@ -17,7 +17,7 @@ bootblock-y += bootblock.c bootblock-$(CONFIG_SPI_FLASH) += flash_controller.c -bootblock-y += i2c.c +bootblock-y += ../common/i2c.c i2c.c bootblock-y += ../common/pll.c pll.c bootblock-y += ../common/spi.c spi.c bootblock-y += ../common/timer.c @@ -32,7 +32,7 @@ ################################################################################ -verstage-y += i2c.c +verstage-y += ../common/i2c.c i2c.c verstage-y += ../common/spi.c spi.c verstage-y += ../common/uart.c @@ -49,7 +49,7 @@ romstage-y += ../common/pll.c pll.c romstage-y += ../common/timer.c romstage-y += timer.c -romstage-y += i2c.c +romstage-y += ../common/i2c.c i2c.c romstage-y += ../common/uart.c romstage-y += ../common/cbmem.c @@ -71,7 +71,8 @@ ramstage-y += ../common/timer.c ramstage-y += timer.c ramstage-y += ../common/uart.c -ramstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6391.c i2c.c +ramstage-y += ../common/i2c.c i2c.c +ramstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6391.c ramstage-y += mt6311.c ramstage-y += da9212.c ramstage-y += ../common/gpio.c gpio.c diff --git a/src/soc/mediatek/mt8173/i2c.c b/src/soc/mediatek/mt8173/i2c.c index b4c3aa9..85f676c 100644 --- a/src/soc/mediatek/mt8173/i2c.c +++ b/src/soc/mediatek/mt8173/i2c.c @@ -14,19 +14,13 @@ */ #include <assert.h> -#include <delay.h> -#include <device/i2c_simple.h> -#include <string.h> -#include <symbols.h> -#include <timer.h> #include <arch/io.h> -#include <soc/addressmap.h> -#include <soc/i2c.h> #include <soc/pll.h> +#include <soc/i2c.h> #define I2C_CLK_HZ (AXI_HZ / 16) -static struct mtk_i2c i2c[7] = { +struct mtk_i2c mtk_i2c_bus_controller[7] = { /* i2c0 setting */ { .i2c_regs = (void *)I2C_BASE, @@ -68,277 +62,21 @@ } }; -#define I2CTAG "[I2C][PL] " - -#if IS_ENABLED(CONFIG_DEBUG_I2C) -#define I2CLOG(fmt, arg...) printk(BIOS_INFO, I2CTAG fmt, ##arg) -#else -#define I2CLOG(fmt, arg...) -#endif /* CONFIG_DEBUG_I2C */ - -#define I2CERR(fmt, arg...) printk(BIOS_ERR, I2CTAG fmt, ##arg) - -static inline void i2c_dma_reset(struct mt8173_i2c_dma_regs *dma_regs) +void mtk_i2c_init(uint8_t bus) { - write32(&dma_regs->dma_rst, 0x1); - udelay(50); - write32(&dma_regs->dma_rst, 0x2); - udelay(50); - write32(&dma_regs->dma_rst, 0x0); - udelay(50); -} - -void mtk_i2c_bus_init(uint8_t bus) -{ - uint8_t sample_div; uint8_t step_div; uint32_t i2c_freq; + const uint8_t sample_div = 1; - assert(bus < ARRAY_SIZE(i2c)); + assert(bus < ARRAY_SIZE(mtk_i2c_bus_controller)); /* Calculate i2c frequency */ - sample_div = 1; step_div = DIV_ROUND_UP(I2C_CLK_HZ, (400 * KHz * sample_div * 2)); i2c_freq = I2C_CLK_HZ / (step_div * sample_div * 2); assert(sample_div < 8 && step_div < 64 && i2c_freq < 400 * KHz && i2c_freq >= 380 * KHz); /* Init i2c bus Timing register */ - write32(&i2c[bus].i2c_regs->timing, (sample_div - 1) << 8 | - (step_div - 1)); -} - -static inline void mtk_i2c_dump_info(uint8_t bus) -{ - struct mt8173_i2c_regs *regs; - - regs = i2c[bus].i2c_regs; - - I2CLOG("I2C register:\nSLAVE_ADDR %x\nINTR_MASK %x\nINTR_STAT %x\n" - "CONTROL %x\nTRANSFER_LEN %x\nTRANSAC_LEN %x\nDELAY_LEN %x\n" - "TIMING %x\nSTART %x\nFIFO_STAT %x\nIO_CONFIG %x\nHS %x\n" - "DEBUGSTAT %x\nEXT_CONF %x\n", - (read32(&regs->salve_addr)), - (read32(&regs->intr_mask)), - (read32(&regs->intr_stat)), - (read32(&regs->control)), - (read32(&regs->transfer_len)), - (read32(&regs->transac_len)), - (read32(&regs->delay_len)), - (read32(&regs->timing)), - (read32(&regs->start)), - (read32(&regs->fifo_stat)), - (read32(&regs->io_config)), - (read32(&regs->hs)), - (read32(&regs->debug_stat)), - (read32(&regs->ext_conf))); - - I2CLOG("addr address %x\n", (uint32_t)regs); -} - -static uint32_t mtk_i2c_transfer(uint8_t bus, struct i2c_msg *seg, - enum i2c_modes read) -{ - uint32_t ret_code = I2C_OK; - uint16_t status; - uint32_t time_out_val = 0; - uint8_t addr; - uint32_t write_len = 0; - uint32_t read_len = 0; - uint8_t *write_buffer = NULL; - uint8_t *read_buffer = NULL; - struct mt8173_i2c_regs *regs; - struct mt8173_i2c_dma_regs *dma_regs; - struct stopwatch sw; - - regs = i2c[bus].i2c_regs; - dma_regs = i2c[bus].i2c_dma_regs; - - addr = seg[0].slave; - - switch (read) { - case I2C_WRITE_MODE: - assert(seg[0].len > 0 && seg[0].len <= 255); - write_len = seg[0].len; - write_buffer = seg[0].buf; - break; - - case I2C_READ_MODE: - assert(seg[0].len > 0 && seg[0].len <= 255); - read_len = seg[0].len; - read_buffer = seg[0].buf; - break; - - /* Must use special write-then-read mode for repeated starts. */ - case I2C_WRITE_READ_MODE: - assert(seg[0].len > 0 && seg[0].len <= 255); - assert(seg[1].len > 0 && seg[1].len <= 255); - write_len = seg[0].len; - read_len = seg[1].len; - write_buffer = seg[0].buf; - read_buffer = seg[1].buf; - break; - } - - /* Clear interrupt status */ - write32(&regs->intr_stat, I2C_TRANSAC_COMP | I2C_ACKERR | - I2C_HS_NACKERR); - - write32(&regs->fifo_addr_clr, 0x1); - - /* Enable interrupt */ - write32(&regs->intr_mask, I2C_HS_NACKERR | I2C_ACKERR | - I2C_TRANSAC_COMP); - - switch (read) { - case I2C_WRITE_MODE: - memcpy(_dma_coherent, write_buffer, write_len); - - /* control registers */ - write32(&regs->control, ACK_ERR_DET_EN | DMA_EN | CLK_EXT | - REPEATED_START_FLAG); - - /* Set transfer and transaction len */ - write32(&regs->transac_len, 1); - write32(&regs->transfer_len, write_len); - - /* set i2c write slave address*/ - write32(&regs->slave_addr, addr << 1); - - /* Prepare buffer data to start transfer */ - write32(&dma_regs->dma_con, I2C_DMA_CON_TX); - write32(&dma_regs->dma_tx_mem_addr, (uintptr_t)_dma_coherent); - write32(&dma_regs->dma_tx_len, write_len); - break; - - case I2C_READ_MODE: - /* control registers */ - write32(&regs->control, ACK_ERR_DET_EN | DMA_EN | CLK_EXT | - REPEATED_START_FLAG); - - /* Set transfer and transaction len */ - write32(&regs->transac_len, 1); - write32(&regs->transfer_len, read_len); - - /* set i2c read slave address*/ - write32(&regs->slave_addr, (addr << 1 | 0x1)); - - /* Prepare buffer data to start transfer */ - write32(&dma_regs->dma_con, I2C_DMA_CON_RX); - write32(&dma_regs->dma_rx_mem_addr, (uintptr_t)_dma_coherent); - write32(&dma_regs->dma_rx_len, read_len); - break; - - case I2C_WRITE_READ_MODE: - memcpy(_dma_coherent, write_buffer, write_len); - - /* control registers */ - write32(&regs->control, DIR_CHG | ACK_ERR_DET_EN | DMA_EN | - CLK_EXT | REPEATED_START_FLAG); - - /* Set transfer and transaction len */ - write32(&regs->transfer_len, write_len); - write32(&regs->transfer_aux_len, read_len); - write32(&regs->transac_len, 2); - - /* set i2c write slave address*/ - write32(&regs->slave_addr, addr << 1); - - /* Prepare buffer data to start transfer */ - write32(&dma_regs->dma_con, I2C_DMA_CLR_FLAG); - write32(&dma_regs->dma_tx_mem_addr, (uintptr_t)_dma_coherent); - write32(&dma_regs->dma_tx_len, write_len); - write32(&dma_regs->dma_rx_mem_addr, (uintptr_t)_dma_coherent); - write32(&dma_regs->dma_rx_len, read_len); - break; - } - - write32(&dma_regs->dma_int_flag, I2C_DMA_CLR_FLAG); - write32(&dma_regs->dma_en, I2C_DMA_START_EN); - - /* start transfer transaction */ - write32(&regs->start, 0x1); - - stopwatch_init_msecs_expire(&sw, 100); - - /* polling mode : see if transaction complete */ - while (1) { - status = read32(&regs->intr_stat); - if (status & I2C_HS_NACKERR) { - ret_code = I2C_TRANSFER_FAIL_HS_NACKERR; - I2CERR("[i2c%d transfer] transaction NACK error\n", - bus); - mtk_i2c_dump_info(bus); - break; - } else if (status & I2C_ACKERR) { - ret_code = I2C_TRANSFER_FAIL_ACKERR; - I2CERR("[i2c%d transfer] transaction ACK error\n", bus); - mtk_i2c_dump_info(bus); - break; - } else if (status & I2C_TRANSAC_COMP) { - ret_code = I2C_OK; - memcpy(read_buffer, _dma_coherent, read_len); - break; - } - - if (stopwatch_expired(&sw)) { - ret_code = I2C_TRANSFER_FAIL_TIMEOUT; - I2CERR("[i2c%d transfer] transaction timeout:%d\n", bus, - time_out_val); - mtk_i2c_dump_info(bus); - break; - } - } - - write32(&regs->intr_stat, I2C_TRANSAC_COMP | I2C_ACKERR | - I2C_HS_NACKERR); - - /* clear bit mask */ - write32(&regs->intr_mask, I2C_HS_NACKERR | I2C_ACKERR | - I2C_TRANSAC_COMP); - - /* reset the i2c controller for next i2c transfer. */ - write32(&regs->softreset, 0x1); - - i2c_dma_reset(dma_regs); - - return ret_code; -} - -static uint8_t mtk_i2c_should_combine(struct i2c_msg *seg, int left_count) -{ - if (left_count >= 2 && - !(seg[0].flags & I2C_M_RD) && - (seg[1].flags & I2C_M_RD) && - seg[0].slave == seg[1].slave) - return 1; - else - return 0; -} - -int platform_i2c_transfer(unsigned bus, struct i2c_msg *segments, - int seg_count) -{ - int ret = 0; - int i; - int read; - - for (i = 0; i < seg_count; i++) { - if (mtk_i2c_should_combine(&segments[i], seg_count - i)) { - read = I2C_WRITE_READ_MODE; - } else { - read = (segments[i].flags & I2C_M_RD) ? - I2C_READ_MODE : I2C_WRITE_MODE; - } - - ret = mtk_i2c_transfer(bus, &segments[i], read); - - if (ret) - break; - - if (read == I2C_WRITE_READ_MODE) - i++; - } - - return ret; + write32(&mtk_i2c_bus_controller[bus].i2c_regs->timing, + (sample_div - 1) << 8 | (step_div - 1)); } diff --git a/src/soc/mediatek/mt8173/include/soc/i2c.h b/src/soc/mediatek/mt8173/include/soc/i2c.h old mode 100644 new mode 100755 index 5f46e9c..f2f9cf2 --- a/src/soc/mediatek/mt8173/include/soc/i2c.h +++ b/src/soc/mediatek/mt8173/include/soc/i2c.h @@ -16,47 +16,10 @@ #ifndef SOC_MEDIATEK_MT8173_I2C_H #define SOC_MEDIATEK_MT8173_I2C_H -#include <stddef.h> - -/* I2C Configuration */ -enum { - I2C_HS_DEFAULT_VALUE = 0x0102, -}; - -enum i2c_modes { - I2C_WRITE_MODE = 0, - I2C_READ_MODE = 1, - I2C_WRITE_READ_MODE = 2, -}; - -enum { - I2C_DMA_CON_TX = 0x0, - I2C_DMA_CON_RX = 0x1, - I2C_DMA_START_EN = 0x1, - I2C_DMA_INT_FLAG_NONE = 0x0, - I2C_DMA_CLR_FLAG = 0x0, - I2C_DMA_FLUSH_FLAG = 0x1, -}; - -/* I2C DMA Registers */ -struct mt8173_i2c_dma_regs { - uint32_t dma_int_flag; - uint32_t dma_int_en; - uint32_t dma_en; - uint32_t dma_rst; - uint32_t reserved1; - uint32_t dma_flush; - uint32_t dma_con; - uint32_t dma_tx_mem_addr; - uint32_t dma_rx_mem_addr; - uint32_t dma_tx_len; - uint32_t dma_rx_len; -}; - -check_member(mt8173_i2c_dma_regs, dma_tx_len, 0x24); +#include <soc/i2c_common.h> /* I2C Register */ -struct mt8173_i2c_regs { +struct mt_i2c_regs { uint32_t data_port; uint32_t slave_addr; uint32_t intr_mask; @@ -85,48 +48,8 @@ uint32_t transfer_aux_len; }; -check_member(mt8173_i2c_regs, debug_stat, 0x64); +check_member(mt_i2c_regs, debug_stat, 0x64); -struct mtk_i2c { - struct mt8173_i2c_regs *i2c_regs; - struct mt8173_i2c_dma_regs *i2c_dma_regs; -}; - -enum { - I2C_TRANS_LEN_MASK = (0xff), - I2C_TRANS_AUX_LEN_MASK = (0x1f << 8), - I2C_CONTROL_MASK = (0x3f << 1) -}; - -/* Register mask */ -enum { - I2C_HS_NACKERR = (1 << 2), - I2C_ACKERR = (1 << 1), - I2C_TRANSAC_COMP = (1 << 0), -}; - -/* i2c control bits */ -enum { - ACK_ERR_DET_EN = (1 << 5), - DIR_CHG = (1 << 4), - CLK_EXT = (1 << 3), - DMA_EN = (1 << 2), - REPEATED_START_FLAG = (1 << 1), - STOP_FLAG = (0 << 1) -}; - -/* I2C Status Code */ - -enum { - I2C_OK = 0x0000, - I2C_SET_SPEED_FAIL_OVER_SPEED = 0xA001, - I2C_TRANSFER_INVALID_LENGTH = 0xA002, - I2C_TRANSFER_FAIL_HS_NACKERR = 0xA003, - I2C_TRANSFER_FAIL_ACKERR = 0xA004, - I2C_TRANSFER_FAIL_TIMEOUT = 0xA005, - I2C_TRANSFER_INVALID_ARGUMENT = 0xA006 -}; - -void mtk_i2c_bus_init(uint8_t bus); +void mtk_i2c_init(uint8_t bus); #endif /* SOC_MEDIATEK_MT8173_I2C_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30975 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I407d5e2a9eb29562b40bb300e39f206a94afe76c Gerrit-Change-Number: 30975 Gerrit-PatchSet: 1 Gerrit-Owner: wang qii <Qii.Wang(a)mediatek.com> Gerrit-MessageType: newchange

7 29

Change in ...coreboot[master]: fu540: add code to initialize flash
by Xiang Wang (Code Review) 02 Aug '19

02 Aug '19

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30466 Change subject: fu540: add code to initialize flash ...................................................................... fu540: add code to initialize flash SiFive's ZSBL has initialized flash, but only 16MB of space is available. I fixed it to use all 32MB. Change-Id: I8cd803369da5526eff90400c15b91bbf6b477c69 Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/mainboard/sifive/hifive-unleashed/Makefile.inc A src/mainboard/sifive/hifive-unleashed/bootblock.c A src/mainboard/sifive/hifive-unleashed/flash.c M src/mainboard/sifive/hifive-unleashed/romstage.c M src/soc/sifive/fu540/Makefile.inc A src/soc/sifive/fu540/include/soc/spi.h A src/soc/sifive/fu540/include/soc/spi_flash.h A src/soc/sifive/fu540/spi.c 8 files changed, 506 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/30466/1 diff --git a/src/mainboard/sifive/hifive-unleashed/Makefile.inc b/src/mainboard/sifive/hifive-unleashed/Makefile.inc index 27ddcba..2dac283 100644 --- a/src/mainboard/sifive/hifive-unleashed/Makefile.inc +++ b/src/mainboard/sifive/hifive-unleashed/Makefile.inc @@ -11,6 +11,10 @@ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. +bootblock-y += flash.c +bootblock-y += bootblock.c + +romstage-y += flash.c romstage-y += romstage.c bootblock-y += memlayout.ld diff --git a/src/mainboard/sifive/hifive-unleashed/bootblock.c b/src/mainboard/sifive/hifive-unleashed/bootblock.c new file mode 100644 index 0000000..777b2aa --- /dev/null +++ b/src/mainboard/sifive/hifive-unleashed/bootblock.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 HardenedLinux + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/addressmap.h> +#include <soc/spi.h> +#include <soc/spi_flash.h> +#include <soc/clock.h> + +extern void flash_init(void); +extern void bootblock_mainboard_init(void); + +void bootblock_mainboard_init(void) +{ + flash_init(); +} diff --git a/src/mainboard/sifive/hifive-unleashed/flash.c b/src/mainboard/sifive/hifive-unleashed/flash.c new file mode 100644 index 0000000..a29ac24 --- /dev/null +++ b/src/mainboard/sifive/hifive-unleashed/flash.c @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 HardenedLinux + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/addressmap.h> +#include <soc/spi.h> +#include <soc/spi_flash.h> +#include <soc/clock.h> + +extern void flash_init(void); + +const static spi_reg_ffmt ffmt= { + .cmd_en = 1, + .addr_len = 4, + .pad_cnt = 8, + .command_proto = SPI_PROTO_S, + .addr_proto = SPI_PROTO_S, + .data_proto = SPI_PROTO_Q, + .command_code = 0x6c +}; + + +void flash_init(void) +{ + initialize_spi_flash_mmap_quad( + (spi_ctrl*)FU540_QSPI0, + clock_get_tlclk_khz(), + ffmt.raw_bits, + 0x66, + 0x99); +} diff --git a/src/mainboard/sifive/hifive-unleashed/romstage.c b/src/mainboard/sifive/hifive-unleashed/romstage.c index 8277141..1675aca 100644 --- a/src/mainboard/sifive/hifive-unleashed/romstage.c +++ b/src/mainboard/sifive/hifive-unleashed/romstage.c @@ -21,6 +21,8 @@ #include <soc/clock.h> #include <soc/sdram.h> +extern void flash_init(void); + void main(void) { console_init(); @@ -39,6 +41,7 @@ if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) uart_init(CONFIG_UART_FOR_CONSOLE); + flash_init(); sdram_init(); cbmem_initialize_empty(); diff --git a/src/soc/sifive/fu540/Makefile.inc b/src/soc/sifive/fu540/Makefile.inc index 4f62f3e..83c7b1c 100644 --- a/src/soc/sifive/fu540/Makefile.inc +++ b/src/soc/sifive/fu540/Makefile.inc @@ -18,6 +18,7 @@ bootblock-y += media.c bootblock-y += bootblock.c bootblock-y += clock.c +bootblock-y += spi.c romstage-y += uart.c romstage-y += clint.c @@ -26,6 +27,7 @@ romstage-y += cbmem.c romstage-y += otp.c romstage-y += clock.c +romstage-y += spi.c ramstage-y += uart.c ramstage-y += clint.c @@ -34,6 +36,7 @@ ramstage-y += cbmem.c ramstage-y += otp.c ramstage-y += clock.c +ramstage-y += spi.c CPPFLAGS_common += -Isrc/soc/sifive/fu540/include diff --git a/src/soc/sifive/fu540/include/soc/spi.h b/src/soc/sifive/fu540/include/soc/spi.h new file mode 100644 index 0000000..c40ae7c --- /dev/null +++ b/src/soc/sifive/fu540/include/soc/spi.h @@ -0,0 +1,266 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 SiFive, Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __SOC_SIFIVE_HIFIVE_U_SPI_H__ +#define __SOC_SIFIVE_HIFIVE_U_SPI_H__ + +#include <stdint.h> + +#define _ASSERT_SIZEOF(type, size) _Static_assert(sizeof(type) == (size), #type " must be " #size " bytes wide") + +typedef union +{ + struct + { + uint32_t pha : 1; + uint32_t pol : 1; + uint32_t reserved : 30; + }; + uint32_t raw_bits; +} spi_reg_sckmode; +_ASSERT_SIZEOF(spi_reg_sckmode, 4); + + +typedef union +{ + struct + { + uint32_t mode : 2; + uint32_t reserved : 30; + }; + uint32_t raw_bits; +} spi_reg_csmode; +_ASSERT_SIZEOF(spi_reg_csmode, 4); + + +typedef union +{ + struct + { + uint32_t cssck : 8; + uint32_t reserved0 : 8; + uint32_t sckcs : 8; + uint32_t reserved1 : 8; + }; + uint32_t raw_bits; +} spi_reg_delay0; +_ASSERT_SIZEOF(spi_reg_delay0, 4); + + +typedef union +{ + struct + { + uint32_t intercs : 8; + uint32_t reserved0 : 8; + uint32_t interxfr : 8; + uint32_t reserved1 : 8; + }; + uint32_t raw_bits; +} spi_reg_delay1; +_ASSERT_SIZEOF(spi_reg_delay1, 4); + + +typedef union +{ + struct + { + uint32_t proto : 2; + uint32_t endian : 1; + uint32_t dir : 1; + uint32_t reserved0 : 12; + uint32_t len : 4; + uint32_t reserved1 : 12; + }; + uint32_t raw_bits; +} spi_reg_fmt; +_ASSERT_SIZEOF(spi_reg_fmt, 4); + + +typedef union +{ + struct + { + uint32_t data : 8; + uint32_t reserved : 23; + uint32_t full : 1; + }; + uint32_t raw_bits; +} spi_reg_txdata; +_ASSERT_SIZEOF(spi_reg_txdata, 4); + + +typedef union +{ + struct + { + uint32_t data : 8; + uint32_t reserved : 23; + uint32_t empty : 1; + }; + uint32_t raw_bits; +} spi_reg_rxdata; +_ASSERT_SIZEOF(spi_reg_rxdata, 4); + + +typedef union +{ + struct + { + uint32_t txmark : 3; + uint32_t reserved : 29; + }; + uint32_t raw_bits; +} spi_reg_txmark; +_ASSERT_SIZEOF(spi_reg_txmark, 4); + + +typedef union +{ + struct + { + uint32_t rxmark : 3; + uint32_t reserved : 29; + }; + uint32_t raw_bits; +} spi_reg_rxmark; +_ASSERT_SIZEOF(spi_reg_rxmark, 4); + + +typedef union +{ + struct + { + uint32_t en : 1; + uint32_t reserved : 31; + }; + uint32_t raw_bits; +} spi_reg_fctrl; +_ASSERT_SIZEOF(spi_reg_fctrl, 4); + + +typedef union +{ + struct + { + uint32_t cmd_en : 1; + uint32_t addr_len : 3; + uint32_t pad_cnt : 4; + uint32_t command_proto : 2; + uint32_t addr_proto : 2; + uint32_t data_proto : 2; + uint32_t reserved : 2; + uint32_t command_code : 8; + uint32_t pad_code : 8; + }; + uint32_t raw_bits; +} spi_reg_ffmt; +_ASSERT_SIZEOF(spi_reg_ffmt, 4); + + +typedef union +{ + struct + { + uint32_t txwm : 1; + uint32_t rxwm : 1; + uint32_t reserved : 30; + }; + uint32_t raw_bits; +} spi_reg_ie; +typedef spi_reg_ie spi_reg_ip; +_ASSERT_SIZEOF(spi_reg_ie, 4); +_ASSERT_SIZEOF(spi_reg_ip, 4); + +#undef _ASSERT_SIZEOF + + +/** + * SPI control register memory map. + * + * All functions take a pointer to a SPI device's control registers. + */ +typedef volatile struct +{ + uint32_t sckdiv; + spi_reg_sckmode sckmode; + uint32_t reserved08; + uint32_t reserved0c; + + uint32_t csid; + uint32_t csdef; + spi_reg_csmode csmode; + uint32_t reserved1c; + + uint32_t reserved20; + uint32_t reserved24; + spi_reg_delay0 delay0; + spi_reg_delay1 delay1; + + uint32_t reserved30; + uint32_t reserved34; + uint32_t reserved38; + uint32_t reserved3c; + + spi_reg_fmt fmt; + uint32_t reserved44; + spi_reg_txdata txdata; + spi_reg_rxdata rxdata; + + spi_reg_txmark txmark; + spi_reg_rxmark rxmark; + uint32_t reserved58; + uint32_t reserved5c; + + spi_reg_fctrl fctrl; + spi_reg_ffmt ffmt; + uint32_t reserved68; + uint32_t reserved6c; + + spi_reg_ie ie; + spi_reg_ip ip; +} spi_ctrl; + + +void spi_tx(spi_ctrl* spictrl, uint8_t in); +uint8_t spi_rx(spi_ctrl* spictrl); +uint8_t spi_txrx(spi_ctrl* spictrl, uint8_t in); + +// Inlining header functions in C +// https://stackoverflow.com/a/23699777/7433423 + +/** + * Get smallest clock divisor that divides input_khz to a quotient less than or + * equal to max_target_khz; + */ +static inline unsigned int spi_min_clk_divisor(unsigned int input_khz, unsigned int max_target_khz) +{ + // f_sck = f_in / (2 * (div + 1)) => div = (f_in / (2*f_sck)) - 1 + // + // The nearest integer solution for div requires rounding up as to not exceed + // max_target_khz. + // + // div = ceil(f_in / (2*f_sck)) - 1 + // = floor((f_in - 1 + 2*f_sck) / (2*f_sck)) - 1 + // + // This should not overflow as long as (f_in - 1 + 2*f_sck) does not exceed + // 2^32 - 1, which is unlikely since we represent frequencies in kHz. + unsigned int quotient = (input_khz + 2 * max_target_khz - 1) / (2 * max_target_khz); + // Avoid underflow + if (quotient == 0) + return 0; + return quotient - 1; +} + +#endif /* __SOC_SIFIVE_HIFIVE_U_SPI_H__ */ diff --git a/src/soc/sifive/fu540/include/soc/spi_flash.h b/src/soc/sifive/fu540/include/soc/spi_flash.h new file mode 100644 index 0000000..9926b82 --- /dev/null +++ b/src/soc/sifive/fu540/include/soc/spi_flash.h @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 SiFive, Inc + * Copyright (C) 2018 HardenedLinux + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_SIFIVE_HIFIVE_U_SPI_FLASH_H__ +#define __SOC_SIFIVE_HIFIVE_U_SPI_FLASH_H__ + +#include <soc/spi.h> +#include <stdint.h> + +#define SPI_PROTO_S 0 +#define SPI_PROTO_D 1 +#define SPI_PROTO_Q 2 + +/** + * Set up SPI for direct, non-memory-mapped access. + */ + +static inline int initialize_spi_flash_direct( + spi_ctrl* spictrl, + unsigned int spi_clk_input_khz, + unsigned int command_enable, + unsigned int command_reset) +{ + // Max desired SPI clock is 10MHz + spictrl->sckdiv = spi_min_clk_divisor(spi_clk_input_khz, 10000); + + spictrl->fctrl.en = 0; + + spi_txrx(spictrl, command_enable); + spi_txrx(spictrl, command_reset); + + return 0; +} + +static inline int _initialize_spi_flash_mmap( + spi_ctrl* spictrl, + unsigned int spi_clk_input_khz, + uint32_t ffmt_rawbits, + unsigned int command_enable, + unsigned int command_reset) +{ + // Max desired SPI clock is 10MHz + spictrl->sckdiv = spi_min_clk_divisor(spi_clk_input_khz, 10000); + + spictrl->fctrl.en = 0; + + spi_txrx(spictrl, command_enable); + spi_txrx(spictrl, command_reset); + + spictrl->ffmt.raw_bits = ffmt_rawbits; + + spictrl->fctrl.en = 1; + __asm__ __volatile__ ("fence io, io"); + return 0; +} + + +static inline int initialize_spi_flash_mmap_single( + spi_ctrl* spictrl, + unsigned int spi_clk_input_khz, + uint32_t ffmt_rawbits, + unsigned int command_enable, + unsigned int command_reset) +{ + return _initialize_spi_flash_mmap( + spictrl, + spi_clk_input_khz, + ffmt_rawbits, + command_enable, + command_reset); +} + + +static inline int initialize_spi_flash_mmap_quad( + spi_ctrl* spictrl, + unsigned int spi_clk_input_khz, + uint32_t ffmt_rawbits, + unsigned int command_enable, + unsigned int command_reset) +{ + return _initialize_spi_flash_mmap( + spictrl, + spi_clk_input_khz, + ffmt_rawbits, + command_enable, + command_reset); +} + +#endif /* __SOC_SIFIVE_HIFIVE_U_SPI_FLASH_H__ */ + diff --git a/src/soc/sifive/fu540/spi.c b/src/soc/sifive/fu540/spi.c new file mode 100644 index 0000000..01a58dd --- /dev/null +++ b/src/soc/sifive/fu540/spi.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 SiFive, Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/spi.h> + +/** + * Wait until SPI is ready for transmission and transmit byte. + */ +void spi_tx(spi_ctrl* spictrl, uint8_t in) +{ +#if __riscv_atomic + int32_t r; + do { + asm volatile ( + "amoor.w %0, %2, %1\n" + : "=r" (r), "+A" (spictrl->txdata.raw_bits) + : "r" (in) + ); + } while (r < 0); +#else + while ((int32_t) spictrl->txdata.raw_bits < 0); + spictrl->txdata.data = in; +#endif +} + + +/** + * Wait until SPI receive queue has data and read byte. + */ +uint8_t spi_rx(spi_ctrl* spictrl) +{ + int32_t out; + while ((out = (int32_t) spictrl->rxdata.raw_bits) < 0); + return (uint8_t) out; +} + + +/** + * Transmit a byte and receive a byte. + */ +uint8_t spi_txrx(spi_ctrl* spictrl, uint8_t in) +{ + spi_tx(spictrl, in); + return spi_rx(spictrl); +} + -- To view, visit https://review.coreboot.org/c/coreboot/+/30466 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8cd803369da5526eff90400c15b91bbf6b477c69 Gerrit-Change-Number: 30466 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-MessageType: newchange

6 50

Change in ...coreboot[master]: security/tpm/tss/tcg-2.0: Add function to return TMP2 capabilities.
by Frans Hendriks (Code Review) 19 Jul '19

19 Jul '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30826 Change subject: security/tpm/tss/tcg-2.0: Add function to return TMP2 capabilities. ...................................................................... security/tpm/tss/tcg-2.0: Add function to return TMP2 capabilities. Add function tlcl_getcapability() to return capability, used by measured boot. In function unmarshal_get_capability handling of TPM_CAP_PCRS has been added for TPM2 get capability commands. BUG=N/A TEST=Build binary and verified logging on Facebook FBG-1701 Change-Id: I85e1bd2822aa6e7fd95ff2b9faa25cf183e6de37 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/security/tpm/tss.h M src/security/tpm/tss/tcg-2.0/tss.c M src/security/tpm/tss/tcg-2.0/tss_marshaling.c M src/security/tpm/tss/tcg-2.0/tss_structures.h 4 files changed, 302 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/30826/1 diff --git a/src/security/tpm/tss.h b/src/security/tpm/tss.h index c4f2608..610a99c 100644 --- a/src/security/tpm/tss.h +++ b/src/security/tpm/tss.h @@ -1,4 +1,5 @@ /* Copyright (c) 2013 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2018 Eltan B.V. * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -122,6 +123,35 @@ uint32_t tlcl_continue_self_test(void); /** + * Issue tpm get capability command + */ +uint32_t tlcl_getcapability(TPM_CAP capability, uint32_t property, + uint32_t propertyCount, TPMI_YES_NO *moreData, + TPMS_CAPABILITY_DATA *capabilityData); + +/** + * Issue more flexible process command + */ +void *tpm_process_command_ex(TPM_CC command, void *command_body, + size_t command_size, size_t *response_size, + bool marshal); + +/* + * tlcl_extend command that allows more digests to be passed in at the same + * time + */ +uint32_t tlcl_extend_ex(int pcr_num, const TPML_DIGEST_VALUES *in_digests); + +/** + * Return size of digest. + * + * @param[in] HashAlgo Hash algorithm + * + * @return size of digest + */ +uint16_t tlcl_get_hash_size_from_algo(TPMI_ALG_HASH hashAlgo); + +/** * Write [length] bytes of [data] to space at [index]. The TPM error code is * returned. */ @@ -144,7 +174,7 @@ uint32_t tlcl_physical_presence_cmd_enable(void); /** - * Finalize the physical presence settings: sofware PP is enabled, hardware PP + * Finalize the physical presence settings: software PP is enabled, hardware PP * is disabled, and the lifetime lock is set. The TPM error code is returned. */ uint32_t tlcl_finalize_physical_presence(void); diff --git a/src/security/tpm/tss/tcg-2.0/tss.c b/src/security/tpm/tss/tcg-2.0/tss.c index e579bff..87f38e1 100644 --- a/src/security/tpm/tss/tcg-2.0/tss.c +++ b/src/security/tpm/tss/tcg-2.0/tss.c @@ -1,5 +1,6 @@ /* * Copyright 2016 The Chromium OS Authors. All rights reserved. + * Copyright 2017-2018 Eltan B.V. * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -15,6 +16,12 @@ #include "tss_structures.h" #include "tss_marshaling.h" +static INTERNAL_HASH_INFO mHashInfo[] = { + {TPM_ALG_ERROR, 1}, + {TPM_ALG_SHA1, SHA1_DIGEST_SIZE}, + {TPM_ALG_SHA256, SHA256_DIGEST_SIZE}, +}; + /* * This file provides interface between firmware and TPM2 device. The TPM1.2 * API was copied as is and relevant functions modified to comply with the @@ -53,6 +60,48 @@ return tpm_unmarshal_response(command, &ib); } +void *tpm_process_command_ex(TPM_CC command, void *command_body, + size_t command_size, size_t *response_size, bool marshal) +{ + struct obuf ob; + struct ibuf ib; + size_t out_size; + size_t in_size; + const uint8_t *sendb; + /* Command/response buffer. */ + static uint8_t cr_buffer[TPM_BUFFER_SIZE] CAR_GLOBAL; + + uint8_t *cr_buffer_ptr = car_get_var_ptr(cr_buffer); + + if (marshal) { + obuf_init(&ob, cr_buffer_ptr, sizeof(cr_buffer)); + if (tpm_marshal_command(command, command_body, &ob) < 0) { + printk(BIOS_ERR, "command %#x\n", command); + return NULL; + } + sendb = obuf_contents(&ob, &out_size); + } else { + sendb = command_body; + out_size = command_size; + } + + in_size = sizeof(cr_buffer); + if (tis_sendrecv(sendb, out_size, cr_buffer_ptr, &in_size)) { + printk(BIOS_ERR, "tpm transaction failed\n"); + return NULL; + } + + ibuf_init(&ib, cr_buffer_ptr, in_size); + + if (response_size) + *response_size = in_size; + + if (marshal) + return tpm_unmarshal_response(command, &ib); + else + return cr_buffer_ptr; +} + static uint32_t tlcl_send_startup(TPM_SU type) { struct tpm2_startup startup; @@ -139,7 +188,7 @@ pcr_ext_cmd.digests.count = 1; pcr_ext_cmd.digests.digests[0].hashAlg = TPM_ALG_SHA256; memcpy(pcr_ext_cmd.digests.digests[0].digest.sha256, in_digest, - sizeof(pcr_ext_cmd.digests.digests[0].digest.sha256)); + sizeof(TPMU_HA)); response = tpm_process_command(TPM2_PCR_Extend, &pcr_ext_cmd); @@ -151,6 +200,65 @@ return TPM_SUCCESS; } +/* + * Handle multiple digests (SHA1 and SHA256 at the moment) + */ +uint32_t tlcl_extend_ex(int pcr_num, const TPML_DIGEST_VALUES *in_digests) +{ + struct tpm2_pcr_extend_cmd pcr_ext_cmd; + struct tpm2_response *response; + int i; + + pcr_ext_cmd.pcrHandle = HR_PCR + pcr_num; + pcr_ext_cmd.digests.count = in_digests->count; + + printk(BIOS_SPEW, "%s: pcr = %d\n", __func__, pcr_num); + printk(BIOS_SPEW, "%s: in_digests->count = %d\n", __func__, + in_digests->count); + + for (i = 0; i < in_digests->count ; i++) { + pcr_ext_cmd.digests.digests[i].hashAlg = + in_digests->digests[i].hashAlg; + memcpy((void *) pcr_ext_cmd.digests.digests[i].digest.sha256, + (void *) in_digests->digests[i].digest.sha256, + sizeof(TPMU_HA)); + + printk(BIOS_SPEW, "%s: in_digests[%d]->hash_alg = 0x%x\n", + __func__, i, in_digests->digests[i].hashAlg); + } + + response = tpm_process_command(TPM2_PCR_Extend, &pcr_ext_cmd); + + /* + * Check if we are invalidating the pcrs, ignore the error if this is + * the case + */ + if (in_digests->count == 1) { + if (in_digests->digests[0].hashAlg == TPM_ALG_ERROR) { + if (in_digests->digests[0].digest.invalidate_pcrs == + 1) { + if (response) { + if ((response->hdr.tpm_code & + ~TPM_RC_N_MASK) == (TPM_RC_P | + TPM_RC_HASH)){ + printk(BIOS_SPEW, "%s:" + " TPM_RC_HASH returned this is" + " expected\n", __func__); + return TPM_SUCCESS; + } + } + } + } + } + + printk(BIOS_INFO, "%s: response is 0x%x\n", + __func__, response ? response->hdr.tpm_code : -1); + if (!response || response->hdr.tpm_code) + return TPM_E_IOERROR; + + return TPM_SUCCESS; +} + uint32_t tlcl_finalize_physical_presence(void) { /* Nothing needs to be done with tpm2. */ @@ -178,13 +286,22 @@ uint32_t tlcl_lib_init(void) { uint8_t done = car_get_var(tlcl_init_done); + + printk(BIOS_SPEW, "%s: tlcl_init_done is %d\n", __func__, done); if (done) return VB2_SUCCESS; - if (tis_init()) + printk(BIOS_SPEW, "%s: calling tis_init\n", __func__); + if (tis_init()) { + printk(BIOS_ERR, "%s: tis_init returned error\n", __func__); return VB2_ERROR_UNKNOWN; - if (tis_open()) + } + + printk(BIOS_SPEW, "%s: calling tis_open\n", __func__); + if (tis_open()) { + printk(BIOS_ERR, "%s: tis_open returned error\n", __func__); return VB2_ERROR_UNKNOWN; + } car_set_var(tlcl_init_done, 1); @@ -361,3 +478,61 @@ return TPM_SUCCESS; } + +/* + * Issue the tpm2 get capability command + * + * Please note that the capabilityData is not unmarshalled. + */ +uint32_t tlcl_getcapability(TPM_CAP capability, uint32_t property, + uint32_t propertyCount, TPMI_YES_NO *moreData, + TPMS_CAPABILITY_DATA *capabilityData) +{ + struct tpm2_get_capability cmd; + struct tpm2_response *response; + size_t response_size; + + cmd.capability = capability; + cmd.property = property; + cmd.propertyCount = propertyCount; + + if (propertyCount > 1) { + printk(BIOS_ERR, "%s: PropertyCount more than one not supported" + " yet\n", __func__); + } + + response = tpm_process_command_ex(TPM2_GetCapability, &cmd, 0, + &response_size, 1); + + if (!response) { + printk(BIOS_ERR, "%s: Command Failed\n", __func__); + return TPM_E_IOERROR; + } + + if (moreData) + *moreData = response->gc.more_data; + memcpy(capabilityData, &response->gc.cd, response_size - + sizeof(TPMI_YES_NO) - sizeof(struct tpm_header)); + return TPM_SUCCESS; +} + +/** + Return size of digest. + + @param[in] HashAlgo Hash algorithm + + @return size of digest +**/ + +uint16_t tlcl_get_hash_size_from_algo(TPMI_ALG_HASH hashAlgo) +{ + uint16_t index; + + for (index = 0; index < ARRAY_SIZE(mHashInfo); index++) + if (mHashInfo[index].hashAlgo == hashAlgo) + return mHashInfo[index].hashSize; + + printk(BIOS_SPEW, "%s: unknown hash algorithm %d\n", __func__, + hashAlgo); + return 0; +} diff --git a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c index 49ac5e8..b4518d20 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c +++ b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c @@ -1,5 +1,6 @@ /* * Copyright 2016 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2018 Eltan B.V. * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -12,6 +13,7 @@ #include "tss_marshaling.h" #include <security/tpm/tss/vendor/cr50/cr50.h> +#include <security/tpm/tss.h> static uint16_t tpm_tag CAR_GLOBAL; /* Depends on the command type. */ @@ -82,7 +84,7 @@ rc |= marshal_TPMI_ALG_HASH(ob, tpmtha->hashAlg); rc |= obuf_write(ob, tpmtha->digest.sha256, - sizeof(tpmtha->digest.sha256)); + tlcl_get_hash_size_from_algo(tpmtha->hashAlg)); return rc; } @@ -398,6 +400,22 @@ rc |= ibuf_read_be32(ib, &pp->value); } break; + case TPM_CAP_PCRS: + if (ibuf_read_be32(ib, &gcr->cd.data.assignedPCR.count)) + return -1; + if (gcr->cd.data.assignedPCR.count > ARRAY_SIZE + (gcr->cd.data.assignedPCR.pcrSelections)) { + printk(BIOS_INFO, "%s:%s:%d - %d - too many properties\n", + __FILE__, __func__, __LINE__, + gcr->cd.data.assignedPCR.count); + return -1; + } + for (i = 0; i < gcr->cd.data.assignedPCR.count; i++) { + TPMS_PCR_SELECTION *pp = + gcr->cd.data.assignedPCR.pcrSelections + i; + rc |= ibuf_read(ib, pp, sizeof(TPMS_PCR_SELECTION)); + } + break; default: printk(BIOS_ERR, "%s:%d - unable to unmarshal capability response", @@ -448,12 +466,12 @@ } /* - * Let's ignore the authorisation section. It should be 5 bytes total, + * Let's ignore the authorization section. It should be 5 bytes total, * just confirm that this is the case and report any discrepancy. */ if (ibuf_remaining(ib) != 5) printk(BIOS_ERR, - "%s:%d - unexpected authorisation seciton size %zd\n", + "%s:%d - unexpected authorization section size %zd\n", __func__, __LINE__, ibuf_remaining(ib)); ibuf_oob_drain(ib, ibuf_remaining(ib)); diff --git a/src/security/tpm/tss/tcg-2.0/tss_structures.h b/src/security/tpm/tss/tcg-2.0/tss_structures.h index 2bac633..e70ae02 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_structures.h +++ b/src/security/tpm/tss/tcg-2.0/tss_structures.h @@ -1,5 +1,6 @@ /* * Copyright 2016 The Chromium OS Authors. All rights reserved. + * Copyright 2017-2018 Eltan B.V. * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -22,6 +23,12 @@ #define TPM2_RC_SUCCESS 0 #define TPM2_RC_NV_DEFINED 0x14c +// +// We set this to two here as we only support SHA1 and SHA256 right now. +// Should be updated when additional algorithms are supported +// +#define HASH_COUNT 2 + /* Basic TPM2 types. */ typedef uint16_t TPM_SU; typedef uint16_t TPM_ALG_ID; @@ -36,12 +43,28 @@ typedef TPM_HANDLE TPM_RH; /* Some hardcoded algorithm values. */ -#define TPM_ALG_HMAC ((TPM_ALG_ID)0x0005) -#define TPM_ALG_NULL ((TPM_ALG_ID)0x0010) -#define TPM_ALG_SHA1 ((TPM_ALG_ID)0x0004) -#define TPM_ALG_SHA256 ((TPM_ALG_ID)0x000b) +// Table 7 - TPM_ALG_ID Constants +#define TPM_ALG_ERROR ((TPM_ALG_ID)0x0000) +#define TPM_ALG_HMAC ((TPM_ALG_ID)0x0005) +#define TPM_ALG_NULL ((TPM_ALG_ID)0x0010) +#define TPM_ALG_SHA1 ((TPM_ALG_ID)0x0004) +#define TPM_ALG_SHA256 ((TPM_ALG_ID)0x000b) +#define TPM_ALG_SHA384 ((TPM_ALG_ID)0x000C) +#define TPM_ALG_SHA512 ((TPM_ALG_ID)0x000D) +#define TPM_ALG_SM3_256 ((TPM_ALG_ID)0x0012) +// Annex A Algorithm Constants + +// Table 205 - Defines for SHA1 Hash Values +#define SHA1_DIGEST_SIZE 20 +// Table 206 - Defines for SHA256 Hash Values #define SHA256_DIGEST_SIZE 32 +// Table 207 - Defines for SHA384 Hash Values +//#define SHA384_DIGEST_SIZE 48 +// Table 208 - Defines for SHA512 Hash Values +#define SHA512_DIGEST_SIZE 64 +// Table 209 - Defines for SM3_256 Hash Values +//#define SM3_256_DIGEST_SIZE 32 /* Some hardcoded hierarchies. */ #define TPM_RH_NULL 0x40000007 @@ -79,6 +102,12 @@ space is defined by the lower 16 bits. */ #define TPM_CC_VENDOR_BIT_MASK 0x20000000 +// Table 15 - TPM_RC Constants (Actions) +#define RC_FMT1 (TPM_RC)(0x080) +#define TPM_RC_HASH (TPM_RC)(RC_FMT1 + 0x003) +#define TPM_RC_P (TPM_RC)(0x040) +#define TPM_RC_N_MASK (TPM_RC)(0xF00) + /* Startup values. */ #define TPM_SU_CLEAR 0 #define TPM_SU_STATE 1 @@ -144,7 +173,9 @@ }; /* Various TPM capability types to use when querying the device. */ +// Table 21 - TPM_CAP Constants typedef uint32_t TPM_CAP; +#define TPM_CAP_PCRS ((TPM_CAP)0x00000005) #define TPM_CAP_TPM_PROPERTIES ((TPM_CAP)0x00000006) typedef TPM_HANDLE TPMI_RH_NV_AUTH; @@ -224,16 +255,37 @@ sizeof(TPMI_YES_NO) - sizeof(TPM_CAP) - sizeof(uint32_t)) #define MAX_TPM_PROPERTIES (MAX_CAP_DATA/sizeof(TPMS_TAGGED_PROPERTY)) +#define IMPLEMENTATION_PCR 24 +#define PLATFORM_PCR 24 + +#define PCR_SELECT_MIN ((PLATFORM_PCR + 7) / 8) +#define PCR_SELECT_MAX ((IMPLEMENTATION_PCR + 7) / 8) + /* Somewhat arbitrary, leave enough room for command wrappers. */ #define MAX_NV_BUFFER_SIZE (TPM_BUFFER_SIZE - sizeof(struct tpm_header) - 50) +// Table 81 - TPMS_PCR_SELECTION Structure typedef struct { - uint32_t count; - TPMS_TAGGED_PROPERTY tpmProperty[MAX_TPM_PROPERTIES]; + TPMI_ALG_HASH hash; + uint8_t sizeofSelect; + uint8_t pcrSelect[PCR_SELECT_MAX]; +} __packed TPMS_PCR_SELECTION; + +// Table 98 - TPML_PCR_SELECTION Structure +typedef struct { + uint32_t count; + TPMS_PCR_SELECTION pcrSelections[HASH_COUNT]; +} __packed TPML_PCR_SELECTION; + +// Table 100 - TPML_TAGGED_TPM_PROPERTY Structure +typedef struct { + uint32_t count; + TPMS_TAGGED_PROPERTY tpmProperty[MAX_TPM_PROPERTIES]; } TPML_TAGGED_TPM_PROPERTY; typedef union { - TPML_TAGGED_TPM_PROPERTY tpmProperties; + TPML_TAGGED_TPM_PROPERTY tpmProperties; + TPML_PCR_SELECTION assignedPCR; } TPMU_CAPABILITIES; typedef struct { @@ -271,22 +323,30 @@ } TPM2B_MAX_NV_BUFFER; /* - * This is a union, but as of now we support just one digest - sha256, so - * there is just one element. + * This is a union, but as of now we support just sha1 and sha256 */ +// Table 66 - TPMU_HA Union typedef union { - uint8_t sha256[SHA256_DIGEST_SIZE]; + uint8_t invalidate_pcrs; + uint8_t sha1[SHA1_DIGEST_SIZE]; + uint8_t sha256[SHA256_DIGEST_SIZE]; } TPMU_HA; typedef struct { + TPMI_ALG_HASH hashAlgo; + uint16_t hashSize; +} INTERNAL_HASH_INFO; + +typedef struct { TPMI_ALG_HASH hashAlg; TPMU_HA digest; } TPMT_HA; +// Table 96 -- TPML_DIGEST_VALUES Structure <I/O> typedef struct { uint32_t count; - TPMT_HA digests[1]; /* Limit max number of hashes to 1. */ -} TPML_DIGEST_VALUES; + TPMT_HA digests[HASH_COUNT]; +} __packed TPML_DIGEST_VALUES; struct nv_read_response { uint32_t params_size; -- To view, visit https://review.coreboot.org/c/coreboot/+/30826 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85e1bd2822aa6e7fd95ff2b9faa25cf183e6de37 Gerrit-Change-Number: 30826 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

6 47

Change in ...coreboot[master]: vendorcode/eltan Add hashing library used for measured and verified b...
by Frans Hendriks (Code Review) 10 Jul '19

10 Jul '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30831 Change subject: vendorcode/eltan Add hashing library used for measured and verified boot. ...................................................................... vendorcode/eltan Add hashing library used for measured and verified boot. To avoid having the whole 3rdparty/vboot/firmware included a small hashing library has been created. Create library which is a 'wrapper' using only sha1, sha256 and sha512 of 3rdparty/vboot/firmware. Fucntions cb_sha1(), cb_sha256() and cb_sha512 can be used for hashing. BUG=N/A TEST=Created binary and verify logging on Facebok FBG-1701 Change-Id: If828bde54c79e836a5b05ff0447645d7e06e819a Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- A src/vendorcode/eltan/security/include/cb_sha1.h A src/vendorcode/eltan/security/include/cb_sha256.h A src/vendorcode/eltan/security/include/cb_sha512.h A src/vendorcode/eltan/security/include/cryptolib.h A src/vendorcode/eltan/security/lib/Makefile.inc A src/vendorcode/eltan/security/lib/cb_sha1.c A src/vendorcode/eltan/security/lib/cb_sha256.c A src/vendorcode/eltan/security/lib/cb_sha512.c 8 files changed, 297 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/30831/1 diff --git a/src/vendorcode/eltan/security/include/cb_sha1.h b/src/vendorcode/eltan/security/include/cb_sha1.h new file mode 100644 index 0000000..3b72355 --- /dev/null +++ b/src/vendorcode/eltan/security/include/cb_sha1.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018. Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SECURITY_SHA1_H__ +#define __SECURITY_SHA1_H__ + +uint8_t *cb_sha1(const uint8_t *data, uint64_t len, uint8_t *digest); + +#endif diff --git a/src/vendorcode/eltan/security/include/cb_sha256.h b/src/vendorcode/eltan/security/include/cb_sha256.h new file mode 100644 index 0000000..3b45f73 --- /dev/null +++ b/src/vendorcode/eltan/security/include/cb_sha256.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018. Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SECURITY_SHA256_H__ +#define __SECURITY_SHA256_H__ + +uint8_t *cb_sha256(const uint8_t *data, uint64_t len, uint8_t *digest); +uint8_t *cb_sha256_ex(const uint8_t *data, uint64_t len, uint8_t *digest, + bool endian); + +#endif diff --git a/src/vendorcode/eltan/security/include/cb_sha512.h b/src/vendorcode/eltan/security/include/cb_sha512.h new file mode 100644 index 0000000..a383cf0 --- /dev/null +++ b/src/vendorcode/eltan/security/include/cb_sha512.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018. Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SECURITY_SHA512_H__ +#define __SECURITY_SHA512_H__ + +uint8_t *cb_sha512(const uint8_t *data, uint64_t len, uint8_t *digest); +uint8_t *cb_sha512_ex(const uint8_t *data, uint64_t len, uint8_t *digest, + bool endian); + +#endif diff --git a/src/vendorcode/eltan/security/include/cryptolib.h b/src/vendorcode/eltan/security/include/cryptolib.h new file mode 100644 index 0000000..ac1668a --- /dev/null +++ b/src/vendorcode/eltan/security/include/cryptolib.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018. Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SECURITY_CRYPTOLIB_H__ +#define __SECURITY_CRYPTOLIB_H__ + +#define NEED_VB2_SHA_LIBRARY + +#include <2rsa.h> +#include <vb21_common.h> +#include <vb2_api.h> + +#include "cb_sha1.h" +#include "cb_sha512.h" +#include "cb_sha256.h" + +#endif \ No newline at end of file diff --git a/src/vendorcode/eltan/security/lib/Makefile.inc b/src/vendorcode/eltan/security/lib/Makefile.inc new file mode 100644 index 0000000..9e2fc39 --- /dev/null +++ b/src/vendorcode/eltan/security/lib/Makefile.inc @@ -0,0 +1,52 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2018 Eltan B.V. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +SECURITYLIB_INCLUDES = -I3rdparty/vboot/firmware/2lib/include -I3rdparty/vboot/firmware/lib21/include + +CPPFLAGS_common+=$(SECURITYLIB_INCLUDES) + +ifeq ($(CONFIG_VERIFIED_BOOT),y) +bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += $(top)/3rdparty/vboot/firmware/2lib/2common.c +bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += $(top)/3rdparty/vboot/firmware/2lib/2rsa.c +bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += $(top)/3rdparty/vboot/firmware/2lib/2sha_utility.c +bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += $(top)/3rdparty/vboot/firmware/lib21/packed_key.c +ifeq ($(CONFIG_VERIFIED_BOOT_USE_SHA512),y) +bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += cb_sha512.c +bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += $(top)/3rdparty/vboot/firmware/2lib/2sha512.c +else +bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += cb_sha256.c +bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += $(top)/3rdparty/vboot/firmware/2lib/2sha256.c +endif +endif + +ifeq ($(CONFIG_MBOOT),y) +ramstage-y += $(top)/3rdparty/vboot/firmware/2lib/2sha1.c +ramstage-y += $(top)/3rdparty/vboot/firmware/2lib/2sha512.c +ramstage-y += $(top)/3rdparty/vboot/firmware/2lib/2sha256.c +ramstage-y += cb_sha1.c +ramstage-y += cb_sha512.c +ramstage-y += cb_sha256.c + +romstage-y += $(top)/3rdparty/vboot/firmware/2lib/2common.c +romstage-y += $(top)/3rdparty/vboot/firmware/2lib/2rsa.c +romstage-y += $(top)/3rdparty/vboot/firmware/2lib/2sha1.c +romstage-y += $(top)/3rdparty/vboot/firmware/2lib/2sha256.c +romstage-y += $(top)/3rdparty/vboot/firmware/2lib/2sha512.c +romstage-y += $(top)/3rdparty/vboot/firmware/2lib/2sha_utility.c +romstage-y += $(top)/3rdparty/vboot/firmware/lib21/packed_key.c +romstage-y += cb_sha1.c +romstage-y += cb_sha512.c +romstage-y += cb_sha256.c +endif \ No newline at end of file diff --git a/src/vendorcode/eltan/security/lib/cb_sha1.c b/src/vendorcode/eltan/security/lib/cb_sha1.c new file mode 100644 index 0000000..fd96943 --- /dev/null +++ b/src/vendorcode/eltan/security/lib/cb_sha1.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cryptolib.h> + +uint8_t *cb_sha1(const uint8_t *data, uint64_t len, uint8_t *digest) +{ + struct vb2_sha1_context ctx; + + vb2_sha1_init(&ctx); + vb2_sha1_update(&ctx, data, len); + vb2_sha1_finalize(&ctx, digest); + + return digest; +} diff --git a/src/vendorcode/eltan/security/lib/cb_sha256.c b/src/vendorcode/eltan/security/lib/cb_sha256.c new file mode 100644 index 0000000..b02ebb2 --- /dev/null +++ b/src/vendorcode/eltan/security/lib/cb_sha256.c @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cryptolib.h> + +uint8_t *cb_sha256_ex(const uint8_t *data, uint64_t len, uint8_t *digest, + bool endian) +{ + int i; + const uint8_t *input_ptr; + uint8_t result[VB2_SHA256_DIGEST_SIZE]; + uint8_t *result_ptr; + uint64_t remaining_len; + struct vb2_sha256_context ctx; + + vb2_sha256_init(&ctx); + + input_ptr = data; + remaining_len = len; + + /* Process data in at most UINT32_MAX byte chunks at a time. */ + while (remaining_len) { + uint32_t block_size; + block_size = (uint32_t) ((remaining_len >= UINT32_MAX) ? + UINT32_MAX : remaining_len); + vb2_sha256_update(&ctx, input_ptr, block_size); + remaining_len -= block_size; + input_ptr += block_size; + } + + result_ptr = result; + vb2_sha256_finalize(&ctx, result_ptr); + for (i = 0; i < VB2_SHA256_DIGEST_SIZE; ++i) { + if (endian) { + /* use big endian here */ + digest[i] = *result_ptr++; + } else { + /* use little endian here */ + digest[VB2_SHA256_DIGEST_SIZE - i - 1] = *result_ptr++; + } + } + return digest; +} + +uint8_t *cb_sha256(const uint8_t *data, uint64_t len, uint8_t *digest) +{ + /* Returned the little endian SHA256 digest */ + return cb_sha256_ex(data, len, digest, 0); +} \ No newline at end of file diff --git a/src/vendorcode/eltan/security/lib/cb_sha512.c b/src/vendorcode/eltan/security/lib/cb_sha512.c new file mode 100644 index 0000000..9d713e7 --- /dev/null +++ b/src/vendorcode/eltan/security/lib/cb_sha512.c @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cryptolib.h> + +uint8_t *cb_sha512_ex(const uint8_t *data, uint64_t len, uint8_t *digest, + bool endian) +{ + int i; + const uint8_t *input_ptr; + uint8_t result[VB2_SHA512_DIGEST_SIZE]; + uint8_t *result_ptr; + uint64_t remaining_len; + struct vb2_sha512_context ctx; + + vb2_sha512_init(&ctx); + + input_ptr = data; + remaining_len = len; + + /* Process data in at most UINT32_MAX byte chunks at a time. */ + while (remaining_len) { + uint32_t block_size; + block_size = (uint32_t) ((remaining_len >= UINT32_MAX) ? + UINT32_MAX : remaining_len); + vb2_sha512_update(&ctx, input_ptr, block_size); + remaining_len -= block_size; + input_ptr += block_size; + } + + result_ptr = result; + vb2_sha512_finalize(&ctx, result_ptr); + for (i = 0; i < VB2_SHA512_DIGEST_SIZE; ++i) { + if (endian) { + /* use big endian here */ + digest[i] = *result_ptr++; + } else { + /* use little endian here */ + digest[VB2_SHA512_DIGEST_SIZE - i - 1] = *result_ptr++; + } + } + return digest; +} + +uint8_t *cb_sha512(const uint8_t *data, uint64_t len, uint8_t *digest) +{ + /* Returned the little endian SHA512 digest */ + return cb_sha512_ex(data, len, digest, 0); +} \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/30831 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If828bde54c79e836a5b05ff0447645d7e06e819a Gerrit-Change-Number: 30831 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

4 18

Change in ...coreboot[master]: intel/945 boards: Use smp_write_pci_intsrc()
by Kyösti Mälkki (Code Review) 25 Jun '19

25 Jun '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30740 Change subject: intel/945 boards: Use smp_write_pci_intsrc() ...................................................................... intel/945 boards: Use smp_write_pci_intsrc() Radically reduces line lengths and splits '(bus<<2) | INT' to separate parameters. Change-Id: I0cfd714da3d2773affdb34d1dab2ac32879e2cfd Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/apple/macbook21/mptable.c M src/mainboard/lenovo/t60/mptable.c M src/mainboard/lenovo/x60/mptable.c M src/mainboard/lenovo/z61t/mptable.c 4 files changed, 62 insertions(+), 62 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/30740/1 diff --git a/src/mainboard/apple/macbook21/mptable.c b/src/mainboard/apple/macbook21/mptable.c index f508eaf..b11b7bb 100644 --- a/src/mainboard/apple/macbook21/mptable.c +++ b/src/mainboard/apple/macbook21/mptable.c @@ -42,21 +42,21 @@ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, isa_bus, 0x00, MP_APIC_ALL, 0x00); smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x00, MP_APIC_ALL, 0x01); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x01 << 2), 0x02, 0x10); /* PCIe root 0.02.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x02 << 2), 0x02, 0x10); /* VGA 0.02.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1b << 2), 0x02, 0x16); /* HD Audio 0:1b.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2), 0x02, 0x11); /* PCIe 0:1c.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x01, 0x02, 0x10); /* PCIe 0:1c.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x02, 0x02, 0x12); /* PCIe 0:1c.2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x03, 0x02, 0x13); /* PCIe 0:1c.3 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) , 0x02, 0x15); /* USB 0:1d.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x01, 0x02, 0x13); /* USB 0:1d.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x02, 0x02, 0x12); /* USB 0:1d.2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x03, 0x02, 0x10); /* USB 0:1d.3 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) , 0x02, 0x12); /* LPC 0:1f.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x01, 0x02, 0x13); /* IDE 0:1f.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x03, 0x02, 0x10); /* SATA 0:1f.3 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x03, (0x03 << 2) , 0x02, 0x13); /* Firewire 3:03.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x01, 0x00, 0x02, 0x10); /* PCIe root 0.01.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x02, 0x00, 0x02, 0x10); /* VGA 0.02.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1b, 0x00, 0x02, 0x16); /* HD Audio 0:1b.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x00, 0x02, 0x11); /* PCIe 0:1c.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x01, 0x02, 0x10); /* PCIe 0:1c.1 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x02, 0x02, 0x12); /* PCIe 0:1c.2 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x03, 0x02, 0x13); /* PCIe 0:1c.3 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x00, 0x02, 0x15); /* USB 0:1d.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x01, 0x02, 0x13); /* USB 0:1d.1 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x02, 0x02, 0x12); /* USB 0:1d.2 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x03, 0x02, 0x10); /* USB 0:1d.3 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x00, 0x02, 0x12); /* LPC 0:1f.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x01, 0x02, 0x13); /* IDE 0:1f.1 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x03, 0x02, 0x10); /* SATA 0:1f.3 */ + smp_write_pci_intsrc(mc, mp_INT, 0x03, 0x03, 0x00, 0x02, 0x13); /* Firewire 3:03.0 */ mptable_lintsrc(mc, isa_bus); return mptable_finalize(mc); diff --git a/src/mainboard/lenovo/t60/mptable.c b/src/mainboard/lenovo/t60/mptable.c index 8a9ee48..86c6f6d 100644 --- a/src/mainboard/lenovo/t60/mptable.c +++ b/src/mainboard/lenovo/t60/mptable.c @@ -42,21 +42,21 @@ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, isa_bus, 0x00, MP_APIC_ALL, 0x00); smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x00, MP_APIC_ALL, 0x01); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x01 << 2), 0x02, 0x10); /* PCIe root 0.02.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x02 << 2), 0x02, 0x10); /* VGA 0.02.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1b << 2), 0x02, 0x11); /* HD Audio 0:1b.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2), 0x02, 0x14); /* PCIe 0:1c.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x01, 0x02, 0x15); /* PCIe 0:1c.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x02, 0x02, 0x16); /* PCIe 0:1c.2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x03, 0x02, 0x17); /* PCIe 0:1c.3 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) , 0x02, 0x10); /* USB 0:1d.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x01, 0x02, 0x11); /* USB 0:1d.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x02, 0x02, 0x12); /* USB 0:1d.2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x03, 0x02, 0x13); /* USB 0:1d.3 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) , 0x02, 0x17); /* LPC 0:1f.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x01, 0x02, 0x10); /* IDE 0:1f.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x02, 0x02, 0x10); /* SATA 0:1f.2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x06, (0x00 << 2) | 0x00, 0x02, 0x10); /* Cardbus 6:00.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x01, 0x00, 0x02, 0x10); /* PCIe root 0.01.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x02, 0x00, 0x02, 0x10); /* VGA 0.02.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1b, 0x00, 0x02, 0x11); /* HD Audio 0:1b.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x00, 0x02, 0x14); /* PCIe 0:1c.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x01, 0x02, 0x15); /* PCIe 0:1c.1 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x02, 0x02, 0x16); /* PCIe 0:1c.2 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x03, 0x02, 0x17); /* PCIe 0:1c.3 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x00, 0x02, 0x10); /* USB 0:1d.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x01, 0x02, 0x11); /* USB 0:1d.1 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x02, 0x02, 0x12); /* USB 0:1d.2 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x03, 0x02, 0x13); /* USB 0:1d.3 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x00, 0x02, 0x17); /* LPC 0:1f.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x01, 0x02, 0x10); /* IDE 0:1f.1 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x02, 0x02, 0x10); /* SATA 0:1f.2 */ + smp_write_pci_intsrc(mc, mp_INT, 0x06, 0x00, 0x00, 0x02, 0x10); /* Cardbus 6:00.0 */ mptable_lintsrc(mc, isa_bus); return mptable_finalize(mc); diff --git a/src/mainboard/lenovo/x60/mptable.c b/src/mainboard/lenovo/x60/mptable.c index 7b23d5a..091fea7 100644 --- a/src/mainboard/lenovo/x60/mptable.c +++ b/src/mainboard/lenovo/x60/mptable.c @@ -42,23 +42,23 @@ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, isa_bus, 0x00, MP_APIC_ALL, 0x00); smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x00, MP_APIC_ALL, 0x01); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x01 << 2), 0x02, 0x10); /* PCIe root 0.02.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x02 << 2), 0x02, 0x10); /* VGA 0.02.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1b << 2), 0x02, 0x11); /* HD Audio 0:1b.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2), 0x02, 0x14); /* PCIe 0:1c.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x01, 0x02, 0x15); /* PCIe 0:1c.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x02, 0x02, 0x16); /* PCIe 0:1c.2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x03, 0x02, 0x17); /* PCIe 0:1c.3 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) , 0x02, 0x10); /* USB 0:1d.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x01, 0x02, 0x11); /* USB 0:1d.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x02, 0x02, 0x12); /* USB 0:1d.2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x03, 0x02, 0x13); /* USB 0:1d.3 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) , 0x02, 0x17); /* LPC 0:1f.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x01, 0x02, 0x10); /* IDE 0:1f.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x02, 0x02, 0x10); /* SATA 0:1f.2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x05, (0x00 << 2) | 0x00, 0x02, 0x10); /* Cardbus 5:00.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x05, (0x00 << 2) | 0x01, 0x02, 0x11); /* Firewire 5:00.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x05, (0x00 << 2) | 0x02, 0x02, 0x12); /* SDHC 5:00.2 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x01, 0x00, 0x02, 0x10); /* PCIe root 0.01.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x02, 0x00, 0x02, 0x10); /* VGA 0.02.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1b, 0x00, 0x02, 0x11); /* HD Audio 0:1b.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x00, 0x02, 0x14); /* PCIe 0:1c.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x01, 0x02, 0x15); /* PCIe 0:1c.1 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x02, 0x02, 0x16); /* PCIe 0:1c.2 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x03, 0x02, 0x17); /* PCIe 0:1c.3 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x00, 0x02, 0x10); /* USB 0:1d.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x01, 0x02, 0x11); /* USB 0:1d.1 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x02, 0x02, 0x12); /* USB 0:1d.2 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x03, 0x02, 0x13); /* USB 0:1d.3 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x00, 0x02, 0x17); /* LPC 0:1f.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x01, 0x02, 0x10); /* IDE 0:1f.1 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x02, 0x02, 0x10); /* SATA 0:1f.2 */ + smp_write_pci_intsrc(mc, mp_INT, 0x05, 0x00, 0x00, 0x02, 0x10); /* Cardbus 5:00.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x05, 0x00, 0x01, 0x02, 0x11); /* Firewire 5:00.1 */ + smp_write_pci_intsrc(mc, mp_INT, 0x05, 0x00, 0x02, 0x02, 0x12); /* SDHC 5:00.2 */ mptable_lintsrc(mc, isa_bus); return mptable_finalize(mc); diff --git a/src/mainboard/lenovo/z61t/mptable.c b/src/mainboard/lenovo/z61t/mptable.c index 8a9ee48..86c6f6d 100644 --- a/src/mainboard/lenovo/z61t/mptable.c +++ b/src/mainboard/lenovo/z61t/mptable.c @@ -42,21 +42,21 @@ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, isa_bus, 0x00, MP_APIC_ALL, 0x00); smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x00, MP_APIC_ALL, 0x01); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x01 << 2), 0x02, 0x10); /* PCIe root 0.02.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x02 << 2), 0x02, 0x10); /* VGA 0.02.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1b << 2), 0x02, 0x11); /* HD Audio 0:1b.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2), 0x02, 0x14); /* PCIe 0:1c.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x01, 0x02, 0x15); /* PCIe 0:1c.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x02, 0x02, 0x16); /* PCIe 0:1c.2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x03, 0x02, 0x17); /* PCIe 0:1c.3 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) , 0x02, 0x10); /* USB 0:1d.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x01, 0x02, 0x11); /* USB 0:1d.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x02, 0x02, 0x12); /* USB 0:1d.2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x03, 0x02, 0x13); /* USB 0:1d.3 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) , 0x02, 0x17); /* LPC 0:1f.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x01, 0x02, 0x10); /* IDE 0:1f.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x02, 0x02, 0x10); /* SATA 0:1f.2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x06, (0x00 << 2) | 0x00, 0x02, 0x10); /* Cardbus 6:00.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x01, 0x00, 0x02, 0x10); /* PCIe root 0.01.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x02, 0x00, 0x02, 0x10); /* VGA 0.02.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1b, 0x00, 0x02, 0x11); /* HD Audio 0:1b.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x00, 0x02, 0x14); /* PCIe 0:1c.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x01, 0x02, 0x15); /* PCIe 0:1c.1 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x02, 0x02, 0x16); /* PCIe 0:1c.2 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x03, 0x02, 0x17); /* PCIe 0:1c.3 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x00, 0x02, 0x10); /* USB 0:1d.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x01, 0x02, 0x11); /* USB 0:1d.1 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x02, 0x02, 0x12); /* USB 0:1d.2 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x03, 0x02, 0x13); /* USB 0:1d.3 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x00, 0x02, 0x17); /* LPC 0:1f.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x01, 0x02, 0x10); /* IDE 0:1f.1 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x02, 0x02, 0x10); /* SATA 0:1f.2 */ + smp_write_pci_intsrc(mc, mp_INT, 0x06, 0x00, 0x00, 0x02, 0x10); /* Cardbus 6:00.0 */ mptable_lintsrc(mc, isa_bus); return mptable_finalize(mc); -- To view, visit https://review.coreboot.org/c/coreboot/+/30740 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0cfd714da3d2773affdb34d1dab2ac32879e2cfd Gerrit-Change-Number: 30740 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 5

Change in ...coreboot[master]: x86/smmstub: Fix compiling with external toolchains
by Arthur Heymans (Code Review) 21 Jun '19

21 Jun '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30504 Change subject: x86/smmstub: Fix compiling with external toolchains ...................................................................... x86/smmstub: Fix compiling with external toolchains Change-Id: I298d24d54b8fb27da96257ccda65b7fbee988ebb Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/smm/Makefile.inc 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/30504/1 diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index 32f5ea7..e6add1d 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -47,8 +47,8 @@ # SMM Stub Module. The stub is used as a trampoline for relocation and normal # SMM handling. -$(obj)/smmstub/smmstub.o: $$(smmstub-objs) - $(CC_smmstub) $(CFLAGS_smmstub) -nostdlib -r -o $@ $^ +$(obj)/smmstub/smmstub.o: $$(smmstub-objs) $(COMPILER_RT_smmstub) + $(LD_smmstub) -nostdlib -r -o $@ $(COMPILER_RT_FLAGS_smmstub) --whole-archive --start-group $(smmstub-objs) --no-whole-archive $(COMPILER_RT_smmstub) --end-group # Link the SMM stub module with a 0-byte heap. ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) -- To view, visit https://review.coreboot.org/c/coreboot/+/30504 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I298d24d54b8fb27da96257ccda65b7fbee988ebb Gerrit-Change-Number: 30504 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 3

Change in ...coreboot[master]: southbridge/intel/common/smbus.{c,h}: Add support for I2C commands
by Frans Hendriks (Code Review) 20 Jun '19

20 Jun '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30800 Change subject: southbridge/intel/common/smbus.{c,h}: Add support for I2C commands ...................................................................... southbridge/intel/common/smbus.{c,h}: Add support for I2C commands Intel Braswell supports communication with I2C device using SMBus controller. This support is missing in actual smbus routines. Added i2c_block_read() and i2c_block_write() which configures the SMBus controller into I2C mode before sending the commands. Added do_i2c_block_write() for sending block writes in I2C mode. BUG=N/A TEST=Facebook FBG-1701 booting Embedded Linux Change-Id: I40f8c0f5257a62398189f36892b8159052481693 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/southbridge/intel/common/smbus.c M src/southbridge/intel/common/smbus.h 2 files changed, 124 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/30800/1 diff --git a/src/southbridge/intel/common/smbus.c b/src/southbridge/intel/common/smbus.c index de4ff91..3b50e6b 100644 --- a/src/southbridge/intel/common/smbus.c +++ b/src/southbridge/intel/common/smbus.c @@ -4,6 +4,7 @@ * Copyright (C) 2005 Yinghai Lu <yinghailu(a)gmail.com> * Copyright (C) 2009 coresystems GmbH * Copyright (C) 2013 Vladimir Serbinenko + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,6 +17,7 @@ */ #include <arch/io.h> +#include <device/pci.h> #include <console/console.h> #include <device/smbus_def.h> #include <stdlib.h> @@ -96,9 +98,8 @@ unsigned char val; smbus_delay(); val = inb(smbus_base + SMBHSTSTAT); - if ((val & SMBHSTSTS_HOST_BUSY)) { + if ((val & SMBHSTSTS_HOST_BUSY)) break; - } } while (--loops); return loops ? 0 : -1; } @@ -208,6 +209,7 @@ int slave_bytes; int bytes_read = 0; unsigned int loops = SMBUS_TIMEOUT; + if (smbus_wait_until_ready(smbus_base) < 0) return SMBUS_WAIT_UNTIL_READY_TIMEOUT; @@ -220,7 +222,7 @@ /* Set the device I'm talking to */ outb(((device & 0x7f) << 1) | 1, smbus_base + SMBXMITADD); /* Set the command/address... */ - outb(cmd & 0xff, smbus_base + SMBHSTCMD); + outb(cmd, smbus_base + SMBHSTCMD); /* Set up for a block data read */ outb((inb(smbus_base + SMBHSTCTL) & 0xc3) | I801_BLOCK_DATA, (smbus_base + SMBHSTCTL)); @@ -350,6 +352,19 @@ } /* Only since ICH5 */ +int i2c_block_read(u8 smbus_devnr, u8 smbus_func, unsigned int device, u8 cmd, + u32 bytes, u8 *buf) +{ + struct device *smbus_dev; + u32 reg; + + /* SMBus I/O BAR */ + smbus_dev = dev_find_slot(0, PCI_DEVFN(smbus_devnr, smbus_func)); + reg = pci_read_config32(smbus_dev, PCI_BASE_ADDRESS_4) & 0xFFFFFFFE; + + return do_i2c_block_read((unsigned int)reg, device, cmd, bytes, buf); +} + int do_i2c_block_read(unsigned int smbus_base, u8 device, unsigned int offset, const unsigned int bytes, u8 *buf) { @@ -418,3 +433,102 @@ return bytes_read; } + +int i2c_block_write(u8 smbus_devnr, u8 smbus_func, unsigned int device, u8 cmd, + u32 bytes, u8 *buf) +{ + struct device *smbus_dev; + u32 reg; + u32 smb_ctlr_reg; + int status; + + /* SMBus I/O BAR */ + smbus_dev = dev_find_slot(0, PCI_DEVFN(smbus_devnr, smbus_func)); + reg = pci_read_config32(smbus_dev, PCI_BASE_ADDRESS_4) & 0xFFFFFFFE; + + smb_ctlr_reg = pci_read_config32(smbus_dev, 0x40); + + /* Enable I2C_EN bit */ + pci_write_config32(smbus_dev, 0x40, smb_ctlr_reg | 4); + + status = do_i2c_block_write((unsigned int)reg, device, cmd, bytes, + buf); + + /* Restore I2C_EN bit */ + pci_write_config32(smbus_dev, 0x40, smb_ctlr_reg); + + return status; +} + +int do_i2c_block_write(unsigned int smbus_base, u8 device, u8 cmd, + const unsigned int bytes, u8 *buf) +{ + u8 status; + int bytes_write; + unsigned int loops = SMBUS_TIMEOUT; + + if (smbus_wait_until_ready(smbus_base) < 0) + return SMBUS_WAIT_UNTIL_READY_TIMEOUT; + + /* Set up transaction */ + /* Disable interrupts */ + outb(inb(smbus_base + SMBHSTCTL) & ~SMBHSTCNT_INTREN, + smbus_base + SMBHSTCTL); + + /* Set the slave address */ + outb(((device & 0x7f) << 1), smbus_base + SMBXMITADD); + + outb(cmd, smbus_base + SMBHSTCMD); + outb(cmd, smbus_base + SMBHSTDAT1); + + /* Number of bytes to write */ + outb(bytes, smbus_base + SMBHSTDAT0); + + /* Set up for a smbus block data write */ + outb((inb(smbus_base + SMBHSTCTL) & 0xc3) | I801_BLOCK_DATA, + (smbus_base + SMBHSTCTL)); + + /* Clear any lingering errors, so the transaction will run */ + outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT); + + /* Send first byte from buffer */ + outb(*buf++, smbus_base + SMBBLKDAT); + + for (bytes_write = 0; bytes_write < bytes; bytes_write++) { + /* Start the command */ + outb((inb(smbus_base + SMBHSTCTL) | SMBHSTCNT_START), + smbus_base + SMBHSTCTL); + + /* poll for it to start */ + if (smbus_wait_until_active(smbus_base) < 0) + return SMBUS_WAIT_UNTIL_ACTIVE_TIMEOUT; + + loops = SMBUS_TIMEOUT; + do { + loops--; + status = inb(smbus_base + SMBHSTSTAT); + if (status & (SMBHSTSTS_FAILED | /* FAILED */ + SMBHSTSTS_BUS_ERR | /* BUS ERR */ + SMBHSTSTS_DEV_ERR)) /* DEV ERR */ + return SMBUS_ERROR; + } while (!(status & SMBHSTSTS_BYTE_DONE) && loops); + + if (status & SMBHSTSTS_BYTE_DONE) { + if (bytes_write+1 < bytes) + outb(*buf++, smbus_base + SMBBLKDAT); + if ((bytes_write + 1 >= bytes) && (bytes > 1)) { + /* indicate that next byte is the last one */ + outb(inb(smbus_base + SMBHSTCTL) | + SMBHSTCNT_LAST_BYTE, + smbus_base + SMBHSTCTL); + } + + outb(status & (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR), + smbus_base + SMBHSTSTAT); + } else { + return SMBUS_ERROR; + } + } + return (bytes_write+1); +} + diff --git a/src/southbridge/intel/common/smbus.h b/src/southbridge/intel/common/smbus.h index be1aa76..f272165 100644 --- a/src/southbridge/intel/common/smbus.h +++ b/src/southbridge/intel/common/smbus.h @@ -4,6 +4,7 @@ * Copyright (C) 2005 Yinghai Lu <yinghailu(a)gmail.com> * Copyright (C) 2009 coresystems GmbH * Copyright (C) 2013 Vladimir Serbinenko + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -43,4 +44,10 @@ /* Only since ICH5 */ int do_i2c_block_read(unsigned int smbus_base, u8 device, unsigned int offset, unsigned int bytes, u8 *buf); +int do_i2c_block_write(unsigned int smbus_base, u8 device, u8 cmd, + const unsigned int bytes, u8 *buf); +int i2c_block_read(u8 smbus_devnr, u8 smbus_func, unsigned int device, u8 cmd, + u32 bytes, u8 *buf); +int i2c_block_write(u8 smbus_devnr, u8 smbus_func, unsigned int device, u8 cmd, + u32 bytes, u8 *buf); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/30800 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40f8c0f5257a62398189f36892b8159052481693 Gerrit-Change-Number: 30800 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

10 56

← Newer
1
...
4
5
6
7
8
9
10
...
130
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2019