coreboot-gerrit January 2019

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Change in ...coreboot[master]: soc/intel/denverton_ns: Allow using FSP repo
by Felix Singer (Code Review) 04 Mar '20

04 Mar '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30931 Change subject: soc/intel/denverton_ns: Allow using FSP repo ...................................................................... soc/intel/denverton_ns: Allow using FSP repo Change-Id: I615305da5865bef305f560f5c90482cf0937b25a Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/denverton_ns/Kconfig 2 files changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/30931/1 diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 8156d18..6f5ed2a 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -85,7 +85,8 @@ bool "Use the IntelFSP based binaries" depends on ADD_FSP_BINARIES depends on SOC_INTEL_APOLLOLAKE || SOC_INTEL_SKYLAKE || \ - SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE + SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE || \ + SOC_INTEL_DENVERTON_NS help When selecting this option, the SoC must set FSP_HEADER_PATH and FSP_FD_PATH correctly so FSP splitting works. diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 1096549..dfb5c37 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -78,6 +78,16 @@ help The memory location of the Intel FSP-S binary for this platform. +config FSP_HEADER_PATH + string "Location of FSP headers" + depends on MAINBOARD_USES_FSP2_0 + default "3rdparty/fsp/DenvertonNSFspBinPkg/Include/" + +config FSP_FD_PATH + string + depends on FSP_USE_REPO + default "3rdparty/fsp/DenvertonNSFspBinPkg/FspBin/DenvertonNSFsp.fd" + # CAR memory layout on DENVERTON_NS hardware: ## CAR base address - 0xfef00000 ## CAR size 1MB - 0x100 (0xfff00) -- To view, visit https://review.coreboot.org/c/coreboot/+/30931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I615305da5865bef305f560f5c90482cf0937b25a Gerrit-Change-Number: 30931 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: x86/acpi_s3: Remove trailing dots from debug message
by Paul Menzel (Code Review) 02 Mar '20

02 Mar '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30806 Change subject: x86/acpi_s3: Remove trailing dots from debug message ...................................................................... x86/acpi_s3: Remove trailing dots from debug message The dot is not needed, as it is no sentence and followed by a line break. Change-Id: I3905853eb7039f9c6d2486a77da47a4460276624 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/arch/x86/acpi_s3.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/30806/1 diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index ad9fe00..07c0332 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -34,10 +34,10 @@ { if (acpi_slp_type < 0) { if (romstage_handoff_is_resume()) { - printk(BIOS_DEBUG, "S3 Resume.\n"); + printk(BIOS_DEBUG, "S3 Resume\n"); acpi_slp_type = ACPI_S3; } else { - printk(BIOS_DEBUG, "Normal boot.\n"); + printk(BIOS_DEBUG, "Normal boot\n"); acpi_slp_type = ACPI_S0; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/30806 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3905853eb7039f9c6d2486a77da47a4460276624 Gerrit-Change-Number: 30806 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: arch/x86: Drop Kconfig SIPI_VECTOR_IN_ROM
by Kyösti Mälkki (Code Review) 21 Dec '19

21 Dec '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30856 Change subject: arch/x86: Drop Kconfig SIPI_VECTOR_IN_ROM ...................................................................... arch/x86: Drop Kconfig SIPI_VECTOR_IN_ROM This was used to enforce 4kiB alignment of _start16bit in romcc bootblock. Platforms requiring this moved away to C_ENVIRONMENT_BOOTBLOCK that globally forces the alignment. Change-Id: I8ca453bbc56ab2aeb127f3e081c69e1b38bb8396 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/Kconfig M src/arch/x86/failover.ld M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/cpu/intel/model_106cx/Kconfig M src/cpu/intel/socket_LGA775/Kconfig M src/cpu/intel/socket_mPGA604/Kconfig M src/cpu/x86/16bit/entry16.inc 7 files changed, 5 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/30856/1 diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 242a7cf..c2fc914 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -81,13 +81,6 @@ default n depends on ARCH_X86 && SMP -# Aligns 16bit entry code in bootblock so that hyper-threading CPUs -# can boot AP CPUs to enable their shared caches. -config SIPI_VECTOR_IN_ROM - bool - default n - depends on ARCH_X86 - # Set the rambase for systems that still need it, only 5 chipsets as of # Sep 2018. This value was 0x100000, chosen to match the entry point # of Linux 2.2 in 1999. The new value, 14 MiB, makes a lot more sense diff --git a/src/arch/x86/failover.ld b/src/arch/x86/failover.ld index b32aa29..eabc9f7 100644 --- a/src/arch/x86/failover.ld +++ b/src/arch/x86/failover.ld @@ -23,12 +23,11 @@ TARGET(binary) SECTIONS { - /* Symbol ap_sipi_vector must be aligned to 4kB to start AP CPUs - * with Startup IPI message without RAM. Align .rom to next 4 byte - * boundary anyway, so no pad byte appears between _rom and _start. + /* Align .rom to 4 byte boundary so no pad byte appears + * between _rom and _start. */ .bogus ROMLOC_MIN : { - . = CONFIG_SIPI_VECTOR_IN_ROM ? ALIGN(4096) : ALIGN(4); + . = ALIGN(4); ROMLOC = .; } >rom = 0xff @@ -49,12 +48,7 @@ * may cause the total size of a section to change when the start * address gets applied. */ - ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) - - (CONFIG_SIPI_VECTOR_IN_ROM ? 4096 : 0); - - /* Post-check proper SIPI vector. */ - _bogus = ASSERT(!CONFIG_SIPI_VECTOR_IN_ROM || (ap_sipi_vector_in_rom == 0xff), - "Address mismatch on AP_SIPI_VECTOR"); + ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16); /DISCARD/ : { *(.comment) diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index fda572d..5c579a1 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -23,10 +23,6 @@ /* Macro to access Local APIC registers at default base. */ #define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x) -#if !IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) -/* Fixed location, ASSERTED in failover.ld if it changes. */ -.set ap_sipi_vector_in_rom, 0xff -#endif #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index f365cf1..2a324fb 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -7,7 +7,6 @@ select SMP select SSE2 select UDELAY_LAPIC - select SIPI_VECTOR_IN_ROM select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig index 8b227bd..6c3d837 100644 --- a/src/cpu/intel/socket_LGA775/Kconfig +++ b/src/cpu/intel/socket_LGA775/Kconfig @@ -13,7 +13,6 @@ select CPU_INTEL_MODEL_1067X select MMX select SSE - select SIPI_VECTOR_IN_ROM config DCACHE_RAM_SIZE hex diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index ca2f7b3..e860ded 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -9,7 +9,6 @@ select MMX select SSE select UDELAY_TSC - select SIPI_VECTOR_IN_ROM select C_ENVIRONMENT_BOOTBLOCK # mPGA604 are usually Intel Netburst CPUs which should have SSE2 diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index 2a9f8c5..f110980 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -29,8 +29,7 @@ #include <arch/rom_segs.h> -#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) || \ - IS_ENABLED(CONFIG_SIPI_VECTOR_IN_ROM) +#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) /* Symbol _start16bit must be aligned to 4kB to start AP CPUs with * Startup IPI message without RAM. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ca453bbc56ab2aeb127f3e081c69e1b38bb8396 Gerrit-Change-Number: 30856 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [WIP] Move AGESA and apufw higher in CBFS
by Kyösti Mälkki (Code Review) 19 Dec '19

19 Dec '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31076 Change subject: [WIP] Move AGESA and apufw higher in CBFS ...................................................................... [WIP] Move AGESA and apufw higher in CBFS Increases continuous free space in CBFS from 5.8 MiB to 7.1 MiB. Will not work with released binaryPI build from 3rdparty/blobs. Change-Id: I3c166102b8774499a0b21f212b5e8a66fe6c52eb Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/amd/pi/hudson/Makefile.inc M src/vendorcode/amd/pi/Kconfig 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/31076/1 diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 81fe7ff..57bad38 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -75,7 +75,7 @@ ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) HUDSON_FWM_POSITION=$(call int-add, $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) 0x20000 1) else -HUDSON_FWM_POSITION=0xfff20000 +HUDSON_FWM_POSITION=0xfffa0000 endif ifeq ($(CONFIG_HUDSON_PSP), y) diff --git a/src/vendorcode/amd/pi/Kconfig b/src/vendorcode/amd/pi/Kconfig index f463b7d..3dc7052 100644 --- a/src/vendorcode/amd/pi/Kconfig +++ b/src/vendorcode/amd/pi/Kconfig @@ -96,7 +96,7 @@ config AGESA_BINARY_PI_LOCATION hex "AGESA PI binary address in ROM" - default 0xFFE00000 + default 0xFFF00000 depends on !AGESA_BINARY_PI_AS_STAGE help Specify the ROM address at which to store the binary Platform -- To view, visit https://review.coreboot.org/c/coreboot/+/31076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c166102b8774499a0b21f212b5e8a66fe6c52eb Gerrit-Change-Number: 31076 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: drivers/smmstore: Fix some issues
by Arthur Heymans (Code Review) 29 Nov '19

29 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30432 Change subject: drivers/smmstore: Fix some issues ...................................................................... drivers/smmstore: Fix some issues This fixes the following: - Make the API ARCH independent (no dependency on size_t) - clean up the code a little Change-Id: I629be25d2a9b65796ae8f7a700b6bdab57b91b22 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/smmstore/store.c M src/include/smmstore.h M src/soc/intel/common/block/smm/smihandler.c 3 files changed, 86 insertions(+), 67 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/30432/1 diff --git a/src/drivers/smmstore/store.c b/src/drivers/smmstore/store.c index 409949a..0a62b3c 100644 --- a/src/drivers/smmstore/store.c +++ b/src/drivers/smmstore/store.c @@ -62,8 +62,8 @@ if (cbfs_locate_file_in_region(&file, CONFIG_SMMSTORE_REGION, CONFIG_SMMSTORE_FILENAME, NULL) < 0) { - printk(BIOS_WARNING, "smm store: " - "Unable to find SMM store file in region '%s'\n", + printk(BIOS_WARNING, + "smm store: Unable to find SMM store file in region '%s'\n", CONFIG_SMMSTORE_REGION); return -1; } @@ -87,14 +87,13 @@ * returns 0 on success, -1 on failure * writes up to `*bufsize` bytes into `buf` and updates `*bufsize` */ -int smmstore_read_region(void *buf, ssize_t *bufsize) +int smmstore_read_region(void *buf, uint32_t *bufsize) { struct region_device store; if (bufsize == NULL) return -1; - *bufsize = 0; if (lookup_store(&store) < 0) { printk(BIOS_WARNING, "reading region failed\n"); return -1; @@ -109,6 +108,66 @@ return 0; } +static enum cb_err scan_end(ssize_t *end) +{ + struct region_device store; + + if (lookup_store(&store) < 0) { + printk(BIOS_WARNING, "reading region failed\n"); + return CB_ERR; + } + ssize_t data_sz = region_device_sz(&store); + + /* scan for end */ + *end = 0; + uint32_t k_sz, v_sz; + while (*end < data_sz) { + /* make odd corner cases identifiable, eg. invalid v_sz */ + k_sz = 0; + + if (rdev_readat(&store, &k_sz, *end, sizeof(k_sz)) < 0) { + printk(BIOS_WARNING, "failed reading key size\n"); + return CB_ERR; + } + + /* found the end */ + if (k_sz == 0xffffffff) + break; + + /* something is fishy here: + * Avoid wrapping (since data_size < MAX_UINT32_T / 2) while + * other problems are covered by the loop condition + */ + if (k_sz > data_sz) { + printk(BIOS_WARNING, "key size out of bounds\n"); + return CB_ERR; + } + + if (rdev_readat(&store, &v_sz, *end + 4, sizeof(v_sz)) < 0) { + printk(BIOS_WARNING, "failed reading value size\n"); + return CB_ERR; + } + + if (v_sz > data_sz) { + printk(BIOS_WARNING, "value size out of bounds\n"); + return CB_ERR; + } + + *end += sizeof(k_sz) + sizeof(v_sz) + k_sz + v_sz + 1; + *end = ALIGN_UP(*end, sizeof(uint32_t)); + } + + printk(BIOS_WARNING, "used smm store size might be 0x%zx bytes\n", *end); + + if (k_sz != 0xffffffff) { + printk(BIOS_WARNING, + "eof of data marker looks invalid: 0x%x\n", k_sz); + return CB_ERR; + } + + return CB_SUCCESS; + +} /* * Append data to region * @@ -124,78 +183,38 @@ return -1; } - ssize_t data_sz = region_device_sz(&store); - - /* scan for end */ - ssize_t end = 0; - uint32_t k_sz, v_sz; - while (end < data_sz) { - /* make odd corner cases identifiable, eg. invalid v_sz */ - k_sz = 0; - - if (rdev_readat(&store, &k_sz, end, sizeof(k_sz)) < 0) { - printk(BIOS_WARNING, "failed reading key size\n"); - return -1; - } - - /* found the end */ - if (k_sz == 0xffffffff) - break; - - /* something is fishy here: - * Avoid wrapping (since data_size < MAX_UINT32_T / 2) while - * other problems are covered by the loop condition - */ - if (k_sz > data_sz) { - printk(BIOS_WARNING, "key size out of bounds\n"); - return -1; - } - - if (rdev_readat(&store, &v_sz, end + 4, sizeof(v_sz)) < 0) { - printk(BIOS_WARNING, "failed reading value size\n"); - return -1; - } - - if (v_sz > data_sz) { - printk(BIOS_WARNING, "value size out of bounds\n"); - return -1; - } - - end += 8 + k_sz + v_sz + 1; - end = ALIGN_UP(end, sizeof(uint32_t)); - } - - printk(BIOS_WARNING, "used smm store size might be 0x%zx bytes\n", end); - - if (k_sz != 0xffffffff) { - printk(BIOS_WARNING, - "eof of data marker looks invalid: 0x%x\n", k_sz); + ssize_t end; + if (scan_end(&end) == CB_ERR) return -1; - } printk(BIOS_WARNING, "used size looks legit\n"); printk(BIOS_WARNING, "open (%zx, %zx) for writing\n", region_device_offset(&store), region_device_sz(&store)); - if (boot_device_rw_subregion(&store.region, &store) < 0) { + if (boot_device_rw_subregion(region_device_region(&store), &store) < 0) { printk(BIOS_WARNING, "couldn't open store for writing\n"); return -1; } - uint32_t record_sz = 8 + key_sz + value_sz + 1; - if (end + record_sz >= data_sz) { + struct region subregion = + { + .offset = end, + .size = sizeof(key_sz) + sizeof(value_sz) + key_sz + value_sz + 1, + }; + + if (region_is_subregion(region_device_region(&store), &subregion)) { printk(BIOS_WARNING, "not enough space for new data\n"); return -1; } - if (rdev_writeat(&store, &key_sz, end, 4) != 4) { + if (rdev_writeat(&store, &key_sz, end, sizeof(key_sz) != sizeof(key_sz))) { printk(BIOS_WARNING, "failed writing key size\n"); } - end += 4; - if (rdev_writeat(&store, &value_sz, end, 4) != 4) { + end += sizeof(key_sz); + if (rdev_writeat(&store, &value_sz, end, sizeof(value_sz) != sizeof(key_sz))) { printk(BIOS_WARNING, "failed writing value size\n"); } - end += 4; + end += sizeof(value_sz); if (rdev_writeat(&store, key, end, key_sz) != key_sz) { printk(BIOS_WARNING, "failed writing key data\n"); } @@ -205,7 +224,7 @@ } end += value_sz; uint8_t nul = 0; - if (rdev_writeat(&store, &nul, end, 1) != 1) { + if (rdev_writeat(&store, &nul, end, sizeof(nul)) != sizeof(nul)) { printk(BIOS_WARNING, "failed writing termination\n"); } diff --git a/src/include/smmstore.h b/src/include/smmstore.h index a535c5b..30a8191 100644 --- a/src/include/smmstore.h +++ b/src/include/smmstore.h @@ -28,22 +28,22 @@ #define SMMSTORE_CMD_APPEND 3 struct smmstore_params_read { - void *buf; - ssize_t bufsize; + uint32_t *buf; + uint32_t bufsize; }; struct smmstore_params_append { - void *key; - size_t keysize; - void *val; - size_t valsize; + uint32_t *key; + uint32_t keysize; + uint32_t *val; + uint32_t valsize; }; /* SMM responder */ uint32_t smmstore_exec(uint8_t command, void *param); /* implementation */ -int smmstore_read_region(void *buf, ssize_t *bufsize); +int smmstore_read_region(void *buf, uint32_t *bufsize); int smmstore_append_data(void *key, uint32_t key_sz, void *value, uint32_t value_sz); int smmstore_clear_region(void); diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 2ffc00f..c125c0c 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -311,7 +311,7 @@ reg_ebx = save_state_ops->get_reg(io_smi, RBX); /* drivers/smmstore/smi.c */ - ret = smmstore_exec(sub_command, (void *)reg_ebx); + ret = smmstore_exec(sub_command, (uintptr_t *)reg_ebx); save_state_ops->set_reg(io_smi, RAX, ret); } -- To view, visit https://review.coreboot.org/c/coreboot/+/30432 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I629be25d2a9b65796ae8f7a700b6bdab57b91b22 Gerrit-Change-Number: 30432 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: device/hypertransport: Drop dev_find_slot() debugging
by Kyösti Mälkki (Code Review) 15 Nov '19

15 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30704 Change subject: device/hypertransport: Drop dev_find_slot() debugging ...................................................................... device/hypertransport: Drop dev_find_slot() debugging Change-Id: I810ca9cfc72de9ea532d53cabdaf8845be837432 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/device/device.c M src/device/device_const.c M src/include/device/device.h 3 files changed, 5 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/30704/1 diff --git a/src/device/device.c b/src/device/device.c index 20a4077..7836af1 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -1253,7 +1253,4 @@ final_link(link); printk(BIOS_INFO, "Devices finalized\n"); - - if (IS_ENABLED(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT)) - ht_report_devtree_sanity(); } diff --git a/src/device/device_const.c b/src/device/device_const.c index 480ac76..cdae33d 100644 --- a/src/device/device_const.c +++ b/src/device/device_const.c @@ -177,15 +177,6 @@ * Work around the devicetree topology being manipulated on-the-fly * on systems with HyperTransport Support. */ - -static int ht_tree_needs_fixing, ht_tree_fixup_failed; - -void ht_report_devtree_sanity(void) -{ - printk(BIOS_INFO, "HT fixup counters %d / %d (rqrd/failed)\n", - ht_tree_needs_fixing, ht_tree_fixup_failed); -} - static const struct bus *ht_bus_reloc(const struct bus *parent, pci_devfn_t devfn) { @@ -222,34 +213,20 @@ DEVTREE_CONST struct device *pcidev_path_on_root(pci_devfn_t devfn) { - DEVTREE_CONST struct device *dev; DEVTREE_CONST struct device *pci_domain; + const struct bus *root; pci_domain = dev_find_path(NULL, DEVICE_PATH_DOMAIN); if (!pci_domain) return NULL; - dev = pcidev_path_behind(pci_domain->link_list, devfn); + root = pci_domain->link_list; /* Static devicetree with HyperTransport has whacky topology. */ - if (!IS_ENABLED(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT)) - return dev; + if (IS_ENABLED(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT)) + root = ht_bus_reloc(root, devfn); - DEVTREE_CONST struct device *dev_fixup, *dev_old_method; - - const struct bus *root = ht_bus_reloc(pci_domain->link_list, devfn); - dev_fixup = pcidev_path_behind(root, devfn); - dev_old_method = dev_find_slot(0, devfn); - - if (ENV_RAMSTAGE) { - if (dev != dev_old_method) - ht_tree_needs_fixing++; - - if (dev_fixup != dev_old_method) - ht_tree_fixup_failed++; - } - - return dev_old_method; + return pcidev_path_behind(root, devfn); } DEVTREE_CONST struct device *pcidev_on_root(uint8_t dev, uint8_t fn) diff --git a/src/include/device/device.h b/src/include/device/device.h index 40a0f58..540b7e3 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -227,7 +227,6 @@ void show_one_resource(int debug_level, struct device *dev, struct resource *resource, const char *comment); void show_all_devs_resources(int debug_level, const char *msg); -void ht_report_devtree_sanity(void); /* Rounding for boundaries. * Due to some chip bugs, go ahead and round IO to 16 -- To view, visit https://review.coreboot.org/c/coreboot/+/30704 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I810ca9cfc72de9ea532d53cabdaf8845be837432 Gerrit-Change-Number: 30704 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: device/hypertransport: Fix regression on dev_find_slot() removal
by Kyösti Mälkki (Code Review) 15 Nov '19

15 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30703 Change subject: device/hypertransport: Fix regression on dev_find_slot() removal ...................................................................... device/hypertransport: Fix regression on dev_find_slot() removal The regression is with the implementation of the functions introduced in commit ad7674e device: Introduce pcidev_on_root() and friends For these platforms, the first PCI node on devicetree is not the root of PCI bus hierarchy, and the topology (bus->children and dev->sibling links) are being manipulated during HyperTransport enumeration. This workaround reverts to old method of using dev_find_slot() while keeping track of whether the new method would give equivalent result. Change-Id: I05a54de542f97159266a1c127da32665957f58f9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M Makefile.inc M src/device/device.c M src/device/device_const.c M src/device/hypertransport.c M src/include/device/device.h M src/include/device/pci.h 6 files changed, 87 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/30703/1 diff --git a/Makefile.inc b/Makefile.inc index 2741b19..24b5164 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -577,7 +577,10 @@ verstage-y+=$(DEVICETREE_STATIC_C) bootblock-y+=$(DEVICETREE_STATIC_C) postcar-y+=$(DEVICETREE_STATIC_C) + +ifneq ($(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT),y) smm-y+=$(DEVICETREE_STATIC_C) +endif ####################################################################### # Clean up rules diff --git a/src/device/device.c b/src/device/device.c index 7836af1..20a4077 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -1253,4 +1253,7 @@ final_link(link); printk(BIOS_INFO, "Devices finalized\n"); + + if (IS_ENABLED(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT)) + ht_report_devtree_sanity(); } diff --git a/src/device/device_const.c b/src/device/device_const.c index ec128e8..480ac76 100644 --- a/src/device/device_const.c +++ b/src/device/device_const.c @@ -173,6 +173,43 @@ return child; } +/*** + * Work around the devicetree topology being manipulated on-the-fly + * on systems with HyperTransport Support. + */ + +static int ht_tree_needs_fixing, ht_tree_fixup_failed; + +void ht_report_devtree_sanity(void) +{ + printk(BIOS_INFO, "HT fixup counters %d / %d (rqrd/failed)\n", + ht_tree_needs_fixing, ht_tree_fixup_failed); +} + +static const struct bus *ht_bus_reloc(const struct bus *parent, + pci_devfn_t devfn) +{ + DEVTREE_CONST struct device *dev; + DEVTREE_CONST struct bus *bus; + + /* HyperTransport enumeration fixes up the whacky + * topology present in static devicetree. + */ + if (ENV_RAMSTAGE && (SCAN_COMPLETE == ht_scanning_status())) + return parent; + + if (devfn >= PCI_DEVFN(0x18, 0)) + return parent; + + /* One of the links is bus for devices 0:00.x to 0:17.x. */ + dev = pcidev_path_behind(parent, PCI_DEVFN(0x18, 0)); + for (bus = dev->link_list; bus; bus = bus->next) + if (bus->children) + return bus; + + return NULL; +} + DEVTREE_CONST struct device *pcidev_path_behind( const struct bus *parent, pci_devfn_t devfn) { @@ -185,12 +222,34 @@ DEVTREE_CONST struct device *pcidev_path_on_root(pci_devfn_t devfn) { + DEVTREE_CONST struct device *dev; DEVTREE_CONST struct device *pci_domain; pci_domain = dev_find_path(NULL, DEVICE_PATH_DOMAIN); if (!pci_domain) return NULL; - return pcidev_path_behind(pci_domain->link_list, devfn); + + dev = pcidev_path_behind(pci_domain->link_list, devfn); + + /* Static devicetree with HyperTransport has whacky topology. */ + if (!IS_ENABLED(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT)) + return dev; + + DEVTREE_CONST struct device *dev_fixup, *dev_old_method; + + const struct bus *root = ht_bus_reloc(pci_domain->link_list, devfn); + dev_fixup = pcidev_path_behind(root, devfn); + dev_old_method = dev_find_slot(0, devfn); + + if (ENV_RAMSTAGE) { + if (dev != dev_old_method) + ht_tree_needs_fixing++; + + if (dev_fixup != dev_old_method) + ht_tree_fixup_failed++; + } + + return dev_old_method; } DEVTREE_CONST struct device *pcidev_on_root(uint8_t dev, uint8_t fn) diff --git a/src/device/hypertransport.c b/src/device/hypertransport.c index ed6b2dd..fd4961e 100644 --- a/src/device/hypertransport.c +++ b/src/device/hypertransport.c @@ -244,6 +244,13 @@ } } +static int ht_scan_chain_process = SCAN_NOT_STARTED; + +int ht_scanning_status(void) +{ + return ht_scan_chain_process; +} + static unsigned int do_hypertransport_scan_chain(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned *ht_unitid_base, @@ -276,6 +283,9 @@ /* Restore the hypertransport chain to it's uninitialized state. */ ht_collapse_early_enumeration(bus, offset_unitid); + if (bus->secondary == 0) + ht_scan_chain_process = SCAN_IN_PROGRESS; + /* See which static device nodes I have. */ old_devices = bus->children; bus->children = 0; @@ -472,6 +482,9 @@ last_func->sibling = old_devices; } + if (bus->secondary == 0) + ht_scan_chain_process = SCAN_COMPLETE; + return next_unitid; } diff --git a/src/include/device/device.h b/src/include/device/device.h index 540b7e3..40a0f58 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -227,6 +227,7 @@ void show_one_resource(int debug_level, struct device *dev, struct resource *resource, const char *comment); void show_all_devs_resources(int debug_level, const char *msg); +void ht_report_devtree_sanity(void); /* Rounding for boundaries. * Due to some chip bugs, go ahead and round IO to 16 diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 7cf7e06..41ad281 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -122,6 +122,13 @@ int pci_msix_table_bar(struct device *dev, u32 *offset, u8 *idx); struct msix_entry *pci_msix_get_table(struct device *dev); +enum { + SCAN_NOT_STARTED = 0, + SCAN_IN_PROGRESS, + SCAN_COMPLETE +}; +int ht_scanning_status(void); + #define PCI_IO_BRIDGE_ALIGN 4096 #define PCI_MEM_BRIDGE_ALIGN (1024*1024) -- To view, visit https://review.coreboot.org/c/coreboot/+/30703 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I05a54de542f97159266a1c127da32665957f58f9 Gerrit-Change-Number: 30703 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: cpu/intel/car/core2: Update microcode in CAR setup
by Arthur Heymans (Code Review) 07 Nov '19

07 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30775 Change subject: cpu/intel/car/core2: Update microcode in CAR setup ...................................................................... cpu/intel/car/core2: Update microcode in CAR setup This updates the BSP microcode during CAR setup. Change-Id: I8ecd1b99e18c7e73ae47f850fdc4870751dc6e8c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/car/core2/cache_as_ram.S 1 file changed, 28 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/30775/1 diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S index 981b12d..4fb8c66 100644 --- a/src/cpu/intel/car/core2/cache_as_ram.S +++ b/src/cpu/intel/car/core2/cache_as_ram.S @@ -111,6 +111,17 @@ movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax wrmsr + /* Cache the whole rom to fetch microcode updates */ + movl $MTRR_PHYS_BASE(1), %ecx + xorl %edx, %edx + movl $CACHE_ROM_BASE | MTRR_TYPE_WRPROT, %eax + wrmsr + + movl $MTRR_PHYS_MASK(1), %ecx + rdmsr + movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax + wrmsr + post_code(0x25) /* Enable MTRR. */ @@ -131,15 +142,17 @@ invd movl %eax, %cr0 - /* Clear the cache memory region. This will also fill up the cache. */ - movl $CACHE_AS_RAM_BASE, %esi - movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE >> 2), %ecx - xorl %eax, %eax - rep stosl +#if IS_ENABLED(CONFIG_MICROCODE_UPDATE_PRE_RAM) +update_microcode: + /* put the return address in %esp */ + movl $end_microcode_update, %esp + jmp update_bsp_microcode +end_microcode_update: +#endif +cache_xip: post_code(0x26) - /* Enable Cache-as-RAM mode by disabling cache. */ + /* Disable caching to set final MTRRs for speeding up XIP. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax movl %eax, %cr0 @@ -165,8 +178,16 @@ /* Enable cache. */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax + invd movl %eax, %cr0 + /* Clear the cache memory region. This will also fill up the cache. */ + movl $CACHE_AS_RAM_BASE, %esi + movl %esi, %edi + movl $(CACHE_AS_RAM_SIZE >> 2), %ecx + xorl %eax, %eax + rep stosl + /* Setup the stack. */ mov $_car_stack_end, %esp -- To view, visit https://review.coreboot.org/c/coreboot/+/30775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ecd1b99e18c7e73ae47f850fdc4870751dc6e8c Gerrit-Change-Number: 30775 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 9

Change in ...coreboot[master]: util/autoport: Make dsdt.asl prettier
by Angel Pons (Code Review) 03 Nov '19

03 Nov '19

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30971 Change subject: util/autoport: Make dsdt.asl prettier ...................................................................... util/autoport: Make dsdt.asl prettier Small cosmetic changes which fix OCD-inducing aesthetic inaccuracies. Change-Id: I8fef4bbe12b283cee2ab8d078de950171757bbfe Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/autoport/main.go 1 file changed, 7 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/30971/1 diff --git a/util/autoport/main.go b/util/autoport/main.go index ee26966..5d660d1 100644 --- a/util/autoport/main.go +++ b/util/autoport/main.go @@ -842,13 +842,14 @@ for _, define := range DSDTDefines { if define.Comment != "" { - fmt.Fprintf(dsdt, "\t/* %s. */\n", define.Comment) + fmt.Fprintf(dsdt, "\t/* %s. */\n", define.Comment) } dsdt.WriteString("#define " + define.Key + " " + define.Value + "\n") } dsdt.WriteString( - `#include <arch/acpi.h> + ` +#include <arch/acpi.h> DefinitionBlock( "dsdt.aml", "DSDT", @@ -858,7 +859,7 @@ 0x20141018 // OEM revision ) { - // Some generic macros + /* Some generic macros */ #include "acpi/platform.asl" `) @@ -870,9 +871,8 @@ } dsdt.WriteString(` - Scope (\_SB) { - Device (PCI0) - { + Device (\_SB.PCI0) + { `) for _, x := range DSDTPCI0Includes { if x.Comment != "" { @@ -881,8 +881,7 @@ fmt.Fprintf(dsdt, "\t\t#include <%s>\n", x.File) } dsdt.WriteString( - ` } - } + ` } } `) -- To view, visit https://review.coreboot.org/c/coreboot/+/30971 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8fef4bbe12b283cee2ab8d078de950171757bbfe Gerrit-Change-Number: 30971 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

4 8

Change in ...coreboot[master]: [WIP] Reduce (void **) pointer usage
by Arthur Heymans (Code Review) 02 Nov '19

02 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30684 Change subject: [WIP] Reduce (void **) pointer usage ...................................................................... [WIP] Reduce (void **) pointer usage Use uintptr_t * instead. Change-Id: I8ef5d9fad0298c79806fd94ca053027822022ac2 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/haswell/stage_cache.c M src/cpu/intel/model_206ax/stage_cache.c M src/drivers/intel/fsp1_1/include/fsp/memmap.h M src/drivers/intel/fsp1_1/raminit.c M src/drivers/intel/fsp1_1/ramstage.c M src/drivers/intel/fsp1_1/stack.c M src/drivers/intel/fsp1_1/stage_cache.c M src/drivers/intel/fsp2_0/include/fsp/memmap.h M src/drivers/intel/fsp2_0/stage_cache.c M src/include/stage_cache.h M src/lib/ext_stage_cache.c M src/soc/amd/stoneyridge/cpu.c M src/soc/amd/stoneyridge/include/soc/northbridge.h M src/soc/amd/stoneyridge/ramtop.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/apollolake/cpu.c M src/soc/intel/apollolake/memmap.c M src/soc/intel/baytrail/stage_cache.c M src/soc/intel/braswell/cpu.c M src/soc/intel/braswell/memmap.c M src/soc/intel/braswell/northcluster.c M src/soc/intel/broadwell/stage_cache.c M src/soc/intel/cannonlake/memmap.c M src/soc/intel/cannonlake/smmrelocate.c M src/soc/intel/common/block/include/intelblocks/smm.h M src/soc/intel/common/block/smm/smm.c M src/soc/intel/denverton_ns/cpu.c M src/soc/intel/denverton_ns/include/soc/smm.h M src/soc/intel/denverton_ns/memmap.c M src/soc/intel/denverton_ns/romstage.c M src/soc/intel/icelake/memmap.c M src/soc/intel/icelake/smmrelocate.c M src/soc/intel/skylake/memmap.c M src/soc/intel/skylake/romstage/romstage_fsp20.c M src/soc/intel/skylake/smmrelocate.c 35 files changed, 102 insertions(+), 124 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/30684/1 diff --git a/src/cpu/intel/haswell/stage_cache.c b/src/cpu/intel/haswell/stage_cache.c index 009cc09..fb4a6c3 100644 --- a/src/cpu/intel/haswell/stage_cache.c +++ b/src/cpu/intel/haswell/stage_cache.c @@ -17,10 +17,10 @@ #include <stage_cache.h> #include "haswell.h" -void stage_cache_external_region(void **base, size_t *size) +void stage_cache_external_region(uintptr_t *base, size_t *size) { /* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. * The top of RAM is defined to be the TSEG base address. */ *size = RESERVED_SMM_SIZE; - *base = (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET); + *base = cbmem_top() + RESERVED_SMM_OFFSET; } diff --git a/src/cpu/intel/model_206ax/stage_cache.c b/src/cpu/intel/model_206ax/stage_cache.c index 26dc5e0..a0aaba5 100644 --- a/src/cpu/intel/model_206ax/stage_cache.c +++ b/src/cpu/intel/model_206ax/stage_cache.c @@ -17,12 +17,12 @@ #include <stage_cache.h> #include "model_206ax.h" -void stage_cache_external_region(void **base, size_t *size) +void stage_cache_external_region(uintptr_t *base, size_t *size) { /* * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. * The top of RAM is defined to be the TSEG base address. */ *size = RESERVED_SMM_SIZE; - *base = (void *)((uintptr_t)cbmem_top() + RESERVED_SMM_OFFSET); + *base = cbmem_top() + RESERVED_SMM_OFFSET; } diff --git a/src/drivers/intel/fsp1_1/include/fsp/memmap.h b/src/drivers/intel/fsp1_1/include/fsp/memmap.h index 965bce6..49bd019 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/memmap.h +++ b/src/drivers/intel/fsp1_1/include/fsp/memmap.h @@ -27,7 +27,7 @@ /* Fills in the arguments for the entire SMM region covered by chipset * protections. e.g. TSEG. */ -void smm_region(void **start, size_t *size); +void smm_region(uintptr_t *start, size_t *size); enum { /* SMM handler area. */ @@ -42,6 +42,6 @@ /* Fills in the start and size for the requested SMM subregion. Returns * 0 on susccess, < 0 on failure. */ -int smm_subregion(int sub, void **start, size_t *size); +int smm_subregion(int sub, uintptr_t *start, size_t *size); #endif /* _COMMON_MEMMAP_H_ */ diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index 7fed2a1..ad9e9dd 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -147,12 +147,12 @@ /* Display SMM area */ #if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) - char *smm_base; + uintptr_t smm_base; size_t smm_size; - smm_region((void **)&smm_base, &smm_size); + smm_region(&smm_base, &smm_size); printk(BIOS_DEBUG, "0x%08x: smm_size\n", (unsigned int)smm_size); - printk(BIOS_DEBUG, "0x%p: smm_base\n", smm_base); + printk(BIOS_DEBUG, "0x%08x: smm_base\n", (unsigned int)smm_base); #endif /* Migrate CAR data */ diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index 864ab45..41d5437 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -33,19 +33,19 @@ /* Display SMM memory map */ static void smm_memory_map(void) { - void *base; + uintptr_t base; size_t size; int i; printk(BIOS_SPEW, "SMM Memory Map\n"); smm_region(&base, &size); - printk(BIOS_SPEW, "SMRAM : %p 0x%zx\n", base, size); + printk(BIOS_SPEW, "SMRAM : 0x%08x 0x%zx\n", (unsigned int)base, size); for (i = 0; i < SMM_SUBREGION_NUM; i++) { if (smm_subregion(i, &base, &size)) continue; - printk(BIOS_SPEW, " Subregion %d: %p 0x%zx\n", i, base, size); + printk(BIOS_SPEW, " Subregion %d: 0x%08x 0x%zx\n", i, (unsigned int)base, size); } } diff --git a/src/drivers/intel/fsp1_1/stack.c b/src/drivers/intel/fsp1_1/stack.c index eb2a637..1b748aa 100644 --- a/src/drivers/intel/fsp1_1/stack.c +++ b/src/drivers/intel/fsp1_1/stack.c @@ -117,9 +117,8 @@ num_mtrrs++; #if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) - void *smm_base; + uintptr_t smm_base; size_t smm_size; - uint32_t tseg_base; /* * Cache the TSEG region at the top of ram. This region is not @@ -128,11 +127,10 @@ * the SMM handler as well as using the TSEG region for other purposes. */ smm_region(&smm_base, &smm_size); - tseg_base = (uint32_t)smm_base; slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */ slot = stack_push32(slot, ~(alignment - 1) | MTRR_PHYS_MASK_VALID); slot = stack_push32(slot, 0); /* upper base */ - slot = stack_push32(slot, tseg_base | MTRR_TYPE_WRBACK); + slot = stack_push32(slot, (uint32_t)smm_base | MTRR_TYPE_WRBACK); num_mtrrs++; #endif diff --git a/src/drivers/intel/fsp1_1/stage_cache.c b/src/drivers/intel/fsp1_1/stage_cache.c index 2d594e6..4895340 100644 --- a/src/drivers/intel/fsp1_1/stage_cache.c +++ b/src/drivers/intel/fsp1_1/stage_cache.c @@ -18,11 +18,11 @@ #include <fsp/memmap.h> #include <stage_cache.h> -void stage_cache_external_region(void **base, size_t *size) +void stage_cache_external_region(uintptr_t *base, size_t *size) { if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) { printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n"); - *base = NULL; + *base = 0; *size = 0; } } diff --git a/src/drivers/intel/fsp2_0/include/fsp/memmap.h b/src/drivers/intel/fsp2_0/include/fsp/memmap.h index 965bce6..49bd019 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/memmap.h +++ b/src/drivers/intel/fsp2_0/include/fsp/memmap.h @@ -27,7 +27,7 @@ /* Fills in the arguments for the entire SMM region covered by chipset * protections. e.g. TSEG. */ -void smm_region(void **start, size_t *size); +void smm_region(uintptr_t *start, size_t *size); enum { /* SMM handler area. */ @@ -42,6 +42,6 @@ /* Fills in the start and size for the requested SMM subregion. Returns * 0 on susccess, < 0 on failure. */ -int smm_subregion(int sub, void **start, size_t *size); +int smm_subregion(int sub, uintptr_t *start, size_t *size); #endif /* _COMMON_MEMMAP_H_ */ diff --git a/src/drivers/intel/fsp2_0/stage_cache.c b/src/drivers/intel/fsp2_0/stage_cache.c index 434eae9..2ea6656 100644 --- a/src/drivers/intel/fsp2_0/stage_cache.c +++ b/src/drivers/intel/fsp2_0/stage_cache.c @@ -20,11 +20,11 @@ #include <reset.h> #include <program_loading.h> -void stage_cache_external_region(void **base, size_t *size) +void stage_cache_external_region(uintptr_t *base, size_t *size) { if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) { printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n"); - *base = NULL; + *base = 0; *size = 0; } } diff --git a/src/include/stage_cache.h b/src/include/stage_cache.h index 28cb859..2a6c3bc 100644 --- a/src/include/stage_cache.h +++ b/src/include/stage_cache.h @@ -41,7 +41,7 @@ /* Load the cached stage at given location returning the stage entry point. */ void stage_cache_load_stage(int stage_id, struct prog *stage); /* Fill in parameters for the external stage cache, if utilized. */ -void stage_cache_external_region(void **base, size_t *size); +void stage_cache_external_region(uintptr_t *base, size_t *size); /* Metadata associated with each stage. */ struct stage_cache { diff --git a/src/lib/ext_stage_cache.c b/src/lib/ext_stage_cache.c index c3d4aee..35bcce4 100644 --- a/src/lib/ext_stage_cache.c +++ b/src/lib/ext_stage_cache.c @@ -32,12 +32,12 @@ static void stage_cache_create_empty(void) { struct imd *imd; - void *base; + uintptr_t base; size_t size; imd = imd_get(); stage_cache_external_region(&base, &size); - imd_handle_init(imd, (void *)(size + (uintptr_t)base)); + imd_handle_init(imd, (void *)(size + base)); printk(BIOS_DEBUG, "External stage cache:\n"); imd_create_tiered_empty(imd, 4096, 4096, 1024, 32); @@ -48,12 +48,12 @@ static void stage_cache_recover(void) { struct imd *imd; - void *base; + uintptr_t base; size_t size; imd = imd_get(); stage_cache_external_region(&base, &size); - imd_handle_init(imd, (void *)(size + (uintptr_t)base)); + imd_handle_init(imd, (void *)(size + base)); if (imd_recover(imd)) printk(BIOS_DEBUG, "Unable to recover external stage cache.\n"); } diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index 1d9804d..e5b8bea 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -62,21 +62,21 @@ static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { - void *smm_base; + uintptr_t smm_base; size_t smm_size; - void *handler_base; + uintptr_t handler_base; size_t handler_size; /* Initialize global tracking state. */ smm_region_info(&smm_base, &smm_size); smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size); - relo_attrs.smbase = (uint32_t)smm_base; + relo_attrs.smbase = smm_base; relo_attrs.tseg_base = relo_attrs.smbase; relo_attrs.tseg_mask = ALIGN_DOWN(~(smm_size - 1), 128 * KiB); relo_attrs.tseg_mask |= SMM_TSEG_WB; - *perm_smbase = (uintptr_t)handler_base; + *perm_smbase = handler_base; *perm_smsize = handler_size; *smm_save_state_size = sizeof(amd64_smm_state_save_area_t); } diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h index d62c791..82be938 100644 --- a/src/soc/amd/stoneyridge/include/soc/northbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h @@ -114,12 +114,12 @@ * Fills in the arguments for the entire SMM region covered by chipset * protections. e.g. TSEG. */ -void smm_region_info(void **start, size_t *size); +void smm_region_info(uintptr_t *start, size_t *size); /* * Fills in the start and size for the requested SMM subregion. Returns * 0 on success, < 0 on failure. */ -int smm_subregion(int sub, void **start, size_t *size); +int smm_subregion(int sub, uintptr_t *start, size_t *size); void domain_enable_resources(struct device *dev); void domain_read_resources(struct device *dev); void domain_set_resources(struct device *dev); diff --git a/src/soc/amd/stoneyridge/ramtop.c b/src/soc/amd/stoneyridge/ramtop.c index 15968ab..ea3bd8b 100644 --- a/src/soc/amd/stoneyridge/ramtop.c +++ b/src/soc/amd/stoneyridge/ramtop.c @@ -80,18 +80,18 @@ return CONFIG_SMM_TSEG_SIZE; } -void stage_cache_external_region(void **base, size_t *size) +void stage_cache_external_region(uintptr_t *base, size_t *size) { if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) { printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n"); - *base = NULL; + *base = 0; *size = 0; } } -void smm_region_info(void **start, size_t *size) +void smm_region_info(uintptr_t *start, size_t *size) { - *start = (void *)smm_region_start(); + *start = smm_region_start(); *size = smm_region_size(); } @@ -117,7 +117,7 @@ wrmsr(SMM_MASK_MSR, mask); } -int smm_subregion(int sub, void **start, size_t *size) +int smm_subregion(int sub, uintptr_t *start, size_t *size) { uintptr_t sub_base; size_t sub_size; @@ -143,7 +143,7 @@ return -1; } - *start = (void *)sub_base; + *start = sub_base; *size = sub_size; return 0; diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 9314488..e89f9e6 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -82,7 +82,7 @@ { struct postcar_frame pcf; uintptr_t top_of_ram; - void *smm_base; + uintptr_t smm_base; size_t smm_size; uintptr_t tseg_base; msr_t base, mask; diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index bcec28e..89faa85 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -196,9 +196,9 @@ static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { - void *smm_base; + uintptr_t smm_base; size_t smm_size; - void *handler_base; + uintptr_t handler_base; size_t handler_size; /* All range registers are aligned to 4KiB */ diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index be15e16..50ececa 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -48,7 +48,7 @@ return tolum; } -int smm_subregion(int sub, void **start, size_t *size) +int smm_subregion(int sub, uintptr_t *start, size_t *size) { uintptr_t sub_base; size_t sub_size; @@ -56,7 +56,6 @@ const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; smm_region_info(&smm_base, &sub_size); - sub_base = (uintptr_t)smm_base; assert(sub_size > CONFIG_SMM_RESERVED_SIZE); @@ -74,7 +73,7 @@ return -1; } - *start = (void *)sub_base; + *start = smm_base; *size = sub_size; return 0; diff --git a/src/soc/intel/baytrail/stage_cache.c b/src/soc/intel/baytrail/stage_cache.c index 4c2a976..8e8c67f 100644 --- a/src/soc/intel/baytrail/stage_cache.c +++ b/src/soc/intel/baytrail/stage_cache.c @@ -17,7 +17,7 @@ #include <stage_cache.h> #include <soc/smm.h> -void stage_cache_external_region(void **base, size_t *size) +void stage_cache_external_region(uintptr_t *base, size_t *size) { char *smm_base; /* 1MiB cache size */ @@ -27,5 +27,5 @@ * cbmem_top(). */ smm_base = cbmem_top(); *size = cache_size; - *base = &smm_base[smm_region_size() - cache_size]; + *base = smm_base + smm_region_size() - cache_size; } diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index 12f34fb..b4face2 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -147,7 +147,7 @@ static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { - void *smm_base; + uintptr_t smm_base; size_t smm_size; /* All range registers are aligned to 4KiB */ diff --git a/src/soc/intel/braswell/memmap.c b/src/soc/intel/braswell/memmap.c index d7c9952..89c3ab0 100644 --- a/src/soc/intel/braswell/memmap.c +++ b/src/soc/intel/braswell/memmap.c @@ -29,9 +29,9 @@ return smm_size; } -void smm_region(void **start, size_t *size) +void smm_region(uintptr_t *start, size_t *size) { - *start = (void *)((iosf_bunit_read(BUNIT_SMRRL) & 0xFFFF) << 20); + *start = (iosf_bunit_read(BUNIT_SMRRL) & 0xFFFF) << 20; *size = smm_region_size(); } @@ -51,15 +51,13 @@ * | (TSEG) | * +-------------------------+ BUNIT_SMRRL */ -int smm_subregion(int sub, void **start, size_t *size) +int smm_subregion(int sub, uintptr_t *start, size_t *size) { uintptr_t sub_base; - void *sub_ptr; size_t sub_size; const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; - smm_region(&sub_ptr, &sub_size); - sub_base = (uintptr_t)sub_ptr; + smm_region(&sub_base, &sub_size); switch (sub) { case SMM_SUBREGION_HANDLER: @@ -75,7 +73,7 @@ return -1; } - *start = (void *)sub_base; + *start = sub_base; *size = sub_size; return 0; @@ -83,7 +81,7 @@ void *cbmem_top(void) { - char *smm_base; + uintptr_t smm_base; size_t smm_size; /* @@ -114,6 +112,6 @@ * +-------------------------+ */ - smm_region((void **)&smm_base, &smm_size); + smm_region(&smm_base, &smm_size); return (void *)smm_base; } diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c index 6e148b9..36b4377 100644 --- a/src/soc/intel/braswell/northcluster.c +++ b/src/soc/intel/braswell/northcluster.c @@ -87,7 +87,7 @@ unsigned long mmconf; unsigned long bmbound_k; unsigned long bmbound_hi; - void *smm_base; + uintptr_t smm_base; size_t smm_size; unsigned long tseg_base_k; unsigned long tseg_top_k; diff --git a/src/soc/intel/broadwell/stage_cache.c b/src/soc/intel/broadwell/stage_cache.c index dc59ab7..b812ced 100644 --- a/src/soc/intel/broadwell/stage_cache.c +++ b/src/soc/intel/broadwell/stage_cache.c @@ -18,7 +18,7 @@ #include <stage_cache.h> #include <stdint.h> -void stage_cache_external_region(void **base, size_t *size) +void stage_cache_external_region(uintptr_t *base, size_t *size) { /* The ramstage cache lives in the TSEG region. * The top of RAM is defined to be the TSEG base address. */ @@ -26,6 +26,6 @@ offset -= CONFIG_IED_REGION_SIZE; offset -= CONFIG_SMM_RESERVED_SIZE; - *base = (void *)(cbmem_top() + offset); + *base = cbmem_top() + offset; *size = CONFIG_SMM_RESERVED_SIZE; } diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c index 64e07be..8aeabac 100644 --- a/src/soc/intel/cannonlake/memmap.c +++ b/src/soc/intel/cannonlake/memmap.c @@ -29,9 +29,9 @@ #include <soc/systemagent.h> #include <stdlib.h> -void smm_region(void **start, size_t *size) +void smm_region(uintptr_t *start, size_t *size) { - *start = (void *)sa_get_tseg_base(); + *start = sa_get_tseg_base(); *size = sa_get_tseg_size(); } @@ -46,16 +46,14 @@ * | (TSEG) | * +-------------------------+ TSEG */ -int smm_subregion(int sub, void **start, size_t *size) +int smm_subregion(int sub, uintptr_t *start, size_t *size) { uintptr_t sub_base; size_t sub_size; - void *smm_base; const size_t ied_size = CONFIG_IED_REGION_SIZE; const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; - smm_region(&smm_base, &sub_size); - sub_base = (uintptr_t)smm_base; + smm_region(&sub_base, &sub_size); switch (sub) { case SMM_SUBREGION_HANDLER: @@ -77,7 +75,7 @@ return -1; } - *start = (void *)sub_base; + *start = sub_base; *size = sub_size; return 0; diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c index e688592..59ae790 100644 --- a/src/soc/intel/cannonlake/smmrelocate.c +++ b/src/soc/intel/cannonlake/smmrelocate.c @@ -173,11 +173,11 @@ static void fill_in_relocation_params(struct device *dev, struct smm_relocation_params *params) { - void *handler_base; + uintptr_t handler_base; size_t handler_size; - void *ied_base; + uintptr_t *ied_base; size_t ied_size; - void *tseg_base; + uintptr_t tseg_base; size_t tseg_size; u32 emrr_base; u32 emrr_size; @@ -196,9 +196,9 @@ smm_subregion(SMM_SUBREGION_CHIPSET, &ied_base, &ied_size); params->smram_size = handler_size; - params->smram_base = (uintptr_t)handler_base; + params->smram_base = handler_base; - params->ied_base = (uintptr_t)ied_base; + params->ied_base = ied_base; params->ied_size = ied_size; /* SMRR has 32-bits of valid address aligned to 4KiB. */ @@ -232,24 +232,21 @@ static void setup_ied_area(struct smm_relocation_params *params) { - char *ied_base; - struct ied_header ied = { .signature = "INTEL RSVD", .size = params->ied_size, .reserved = {0}, }; - ied_base = (void *)params->ied_base; printk(BIOS_DEBUG, "IED base = 0x%08x\n", params->ied_base); printk(BIOS_DEBUG, "IED size = 0x%08x\n", params->ied_size); /* Place IED header at IEDBASE. */ - memcpy(ied_base, &ied, sizeof(ied)); + memcpy(params->ied_base, &ied, sizeof(ied)); /* Zero out 32KiB at IEDBASE + 1MiB */ - memset(ied_base + 1 * MiB, 0, 32 * KiB); + memset(params->ied_base + 1 * MiB, 0, 32 * KiB); } void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, diff --git a/src/soc/intel/common/block/include/intelblocks/smm.h b/src/soc/intel/common/block/include/intelblocks/smm.h index c04ec46..e2d38fd 100644 --- a/src/soc/intel/common/block/include/intelblocks/smm.h +++ b/src/soc/intel/common/block/include/intelblocks/smm.h @@ -33,6 +33,6 @@ void smm_southbridge_clear_state(void); void smm_southbridge_enable(uint16_t pm1_events); /* API to get SMM region start and size based on Host Bridge register */ -void smm_region_info(void **start, size_t *size); +void smm_region_info(uintptr_t *start, size_t *size); #endif diff --git a/src/soc/intel/common/block/smm/smm.c b/src/soc/intel/common/block/smm/smm.c index d929975..d9b5645 100644 --- a/src/soc/intel/common/block/smm/smm.c +++ b/src/soc/intel/common/block/smm/smm.c @@ -89,9 +89,9 @@ ); } -void smm_region_info(void **start, size_t *size) +void smm_region_info(uintptr_t *start, size_t *size) { - *start = (void *)sa_get_tseg_base(); + *start = sa_get_tseg_base(); *size = sa_get_tseg_size(); } diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index 676fab7..683af8e 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -91,9 +91,9 @@ static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { - void *smm_base; + uintptr_t smm_base; size_t smm_size; - void *handler_base; + uintptr_t handler_base; size_t handler_size; /* All range registers are aligned to 4KiB */ @@ -108,7 +108,7 @@ relo_attrs.smrr_mask = ~(smm_size - 1) & rmask; relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID; - *perm_smbase = (uintptr_t)handler_base; + *perm_smbase = handler_base; *perm_smsize = handler_size; *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t); } diff --git a/src/soc/intel/denverton_ns/include/soc/smm.h b/src/soc/intel/denverton_ns/include/soc/smm.h index 771c3d8..e597e9d 100644 --- a/src/soc/intel/denverton_ns/include/soc/smm.h +++ b/src/soc/intel/denverton_ns/include/soc/smm.h @@ -33,7 +33,7 @@ /* Fills in the arguments for the entire SMM region covered by chipset * protections. e.g. TSEG. */ -void smm_region(void **start, size_t *size); +void smm_region(uintptr_t *start, size_t *size); enum { /* SMM handler area. */ @@ -48,7 +48,7 @@ /* Fills in the start and size for the requested SMM subregion. Returns * 0 on success, < 0 on failure. */ -int smm_subregion(int sub, void **start, size_t *size); +int smm_subregion(int sub, uintptr_t *start, size_t *size); #if !defined(__PRE_RAM__) && !defined(__SMM___) #include <stdint.h> diff --git a/src/soc/intel/denverton_ns/memmap.c b/src/soc/intel/denverton_ns/memmap.c index a42d861..b4812ab 100644 --- a/src/soc/intel/denverton_ns/memmap.c +++ b/src/soc/intel/denverton_ns/memmap.c @@ -71,13 +71,13 @@ return system_agent_region_base(TOLUD) - smm_region_start(); } -void smm_region(void **start, size_t *size) +void smm_region(uintptr_t *start, size_t *size) { - *start = (void *)smm_region_start(); + *start = smm_region_start(); *size = smm_region_size(); } -int smm_subregion(int sub, void **start, size_t *size) +int smm_subregion(int sub, uintptr_t *start, size_t *size) { uintptr_t sub_base; size_t sub_size; @@ -102,7 +102,7 @@ return -1; } - *start = (void *)sub_base; + *start = sub_base; *size = sub_size; return 0; diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index 617b64a..712ec83 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -147,9 +147,8 @@ uintptr_t top_of_ram; #if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) - void *smm_base; + uintptr_t smm_base; size_t smm_size; - uintptr_t tseg_base; #endif console_init(); @@ -190,8 +189,7 @@ * region for other purposes. */ smm_region(&smm_base, &smm_size); - tseg_base = (uintptr_t)smm_base; - postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK); + postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); #endif run_postcar_phase(&pcf); diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c index 027b8b0..20ae6e8 100644 --- a/src/soc/intel/icelake/memmap.c +++ b/src/soc/intel/icelake/memmap.c @@ -28,9 +28,9 @@ #include <soc/systemagent.h> #include <stdlib.h> -void smm_region(void **start, size_t *size) +void smm_region(uintptr_t *start, size_t *size) { - *start = (void *)sa_get_tseg_base(); + *start = sa_get_tseg_base(); *size = sa_get_tseg_size(); } @@ -45,16 +45,14 @@ * | (TSEG) | * +-------------------------+ TSEG */ -int smm_subregion(int sub, void **start, size_t *size) +int smm_subregion(int sub, uintptr_t *start, size_t *size) { - uintptr_t sub_base; size_t sub_size; - void *smm_base; + uintptr_t smm_base; const size_t ied_size = CONFIG_IED_REGION_SIZE; const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; smm_region(&smm_base, &sub_size); - sub_base = (uintptr_t)smm_base; switch (sub) { case SMM_SUBREGION_HANDLER: @@ -76,7 +74,7 @@ return -1; } - *start = (void *)sub_base; + *start = smm_base; *size = sub_size; return 0; diff --git a/src/soc/intel/icelake/smmrelocate.c b/src/soc/intel/icelake/smmrelocate.c index 57a366a..bb81799 100644 --- a/src/soc/intel/icelake/smmrelocate.c +++ b/src/soc/intel/icelake/smmrelocate.c @@ -172,11 +172,11 @@ static void fill_in_relocation_params(struct device *dev, struct smm_relocation_params *params) { - void *handler_base; + uintptr_t handler_base; size_t handler_size; - void *ied_base; + uintptr_t ied_base; size_t ied_size; - void *tseg_base; + uintptr_t tseg_base; size_t tseg_size; u32 emrr_base; u32 emrr_size; @@ -195,9 +195,9 @@ smm_subregion(SMM_SUBREGION_CHIPSET, &ied_base, &ied_size); params->smram_size = handler_size; - params->smram_base = (uintptr_t)handler_base; + params->smram_base = handler_base; - params->ied_base = (uintptr_t)ied_base; + params->ied_base = ied_base; params->ied_size = ied_size; /* SMRR has 32-bits of valid address aligned to 4KiB. */ @@ -231,24 +231,21 @@ static void setup_ied_area(struct smm_relocation_params *params) { - char *ied_base; - struct ied_header ied = { .signature = "INTEL RSVD", .size = params->ied_size, .reserved = {0}, }; - ied_base = (void *)params->ied_base; printk(BIOS_DEBUG, "IED base = 0x%08x\n", params->ied_base); printk(BIOS_DEBUG, "IED size = 0x%08x\n", params->ied_size); /* Place IED header at IEDBASE. */ - memcpy(ied_base, &ied, sizeof(ied)); + memcpy(params->ied_base, &ied, sizeof(ied)); /* Zero out 32KiB at IEDBASE + 1MiB */ - memset(ied_base + 1 * MiB, 0, 32 * KiB); + memset(params->ied_base + 1 * MiB, 0, 32 * KiB); } void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index f0ccb1d..c33787a 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -40,9 +40,9 @@ return 8*MiB; } -void smm_region(void **start, size_t *size) +void smm_region(uintptr_t *start, size_t *size) { - *start = (void *)sa_get_tseg_base(); + *start = sa_get_tseg_base(); *size = sa_get_tseg_size(); } @@ -57,16 +57,14 @@ * | (TSEG) | * +-------------------------+ TSEG */ -int smm_subregion(int sub, void **start, size_t *size) +int smm_subregion(int sub, uintptr_t *start, size_t *size) { - uintptr_t sub_base; size_t sub_size; - void *smm_base; + uintptr_t smm_base; const size_t ied_size = CONFIG_IED_REGION_SIZE; const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; smm_region(&smm_base, &sub_size); - sub_base = (uintptr_t)smm_base; switch (sub) { case SMM_SUBREGION_HANDLER: @@ -88,7 +86,7 @@ return -1; } - *start = (void *)sub_base; + *start = smm_base; *size = sub_size; return 0; diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 2a60158..248f50f 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -167,7 +167,7 @@ postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { - void *smm_base; + uintptr_t *smm_base; size_t smm_size; uintptr_t tseg_base; @@ -179,7 +179,7 @@ * region for other purposes. */ smm_region(&smm_base, &smm_size); - tseg_base = (uintptr_t)smm_base; + tseg_base = smm_base; postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK); } diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c index cb4e23f..82aacd4 100644 --- a/src/soc/intel/skylake/smmrelocate.c +++ b/src/soc/intel/skylake/smmrelocate.c @@ -241,24 +241,21 @@ static void setup_ied_area(struct smm_relocation_params *params) { - char *ied_base; - struct ied_header ied = { .signature = "INTEL RSVD", .size = params->ied_size, .reserved = {0}, }; - ied_base = (void *)params->ied_base; printk(BIOS_DEBUG, "IED base = 0x%08x\n", params->ied_base); printk(BIOS_DEBUG, "IED size = 0x%08x\n", params->ied_size); /* Place IED header at IEDBASE. */ - memcpy(ied_base, &ied, sizeof(ied)); + memcpy(params->ied_base, &ied, sizeof(ied)); /* Zero out 32KiB at IEDBASE + 1MiB */ - memset(ied_base + (1 << 20), 0, (32 << 10)); + memset(params->ied_base + 1 * MiB, 0, 32 * KiB); } void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, -- To view, visit https://review.coreboot.org/c/coreboot/+/30684 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ef5d9fad0298c79806fd94ca053027822022ac2 Gerrit-Change-Number: 30684 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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coreboot-gerrit January 2019