coreboot-gerrit January 2019

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Change in ...coreboot[master]: mb/google/poppy/variant/atlas: enable USB acpi
by Gaggery Tsai (Code Review) 03 May '19

03 May '19

Gaggery Tsai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30754 Change subject: mb/google/poppy/variant/atlas: enable USB acpi ...................................................................... mb/google/poppy/variant/atlas: enable USB acpi Main objective for this change is to export the bluetooth reset gpio to the kernel for use in an rf-kill operation. To do so, we enable USB acpi and define all of the USB2 devices, which includes bluetooth's reset gpio information. BUG=b:122540489 BRANCH=None TEST=emerge-atlas coreboot chromeos-bootimage $cat sys/firmware/acpi/tables/SSDT > /tmp/ssdt.dat & retrieve ssdt.dat from DUT & $iasl -d ./ssdt.dat & check the HS03 node is with "reset-gpio" under _DSD object Change-Id: I411ef707782655361bd1b8ac2b914b8ae64defeb Signed-off-by: Gaggery Tsai <gaggery.tsai(a)intel.com> --- M src/mainboard/google/poppy/Kconfig M src/mainboard/google/poppy/variants/atlas/devicetree.cb 2 files changed, 25 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/30754/1 diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index 59abe72..197986d 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -150,6 +150,7 @@ select DRIVERS_I2C_MAX98373 select DRIVERS_I2C_DA7219 select DRIVERS_SPI_ACPI + select DRIVERS_USB_ACPI select EXCLUDE_NATIVE_SD_INTERFACE select MAINBOARD_HAS_SPI_TPM_CR50 select VARIANT_HAS_CAMERA_ACPI diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index f8a6e6d..97c10b0 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -268,7 +268,30 @@ device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device device pci 13.0 off end # Integrated Sensor Hub - device pci 14.0 on end # USB xHCI + device pci 14.0 on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""USB Type C Port 1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E2)" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB Type C Port 2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device usb 2.4 on end + end + end + end + end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem device pci 15.0 on -- To view, visit https://review.coreboot.org/c/coreboot/+/30754 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I411ef707782655361bd1b8ac2b914b8ae64defeb Gerrit-Change-Number: 30754 Gerrit-PatchSet: 1 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-MessageType: newchange

6 11

Change in ...coreboot[master]: nb/intel/i945: Check if interleaved even if rank[4] size is zero
by HAOUAS Elyes (Code Review) 23 Apr '19

23 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31007 Change subject: nb/intel/i945: Check if interleaved even if rank[4] size is zero ...................................................................... nb/intel/i945: Check if interleaved even if rank[4] size is zero With this patch, the board can boot when interleaved but rank4 is 0. Tested on 945G-M4, it boot when: DIMM0 + DIMM2 populated: Ok DIMM0 + DIMM3 populated: Ok DIMM1 + DIMM2 populated: Ok DIMM1 + DIMM3 populated: Ok raminit.c still needs channelA populated. It will not boot if channel A is not populated. Change-Id: Ibf130a3d4b6f8fa816f7a5f06822a9b8807be3d4 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/raminit.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/31007/1 diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 64c87da..a46677b 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -2551,9 +2551,6 @@ u32 bankaddr = 0, tmpaddr, mrsaddr = 0; for (i = 0, nonzero = -1; i < 8; i++) { - if (sysinfo->banksize[i] == 0) - continue; - printk(BIOS_DEBUG, "jedec enable sequence: bank %d\n", i); switch (i) { case 0: @@ -2576,6 +2573,9 @@ bankaddr = 0; } + if (sysinfo->banksize[i] == 0) + continue; + /* We have a bank with a non-zero size.. Remember it * for the next offset we have to calculate */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31007 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf130a3d4b6f8fa816f7a5f06822a9b8807be3d4 Gerrit-Change-Number: 31007 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

5 17

Change in ...coreboot[master]: google/kukui: Support I2C TPM and stop supporting SPI TPM
by You-Cheng Syu (Code Review) 23 Apr '19

23 Apr '19

You-Cheng Syu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30978 Change subject: google/kukui: Support I2C TPM and stop supporting SPI TPM ...................................................................... google/kukui: Support I2C TPM and stop supporting SPI TPM Kukui TPM is going to move from SPI to I2C. This CL makes coreboot supports I2C TPM on Kukui. To make things easier, SPI TPM on Kukui is no longer supported. BRANCH=none BUG=b:117916698 TEST=none Change-Id: I194de167aa946d592ba20cff15f076739e5cc096 Signed-off-by: You-Cheng Syu <youcheng(a)google.com> --- M src/mainboard/google/kukui/Kconfig M src/mainboard/google/kukui/verstage.c 2 files changed, 9 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/30978/1 diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index 7635e5f..5de6b5b 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -35,7 +35,7 @@ select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_SPI - select MAINBOARD_HAS_SPI_TPM_CR50 if VBOOT + select MAINBOARD_HAS_I2C_TPM_CR50 if VBOOT select MAINBOARD_HAS_TPM2 if VBOOT config MAINBOARD_DIR @@ -47,9 +47,13 @@ default "Kukui" if BOARD_GOOGLE_KUKUI default "Flapjack" if BOARD_GOOGLE_FLAPJACK -config DRIVER_TPM_SPI_BUS +config DRIVER_TPM_I2C_BUS hex - default 0x0 + default 0x6 + +config DRIVER_TPM_I2C_ADDR + hex + default 0x50 config BOOT_DEVICE_SPI_FLASH_BUS int diff --git a/src/mainboard/google/kukui/verstage.c b/src/mainboard/google/kukui/verstage.c index 9bf93bf..f80fcc1 100644 --- a/src/mainboard/google/kukui/verstage.c +++ b/src/mainboard/google/kukui/verstage.c @@ -15,12 +15,12 @@ #include <security/vboot/vboot_common.h> #include <soc/gpio.h> -#include <soc/spi.h> +#include <soc/i2c.h> #include "gpio.h" void verstage_mainboard_init(void) { - mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz); + mtk_i2c_bus_init(CONFIG_DRIVER_TPM_I2C_BUS); gpio_eint_configure(CR50_IRQ, IRQ_TYPE_EDGE_RISING); } -- To view, visit https://review.coreboot.org/c/coreboot/+/30978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I194de167aa946d592ba20cff15f076739e5cc096 Gerrit-Change-Number: 30978 Gerrit-PatchSet: 1 Gerrit-Owner: You-Cheng Syu <youcheng(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: drivers/intel/fsp2_0: Set basename for FSP binaries
by Felix Singer (Code Review) 22 Apr '19

22 Apr '19

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30930 Change subject: drivers/intel/fsp2_0: Set basename for FSP binaries ...................................................................... drivers/intel/fsp2_0: Set basename for FSP binaries Since there is no standardized naming scheme for the FSP binaries, the option USE_FSP_REPO can't be used on some platforms, because the output filenames differ and the build process awaits "Fsp_*.fd" as filename. As a workaround, add the option -n to SplitFspBin.py, which defines the basename. Change-Id: Idc684ad00033ffafd1090fc32b23549ce9603b4f Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> --- M src/drivers/intel/fsp2_0/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/30930/1 diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 79fe5f8..1d1bae7 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -69,7 +69,7 @@ ifeq ($(CONFIG_FSP_USE_REPO),y) $(obj)/Fsp_M.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH)) - python2 3rdparty/fsp/Tools/SplitFspBin.py split -f $(CONFIG_FSP_FD_PATH) -o "$(obj)" + python2 3rdparty/fsp/Tools/SplitFspBin.py split -f $(CONFIG_FSP_FD_PATH) -o "$(obj)" -n "Fsp.fd" $(obj)/Fsp_S.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH)) $(obj)/Fsp_M.fd true -- To view, visit https://review.coreboot.org/c/coreboot/+/30930 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc684ad00033ffafd1090fc32b23549ce9603b4f Gerrit-Change-Number: 30930 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-MessageType: newchange

3 4

Change in ...coreboot[master]: mb/ibase/mb899/superio_hwm.c: Fix coding style
by HAOUAS Elyes (Code Review) 18 Apr '19

18 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31156 Change subject: mb/ibase/mb899/superio_hwm.c: Fix coding style ...................................................................... mb/ibase/mb899/superio_hwm.c: Fix coding style Change-Id: I6ce74a006a5bf461a1f33203a9e5ea37a1bc7d7b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/ibase/mb899/superio_hwm.c 1 file changed, 62 insertions(+), 47 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/31156/1 diff --git a/src/mainboard/ibase/mb899/superio_hwm.c b/src/mainboard/ibase/mb899/superio_hwm.c index 7fb45f9..5e3d5c5 100644 --- a/src/mainboard/ibase/mb899/superio_hwm.c +++ b/src/mainboard/ibase/mb899/superio_hwm.c @@ -29,7 +29,7 @@ #define FAN_CRUISE_CONTROL_THERMAL 2 #define FAN_SPEED_5625 0 -//#define FAN_TEMPERATURE_30DEGC 0 +#define FAN_TEMPERATURE_30DEGC 0 #define HWM_BASE 0x290 @@ -52,10 +52,10 @@ // FANIN Target Speed Register // FANIN = 337500 / RPM struct fan_speed fan_speeds[] = { - { 0x3c, 5625 }, { 0x41, 5192 }, { 0x47, 4753 }, { 0x4e, 4326 }, - { 0x56, 3924 }, { 0x5f, 3552 }, { 0x69, 3214 }, { 0x74, 2909 }, - { 0x80, 2636 }, { 0x8d, 2393 }, { 0x9b, 2177 }, { 0xaa, 1985 }, - { 0xba, 1814 }, { 0xcb, 1662 }, { 0xdd, 1527 }, { 0xf0, 1406 } + {0x3c, 5625}, {0x41, 5192}, {0x47, 4753}, {0x4e, 4326}, + {0x56, 3924}, {0x5f, 3552}, {0x69, 3214}, {0x74, 2909}, + {0x80, 2636}, {0x8d, 2393}, {0x9b, 2177}, {0xaa, 1985}, + {0xba, 1814}, {0xcb, 1662}, {0xdd, 1527}, {0xf0, 1406} }; struct temperature { @@ -64,94 +64,109 @@ }; struct temperature temperatures[] = { - { 30, 86 }, { 33, 91 }, { 36, 96 }, { 39, 102 }, - { 42, 107 }, { 45, 113 }, { 48, 118 }, { 51, 123 }, - { 54, 129 }, { 57, 134 }, { 60, 140 }, { 63, 145 }, - { 66, 150 }, { 69, 156 }, { 72, 161 }, { 75, 167 } + {30, 86}, {33, 91}, {36, 96}, {39, 102}, + {42, 107}, {45, 113}, {48, 118}, {51, 123}, + {54, 129}, {57, 134}, {60, 140}, {63, 145}, + {66, 150}, {69, 156}, {72, 161}, {75, 167} }; void hwm_setup(void) { - int cpufan_control = 0, sysfan_control = 0; - int cpufan_speed = 0, sysfan_speed = 0; - int cpufan_temperature = 0, sysfan_temperature = 0; + int cpufan_control = FAN_CRUISE_CONTROL_DISABLED; + int cpufan_speed = FAN_SPEED_5625; + int cpufan_temperature = FAN_TEMPERATURE_30DEGC; + int sysfan_control = FAN_CRUISE_CONTROL_DISABLED; + int sysfan_speed = FAN_SPEED_5625; + int sysfan_temperature = FAN_TEMPERATURE_30DEGC; - cpufan_control = FAN_CRUISE_CONTROL_DISABLED; get_option(&cpufan_control, "cpufan_cruise_control"); - cpufan_speed = FAN_SPEED_5625; get_option(&cpufan_speed, "cpufan_speed"); - //cpufan_temperature = FAN_TEMPERATURE_30DEGC; //get_option(&cpufan_temperature, "cpufan_temperature"); - sysfan_control = FAN_CRUISE_CONTROL_DISABLED; get_option(&sysfan_control, "sysfan_cruise_control"); - sysfan_speed = FAN_SPEED_5625; get_option(&sysfan_speed, "sysfan_speed"); - //sysfan_temperature = FAN_TEMPERATURE_30DEGC; //get_option(&sysfan_temperature, "sysfan_temperature"); // hwm_write(0x31, 0x20); // AVCC high limit // hwm_write(0x34, 0x06); // VIN2 low limit hwm_bank(0); - hwm_write(0x59, 0x20); // Diode Selection - hwm_write(0x5d, 0x0f); // All Sensors Diode, not Thermistor + hwm_write(0x59, 0x20); // Diode Selection + hwm_write(0x5d, 0x0f); // All Sensors Diode, not Thermistor hwm_bank(4); - hwm_write(0x54, 0xf1); // SYSTIN temperature offset - hwm_write(0x55, 0x19); // CPUTIN temperature offset - hwm_write(0x56, 0xfc); // AUXTIN temperature offset + hwm_write(0x54, 0xf1); // SYSTIN temperature offset + hwm_write(0x55, 0x19); // CPUTIN temperature offset + hwm_write(0x56, 0xfc); // AUXTIN temperature offset - hwm_bank(0x80); // Default + hwm_bank(0x80); // Default u8 fan_config = 0; // 00 FANOUT is Manual Mode // 01 FANOUT is Thermal Cruise Mode // 10 FANOUT is Fan Speed Cruise Mode switch (cpufan_control) { - case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 4); break; - case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 4); break; + case FAN_CRUISE_CONTROL_SPEED: + fan_config |= (2 << 4); + break; + case FAN_CRUISE_CONTROL_THERMAL: + fan_config |= (1 << 4); + break; } switch (sysfan_control) { - case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 2); break; - case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 2); break; + case FAN_CRUISE_CONTROL_SPEED: + fan_config |= (2 << 2); + break; + case FAN_CRUISE_CONTROL_THERMAL: + fan_config |= (1 << 2); + break; } // This register must be written first hwm_write(0x04, fan_config); switch (cpufan_control) { case FAN_CRUISE_CONTROL_SPEED: - printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to %d RPM\n", - fan_speeds[cpufan_speed].fan_speed); - hwm_write(0x06, fan_speeds[cpufan_speed].fan_in); // CPUFANIN target speed + printk(BIOS_DEBUG, + "Fan Cruise Control setting CPU fan to %d RPM\n", + fan_speeds[cpufan_speed].fan_speed); + // CPUFANIN target speed + hwm_write(0x06, fan_speeds[cpufan_speed].fan_in); break; case FAN_CRUISE_CONTROL_THERMAL: - printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to activation at %d deg C/%d deg F\n", - temperatures[cpufan_temperature].deg_celsius, - temperatures[cpufan_temperature].deg_fahrenheit); - hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius); // CPUFANIN target temperature + printk(BIOS_DEBUG, + "Fan Cruise Control setting CPU fan to activation " + "at %d deg C/%d deg F\n", + temperatures[cpufan_temperature].deg_celsius, + temperatures[cpufan_temperature].deg_fahrenheit); + // CPUFANIN target temperature + hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius); break; } switch (sysfan_control) { case FAN_CRUISE_CONTROL_SPEED: - printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to %d RPM\n", - fan_speeds[sysfan_speed].fan_speed); - hwm_write(0x05, fan_speeds[sysfan_speed].fan_in); // SYSFANIN target speed + printk(BIOS_DEBUG, + "Fan Cruise Control setting system fan to %d RPM\n", + fan_speeds[sysfan_speed].fan_speed); + // SYSFANIN target speed + hwm_write(0x05, fan_speeds[sysfan_speed].fan_in); break; case FAN_CRUISE_CONTROL_THERMAL: - printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to activation at %d deg C/%d deg F\n", - temperatures[sysfan_temperature].deg_celsius, - temperatures[sysfan_temperature].deg_fahrenheit); - hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); // SYSFANIN target temperature + printk(BIOS_DEBUG, + "Fan Cruise Control setting system fan to activation " + "at %d deg C/%d deg F\n", + temperatures[sysfan_temperature].deg_celsius, + temperatures[sysfan_temperature].deg_fahrenheit); + // SYSFANIN target temperature + hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); break; } - hwm_write(0x0e, 0x02); // Fan Output Step Down Time - hwm_write(0x0f, 0x02); // Fan Output Step Up Time + hwm_write(0x0e, 0x02); // Fan Output Step Down Time + hwm_write(0x0f, 0x02); // Fan Output Step Up Time - hwm_write(0x47, 0xaf); // FAN divisor register - hwm_write(0x4b, 0x84); // AUXFANIN speed divisor + hwm_write(0x47, 0xaf); // FAN divisor register + hwm_write(0x4b, 0x84); // AUXFANIN speed divisor - hwm_write(0x40, 0x01); // Init, but no SMI# + hwm_write(0x40, 0x01); // Init, but no SMI# } -- To view, visit https://review.coreboot.org/c/coreboot/+/31156 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ce74a006a5bf461a1f33203a9e5ea37a1bc7d7b Gerrit-Change-Number: 31156 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: mb/kontron/986lcd-m/mainboard.c: Fix coding style
by HAOUAS Elyes (Code Review) 18 Apr '19

18 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31155 Change subject: mb/kontron/986lcd-m/mainboard.c: Fix coding style ...................................................................... mb/kontron/986lcd-m/mainboard.c: Fix coding style Change-Id: I96a1d480c8b618a184c2b5ae08380f45fbd628ec Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/kontron/986lcd-m/mainboard.c 1 file changed, 66 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/31155/1 diff --git a/src/mainboard/kontron/986lcd-m/mainboard.c b/src/mainboard/kontron/986lcd-m/mainboard.c index 73d5997..2c796b7 100644 --- a/src/mainboard/kontron/986lcd-m/mainboard.c +++ b/src/mainboard/kontron/986lcd-m/mainboard.c @@ -44,7 +44,6 @@ #define FAN_SPEED_5625 0 - struct fan_speed { u8 fan_in; u16 fan_speed; @@ -53,10 +52,10 @@ /* FANIN Target Speed Register */ /* FANIN = 337500 / RPM */ struct fan_speed fan_speeds[] = { - { 0x3c, 5625 }, { 0x41, 5192 }, { 0x47, 4753 }, { 0x4e, 4326 }, - { 0x56, 3924 }, { 0x5f, 3552 }, { 0x69, 3214 }, { 0x74, 2909 }, - { 0x80, 2636 }, { 0x8d, 2393 }, { 0x9b, 2177 }, { 0xaa, 1985 }, - { 0xba, 1814 }, { 0xcb, 1662 }, { 0xdd, 1527 }, { 0xf0, 1406 } + {0x3c, 5625}, {0x41, 5192}, {0x47, 4753}, {0x4e, 4326}, + {0x56, 3924}, {0x5f, 3552}, {0x69, 3214}, {0x74, 2909}, + {0x80, 2636}, {0x8d, 2393}, {0x9b, 2177}, {0xaa, 1985}, + {0xba, 1814}, {0xcb, 1662}, {0xdd, 1527}, {0xf0, 1406} }; struct temperature { @@ -65,89 +64,108 @@ }; struct temperature temperatures[] = { - { 30, 86 }, { 33, 91 }, { 36, 96 }, { 39, 102 }, - { 42, 107 }, { 45, 113 }, { 48, 118 }, { 51, 123 }, - { 54, 129 }, { 57, 134 }, { 60, 140 }, { 63, 145 }, - { 66, 150 }, { 69, 156 }, { 72, 161 }, { 75, 167 } + {30, 86}, {33, 91}, {36, 96}, {39, 102}, + {42, 107}, {45, 113}, {48, 118}, {51, 123}, + {54, 129}, {57, 134}, {60, 140}, {63, 145}, + {66, 150}, {69, 156}, {72, 161}, {75, 167} }; static void hwm_setup(void) { - int cpufan_control = 0, sysfan_control = 0; - int cpufan_speed = 0, sysfan_speed = 0; - int cpufan_temperature = 0, sysfan_temperature = 0; + int cpufan_control = FAN_CRUISE_CONTROL_DISABLED; + int cpufan_speed = FAN_SPEED_5625; + int cpufan_temperature = 0; + int cpufan_temperature = 0; - cpufan_control = FAN_CRUISE_CONTROL_DISABLED; + int sysfan_control = FAN_CRUISE_CONTROL_DISABLED; + int sysfan_speed = FAN_SPEED_5625; + int sysfan_temperature = 0; + get_option(&cpufan_control, "cpufan_cruise_control"); - cpufan_speed = FAN_SPEED_5625; get_option(&cpufan_speed, "cpufan_speed"); - sysfan_control = FAN_CRUISE_CONTROL_DISABLED; get_option(&sysfan_control, "sysfan_cruise_control"); - sysfan_speed = FAN_SPEED_5625; get_option(&sysfan_speed, "sysfan_speed"); hwm_bank(0); - hwm_write(0x59, 0x20); /* Diode Selection */ - hwm_write(0x5d, 0x0f); /* All Sensors Diode, not Thermistor */ + hwm_write(0x59, 0x20); /* Diode Selection */ + hwm_write(0x5d, 0x0f); /* All Sensors Diode, not Thermistor */ hwm_bank(4); - hwm_write(0x54, 0xf1); /* SYSTIN temperature offset */ - hwm_write(0x55, 0x19); /* CPUTIN temperature offset */ - hwm_write(0x56, 0xfc); /* AUXTIN temperature offset */ + hwm_write(0x54, 0xf1); /* SYSTIN temperature offset */ + hwm_write(0x55, 0x19); /* CPUTIN temperature offset */ + hwm_write(0x56, 0xfc); /* AUXTIN temperature offset */ - hwm_bank(0x80); /* Default */ + hwm_bank(0x80); /* Default */ u8 fan_config = 0; /* 00 FANOUT is Manual Mode */ /* 01 FANOUT is Thermal Cruise Mode */ /* 10 FANOUT is Fan Speed Cruise Mode */ switch (cpufan_control) { - case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 4); break; - case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 4); break; + case FAN_CRUISE_CONTROL_SPEED: + fan_config |= (2 << 4); + break; + case FAN_CRUISE_CONTROL_THERMAL: + fan_config |= (1 << 4); + break; } switch (sysfan_control) { - case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 2); break; - case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 2); break; + case FAN_CRUISE_CONTROL_SPEED: + fan_config |= (2 << 2); + break; + case FAN_CRUISE_CONTROL_THERMAL: + fan_config |= (1 << 2); + break; } /* This register must be written first */ hwm_write(0x04, fan_config); switch (cpufan_control) { case FAN_CRUISE_CONTROL_SPEED: - printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to %d RPM\n", - fan_speeds[cpufan_speed].fan_speed); - hwm_write(0x06, fan_speeds[cpufan_speed].fan_in); /* CPUFANIN target speed */ + printk(BIOS_DEBUG, + "Fan Cruise Control setting CPU fan to %d RPM\n", + fan_speeds[cpufan_speed].fan_speed); + /* CPUFANIN target speed */ + hwm_write(0x06, fan_speeds[cpufan_speed].fan_in); break; case FAN_CRUISE_CONTROL_THERMAL: - printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to activation at %d deg C/%d deg F\n", - temperatures[cpufan_temperature].deg_celsius, - temperatures[cpufan_temperature].deg_fahrenheit); - hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius); /* CPUFANIN target temperature */ + printk(BIOS_DEBUG, + "Fan Cruise Control setting CPU fan to activation " + "at %d deg C/%d deg F\n", + temperatures[cpufan_temperature].deg_celsius, + temperatures[cpufan_temperature].deg_fahrenheit); + /* CPUFANIN target temperature */ + hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius); break; } switch (sysfan_control) { case FAN_CRUISE_CONTROL_SPEED: - printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to %d RPM\n", - fan_speeds[sysfan_speed].fan_speed); - hwm_write(0x05, fan_speeds[sysfan_speed].fan_in); /* SYSFANIN target speed */ + printk(BIOS_DEBUG, + "Fan Cruise Control setting system fan to %d RPM\n", + fan_speeds[sysfan_speed].fan_speed); + /* SYSFANIN target speed */ + hwm_write(0x05, fan_speeds[sysfan_speed].fan_in); break; case FAN_CRUISE_CONTROL_THERMAL: - printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to activation at %d deg C/%d deg F\n", - temperatures[sysfan_temperature].deg_celsius, - temperatures[sysfan_temperature].deg_fahrenheit); - hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); /* SYSFANIN target temperature */ + printk(BIOS_DEBUG, + "Fan Cruise Control setting system fan to activation " + "at %d deg C/%d deg F\n", + temperatures[sysfan_temperature].deg_celsius, + temperatures[sysfan_temperature].deg_fahrenheit); + /* SYSFANIN target temperature */ + hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); break; } - hwm_write(0x0e, 0x02); /* Fan Output Step Down Time */ - hwm_write(0x0f, 0x02); /* Fan Output Step Up Time */ + hwm_write(0x0e, 0x02); /* Fan Output Step Down Time */ + hwm_write(0x0f, 0x02); /* Fan Output Step Up Time */ - hwm_write(0x47, 0xaf); /* FAN divisor register */ - hwm_write(0x4b, 0x84); /* AUXFANIN speed divisor */ + hwm_write(0x47, 0xaf); /* FAN divisor register */ + hwm_write(0x4b, 0x84); /* AUXFANIN speed divisor */ - hwm_write(0x40, 0x01); /* Init, but no SMI# */ + hwm_write(0x40, 0x01); /* Init, but no SMI# */ } /* mainboard_enable is executed as first thing after */ @@ -155,7 +173,9 @@ static void mainboard_enable(struct device *dev) { - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 3); + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 3); hwm_setup(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/31155 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96a1d480c8b618a184c2b5ae08380f45fbd628ec Gerrit-Change-Number: 31155 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/common/block/pcr: Remove unneeded white space before '\t'
by HAOUAS Elyes (Code Review) 18 Apr '19

18 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30818 Change subject: soc/intel/common/block/pcr: Remove unneeded white space before '\t' ...................................................................... soc/intel/common/block/pcr: Remove unneeded white space before '\t' Change-Id: If39d9d23acbb37068584caebe93756f7a9ffeaaa Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/common/block/pcr/pcr.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/30818/1 diff --git a/src/soc/intel/common/block/pcr/pcr.c b/src/soc/intel/common/block/pcr/pcr.c index 804ccff..17d7d20 100644 --- a/src/soc/intel/common/block/pcr/pcr.c +++ b/src/soc/intel/common/block/pcr/pcr.c @@ -269,7 +269,7 @@ if (!msg || !data || !response) { printk(BIOS_ERR, "Pointer checked for NULL Fail! " - "msg = %p \t data = %p \t response = %p\n", + "msg = %p\t data = %p\t response = %p\n", msg, data, response); return -1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/30818 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If39d9d23acbb37068584caebe93756f7a9ffeaaa Gerrit-Change-Number: 30818 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/ibase/mb899: Set HD Audio to off
by HAOUAS Elyes (Code Review) 18 Apr '19

18 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30892 Change subject: mb/ibase/mb899: Set HD Audio to off ...................................................................... mb/ibase/mb899: Set HD Audio to off As AC'97 audio is ON in devicetree, HD audio should be OFF Change-Id: I22af68ab92f76bf3ddcea10faa40a3c6fd934c04 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/ibase/mb899/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/30892/1 diff --git a/src/mainboard/ibase/mb899/devicetree.cb b/src/mainboard/ibase/mb899/devicetree.cb index 3544c96..05f48d8 100644 --- a/src/mainboard/ibase/mb899/devicetree.cb +++ b/src/mainboard/ibase/mb899/devicetree.cb @@ -41,7 +41,7 @@ register "c3_latency" = "85" register "p_cnt_throttling_supported" = "0" - #device pci 1b.0 on end # High Definition Audio + device pci 1b.0 off end # High Definition Audio device pci 1c.0 on end # PCIe device pci 1c.1 on end # PCIe device pci 1c.2 on end # PCIe -- To view, visit https://review.coreboot.org/c/coreboot/+/30892 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22af68ab92f76bf3ddcea10faa40a3c6fd934c04 Gerrit-Change-Number: 30892 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/packardbell/ms2290/acpi: Update _OSI strings and OSYS values
by HAOUAS Elyes (Code Review) 18 Apr '19

18 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30468 Change subject: mb/packardbell/ms2290/acpi: Update _OSI strings and OSYS values ...................................................................... mb/packardbell/ms2290/acpi: Update _OSI strings and OSYS values Change-Id: I3f5ee4d68c96e8ee0d964c62edebfcfa37fd1c45 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/packardbell/ms2290/acpi/platform.asl 1 file changed, 67 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/30468/1 diff --git a/src/mainboard/packardbell/ms2290/acpi/platform.asl b/src/mainboard/packardbell/ms2290/acpi/platform.asl index 9812d14..e3f95ed 100644 --- a/src/mainboard/packardbell/ms2290/acpi/platform.asl +++ b/src/mainboard/packardbell/ms2290/acpi/platform.asl @@ -90,51 +90,101 @@ * 2001 | Windows XP(+SP1) * 2002 | Windows XP SP2 * 2006 | Windows Vista - * ???? | Windows 7 + * 2009 | Windows 7 + * 2012 | Windows 8 + * 2013 | Windows 8.1 + * 2015 | Windows 10 + * 2016 | Windows 10, version 1607 + * 2017 | Windows 10, version 1703 + * 2017.2 | Windows 10, version 1709 + * 2018 | Windows 10, version 1803 + * 2018.2 | Windows 10, version 1809 */ /* Let's assume we're running at least Windows 2000 */ Store (2000, OSYS) If (CondRefOf(_OSI)) { + /* Linux answers _OSI with "True" for a couple of + * Windows version queries. But unlike Windows it + * needs a Video repost, so let's determine whether + * we're running Linux. + */ + + If (_OSI("Linux")) { + Store (1, LINX) + } + + If (_OSI("Windows 2000")) { + Store (0x07D0, OSYS) + } + If (_OSI("Windows 2001")) { - Store (2001, OSYS) + Store (0x07D1, OSYS) } If (_OSI("Windows 2001 SP1")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2001 SP2")) { - Store (2002, OSYS) + Store (0x07D1, OSYS) } If (_OSI("Windows 2001.1")) { - Store (2001, OSYS) + Store (0x07D1, OSYS) + } + + If (_OSI("Windows 2001 SP2")) { + Store (0x07D1, OSYS) } If (_OSI("Windows 2001.1 SP1")) { - Store (2001, OSYS) + Store (0x07D1, OSYS) } If (_OSI("Windows 2006")) { - Store (2006, OSYS) - } - - If (_OSI("Windows 2006.1")) { - Store (2006, OSYS) + Store (0x07D6, OSYS) } If (_OSI("Windows 2006 SP1")) { - Store (2006, OSYS) + Store (0x07D6, OSYS) + } + + If (_OSI("Windows 2006.1")) { + Store (0x07D6, OSYS) } If (_OSI("Windows 2009")) { - Store (2009, OSYS) + Store (0x07D9, OSYS) } If (_OSI("Windows 2012")) { - Store (2012, OSYS) + Store (0x07DC, OSYS) + } + + If (_OSI("Windows 2013")) { + Store (0x07DD, OSYS) + } + + If (_OSI("Windows 2015")) { + Store (0x07DF, OSYS) + } + + If (_OSI("Windows 2016")) { + Store (0x07E0, OSYS) + } + + If (_OSI("Windows 2017")) { + Store (0x07E1, OSYS) + } + + If (_OSI("Windows 2017.2")) { + Store (0x07E1, OSYS) + } + + If (_OSI("Windows 2018")) { + Store (0x07E2, OSYS) + } + + If (_OSI("Windows 2018.2")) { + Store (0x07E2, OSYS) } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/30468 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f5ee4d68c96e8ee0d964c62edebfcfa37fd1c45 Gerrit-Change-Number: 30468 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/lenovo/x201/acpi: Update _OSI strings and OSYS values
by HAOUAS Elyes (Code Review) 18 Apr '19

18 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30469 Change subject: mb/lenovo/x201/acpi: Update _OSI strings and OSYS values ...................................................................... mb/lenovo/x201/acpi: Update _OSI strings and OSYS values Change-Id: I503bd92f2a1fa56e3f97c8090431abe92a51fd0e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/lenovo/x201/acpi/platform.asl 1 file changed, 68 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/30469/1 diff --git a/src/mainboard/lenovo/x201/acpi/platform.asl b/src/mainboard/lenovo/x201/acpi/platform.asl index 7d7013b..1f55624 100644 --- a/src/mainboard/lenovo/x201/acpi/platform.asl +++ b/src/mainboard/lenovo/x201/acpi/platform.asl @@ -111,52 +111,103 @@ * 2001 | Windows XP(+SP1) * 2002 | Windows XP SP2 * 2006 | Windows Vista - * ???? | Windows 7 + * 2009 | Windows 7 + * 2012 | Windows 8 + * 2013 | Windows 8.1 + * 2015 | Windows 10 + * 2016 | Windows 10, version 1607 + * 2017 | Windows 10, version 1703 + * 2017.2 | Windows 10, version 1709 + * 2018 | Windows 10, version 1803 + * 2018.2 | Windows 10, version 1809 */ /* Let's assume we're running at least Windows 2000 */ Store (2000, OSYS) If (CondRefOf(_OSI)) { + /* Linux answers _OSI with "True" for a couple of + * Windows version queries. But unlike Windows it + * needs a Video repost, so let's determine whether + * we're running Linux. + */ + + If (_OSI("Linux")) { + Store (1, LINX) + } + + If (_OSI("Windows 2000")) { + Store (0x07D0, OSYS) + } + If (_OSI("Windows 2001")) { - Store (2001, OSYS) + Store (0x07D1, OSYS) } If (_OSI("Windows 2001 SP1")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2001 SP2")) { - Store (2002, OSYS) + Store (0x07D1, OSYS) } If (_OSI("Windows 2001.1")) { - Store (2001, OSYS) + Store (0x07D1, OSYS) + } + + If (_OSI("Windows 2001 SP2")) { + Store (0x07D1, OSYS) } If (_OSI("Windows 2001.1 SP1")) { - Store (2001, OSYS) + Store (0x07D1, OSYS) } If (_OSI("Windows 2006")) { - Store (2006, OSYS) - } - - If (_OSI("Windows 2006.1")) { - Store (2006, OSYS) + Store (0x07D6, OSYS) } If (_OSI("Windows 2006 SP1")) { - Store (2006, OSYS) + Store (0x07D6, OSYS) + } + + If (_OSI("Windows 2006.1")) { + Store (0x07D6, OSYS) } If (_OSI("Windows 2009")) { - Store (2009, OSYS) + Store (0x07D9, OSYS) } If (_OSI("Windows 2012")) { - Store (2012, OSYS) + Store (0x07DC, OSYS) } + + If (_OSI("Windows 2013")) { + Store (0x07DD, OSYS) + } + + If (_OSI("Windows 2015")) { + Store (0x07DF, OSYS) + } + + If (_OSI("Windows 2016")) { + Store (0x07E0, OSYS) + } + + If (_OSI("Windows 2017")) { + Store (0x07E1, OSYS) + } + + If (_OSI("Windows 2017.2")) { + Store (0x07E1, OSYS) + } + + If (_OSI("Windows 2018")) { + Store (0x07E2, OSYS) + } + + If (_OSI("Windows 2018.2")) { + Store (0x07E2, OSYS) + } + } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/30469 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I503bd92f2a1fa56e3f97c8090431abe92a51fd0e Gerrit-Change-Number: 30469 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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coreboot-gerrit January 2019