Change in ...coreboot[master]: mediatek/mt8183: Support gpio eh and rsel setting for I2C

[wang qii (Code Review)]

wang qii has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30974

Change subject: mediatek/mt8183: Support gpio eh and rsel setting for I2C
......................................................................

mediatek/mt8183: Support gpio eh and rsel setting for I2C

The setting of these registers are only for i2c pin.

BUG=b:80501386
BRANCH=none
TEST=Boot correctly on Kukui

Change-Id: I518ca07645fe55aa55e94e4f98178baa0b74a882
Signed-off-by: jg_poxu 
---
M src/soc/mediatek/mt8183/gpio.c
M src/soc/mediatek/mt8183/include/soc/gpio.h
2 files changed, 67 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/30974/1

diff --git a/src/soc/mediatek/mt8183/gpio.c b/src/soc/mediatek/mt8183/gpio.c
index d555c33..c87509a 100644
--- a/src/soc/mediatek/mt8183/gpio.c
+++ b/src/soc/mediatek/mt8183/gpio.c
@@ -15,10 +15,12 @@

#include <arch/io.h>
 #include <gpio.h>
+#include <assert.h>

enum {
    EN_OFFSET = 0x60,
    SEL_OFFSET = 0x80,
+	EH_RSEL_OFFSET = 0xF0,
 };

static void gpio_set_pull_pupd(gpio_t gpio, enum pull_enable enable,
@@ -67,3 +69,66 @@
    else
    	gpio_set_pull_en_sel(gpio, enable, select);
 }
+
+struct i2c_pin_spec {
+	uint16_t id;
+	uint8_t eh_bit;
+	uint8_t rsel_bit;
+};
+
+#define MTK_I2C_PIN_SPEC(pad_id, eh, rsel)	\
+	{					\
+		.id = pad_id,			\
+		.eh_bit = eh,			\
+		.rsel_bit = rsel,		\
+	}
+
+static const struct i2c_pin_spec i2c_pin_spec_list[] = {
+	MTK_I2C_PIN_SPEC(PAD_SCL5_ID, 20, 18),
+	MTK_I2C_PIN_SPEC(PAD_SDA5_ID, 15, 13),
+	MTK_I2C_PIN_SPEC(PAD_SCL3_ID, 12, 10),
+	MTK_I2C_PIN_SPEC(PAD_SDA3_ID, 7, 5),
+	MTK_I2C_PIN_SPEC(PAD_SDA1_ID, 12, 7),
+	MTK_I2C_PIN_SPEC(PAD_SDA0_ID, 9, 5),
+	MTK_I2C_PIN_SPEC(PAD_SCL0_ID, 19, 15),
+	MTK_I2C_PIN_SPEC(PAD_SCL1_ID, 22, 17),
+	MTK_I2C_PIN_SPEC(PAD_SCL2_ID, 24, 20),
+	MTK_I2C_PIN_SPEC(PAD_SDA2_ID, 14, 10),
+	MTK_I2C_PIN_SPEC(PAD_SCL4_ID, 27, 22),
+	MTK_I2C_PIN_SPEC(PAD_SDA4_ID, 17, 12),
+};
+
+static const struct i2c_pin_spec *get_i2c_pin_spec(gpio_t gpio)
+{
+	size_t i;
+
+	for (i = 0; i < ARRAY_SIZE(i2c_pin_spec_list); i++)
+		if (gpio.id == i2c_pin_spec_list[i].id)
+			return &i2c_pin_spec_list[i];
+
+	return NULL;
+}
+
+void gpio_set_i2c_eh(gpio_t gpio, uint32_t select)
+{
+	void *reg = GPIO_TO_IOCFG_BASE(gpio.base) + EH_RSEL_OFFSET;
+	uint8_t bit;
+	const struct i2c_pin_spec *pin = get_i2c_pin_spec(gpio);
+
+	assert(pin);
+	assert(select < 8);
+	bit = pin->eh_bit;
+	clrsetbits_le32(reg, 7 << bit, select << bit);
+}
+
+void gpio_set_i2c_rsel(gpio_t gpio, uint32_t select)
+{
+	void *reg = GPIO_TO_IOCFG_BASE(gpio.base) + EH_RSEL_OFFSET;
+	uint8_t bit;
+	const struct i2c_pin_spec *pin = get_i2c_pin_spec(gpio);
+
+	assert(pin);
+	assert(select < 4);
+	bit = pin->rsel_bit;
+	clrsetbits_le32(reg, 3 << bit, select << bit);
+}
diff --git a/src/soc/mediatek/mt8183/include/soc/gpio.h b/src/soc/mediatek/mt8183/include/soc/gpio.h
index c3c8dda..a3a972b 100644
--- a/src/soc/mediatek/mt8183/include/soc/gpio.h
+++ b/src/soc/mediatek/mt8183/include/soc/gpio.h
@@ -616,5 +616,6 @@
 check_member(gpio_regs, mode[22].val, 0x460);

static struct gpio_regs *const mtk_gpio = (void *)(GPIO_BASE);
-
+void gpio_set_i2c_eh(gpio_t gpio, uint32_t select);
+void gpio_set_i2c_rsel(gpio_t gpio, uint32_t select);
 #endif

[Julius Werner (Code Review)]

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30974 )

Change subject: mediatek/mt8183: Support gpio eh and rsel setting for I2C
......................................................................

Patch Set 1:

(2 comments)

https://review.coreboot.org/#/c/30974/1/src/soc/mediatek/mt8183/gpio.c 
File src/soc/mediatek/mt8183/gpio.c:

https://review.coreboot.org/#/c/30974/1/src/soc/mediatek/mt8183/gpio.c@87 
PS1, Line 87: 	MTK_I2C_PIN_SPEC(PAD_SCL5_ID, 20, 18),
nit: There's no need for this macro, if you want to initialize by position you can just write

{PAD_SDA5_ID, 15, 13}

(of course, initializing by position only is hard to read, so you really should write { .id = PAD_SDA5_ID, .eh_bit = 15, .rsel_bit = 13 } explicitly on every line).

https://review.coreboot.org/#/c/30974/1/src/soc/mediatek/mt8183/gpio.c@98 
PS1, Line 98: 	MTK_I2C_PIN_SPEC(PAD_SDA4_ID, 17, 12),
What do these numbers do and where do they come from? Are they specific to the board layout? Why didn't we need this on 8173?

[wang qii (Code Review)]

wang qii has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30974 )

Change subject: mediatek/mt8183: Support gpio eh and rsel setting for I2C
......................................................................

Patch Set 1:

(2 comments)

https://review.coreboot.org/#/c/30974/1/src/soc/mediatek/mt8183/gpio.c 
File src/soc/mediatek/mt8183/gpio.c:

https://review.coreboot.org/#/c/30974/1/src/soc/mediatek/mt8183/gpio.c@87 
PS1, Line 87: 	MTK_I2C_PIN_SPEC(PAD_SCL5_ID, 20, 18),
> nit: There's no need for this macro, if you want to initialize by position you can just write […]

ok,I will modify it.

https://review.coreboot.org/#/c/30974/1/src/soc/mediatek/mt8183/gpio.c@98 
PS1, Line 98: 	MTK_I2C_PIN_SPEC(PAD_SDA4_ID, 17, 12),
> What do these numbers do and where do they come from? Are they specific to the board layout? Why did […]

These pins are for specific adjustment of AC-timing in order to satisfy the i2c spec(3.4MHz). 8173 only needs to meet the speed requirement of 1MHz.

[wang qii (Code Review)]

Hello Julius Werner, You-Cheng Syu, Tristan Hsieh, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/30974

to look at the new patch set (#2).

Change subject: mediatek/mt8183: Support gpio eh and rsel setting for I2C
......................................................................

mediatek/mt8183: Support gpio eh and rsel setting for I2C

The setting of these registers are only for i2c pin.

BUG=b:80501386
BRANCH=none
TEST=Boot correctly on Kukui

Change-Id: I518ca07645fe55aa55e94e4f98178baa0b74a882
Signed-off-by: jg_poxu 
---
M src/soc/mediatek/mt8183/gpio.c
M src/soc/mediatek/mt8183/include/soc/gpio.h
2 files changed, 60 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/30974/2

[Julius Werner (Code Review)]

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30974 )

Change subject: mediatek/mt8183: Support gpio eh and rsel setting for I2C
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/#/c/30974/1/src/soc/mediatek/mt8183/gpio.c 
File src/soc/mediatek/mt8183/gpio.c:

https://review.coreboot.org/#/c/30974/1/src/soc/mediatek/mt8183/gpio.c@98 
PS1, Line 98: 	MTK_I2C_PIN_SPEC(PAD_SDA4_ID, 17, 12),
> These pins are for specific adjustment of AC-timing in order to satisfy the i2c spec(3.4MHz). […]

What I2C device are you driving at more than 1MHz in firmware? Note that if this is only necessary for devices that will only be used by the kernel, the kernel should do this initialization. The firmware should only initialize devices it actually needs to use itself.

[wang qii (Code Review)]

wang qii has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30974 )

Change subject: mediatek/mt8183: Support gpio eh and rsel setting for I2C
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/#/c/30974/1/src/soc/mediatek/mt8183/gpio.c 
File src/soc/mediatek/mt8183/gpio.c:

https://review.coreboot.org/#/c/30974/1/src/soc/mediatek/mt8183/gpio.c@98 
PS1, Line 98: 	MTK_I2C_PIN_SPEC(PAD_SDA4_ID, 17, 12),
> What I2C device are you driving at more than 1MHz in firmware? Note that if this is only necessary f […]

By default settings must be reset, otherwise the low level of i2c is too high.

[Julius Werner (Code Review)]

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30974 )

Change subject: mediatek/mt8183: Support gpio eh and rsel setting for I2C
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/#/c/30974/1/src/soc/mediatek/mt8183/gpio.c 
File src/soc/mediatek/mt8183/gpio.c:

https://review.coreboot.org/#/c/30974/1/src/soc/mediatek/mt8183/gpio.c@98 
PS1, Line 98: 	MTK_I2C_PIN_SPEC(PAD_SDA4_ID, 17, 12),
> By default settings must be reset, otherwise the low level of i2c is too high.

You didn't really answer my question. Are you saying that this must be done even to get lower frequencies than 3.4MHz working, or what?

[wang qii (Code Review)]

wang qii has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30974 )

Change subject: mediatek/mt8183: Support gpio eh and rsel setting for I2C
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/#/c/30974/1/src/soc/mediatek/mt8183/gpio.c 
File src/soc/mediatek/mt8183/gpio.c:

https://review.coreboot.org/#/c/30974/1/src/soc/mediatek/mt8183/gpio.c@98 
PS1, Line 98: 	MTK_I2C_PIN_SPEC(PAD_SDA4_ID, 17, 12),
> You didn't really answer my question. […]

Yes, if the default settings are not modified, i2c will not work under all speed conditions.

[Julius Werner (Code Review)]

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30974 )

Change subject: mediatek/mt8183: Support gpio eh and rsel setting for I2C
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/#/c/30974/2/src/soc/mediatek/mt8183/gpio.c 
File src/soc/mediatek/mt8183/gpio.c:

https://review.coreboot.org/#/c/30974/2/src/soc/mediatek/mt8183/gpio.c@107 
PS2, Line 107: 	void *reg = GPIO_TO_IOCFG_BASE(gpio.base) + EH_RSEL_OFFSET;
If I understand this right, there are a few EH_RSEL registers (one per IOCFG base) where all the EH values need to be set to 0 and all the RSEL values need to be set to 3. Your code doesn't allow for any other values atm.

So rather than building this table that you have to search through once for every pin, why don't you just have three write32()s somewhere that initialize every EH and RSEL value correctly once at the start of the bootblock? that would seem much simpler and require much less code.

[Julius Werner (Code Review)]

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30974 )

Change subject: mediatek/mt8183: Support gpio eh and rsel setting for I2C
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/#/c/30974/2/src/soc/mediatek/mt8183/gpio.c 
File src/soc/mediatek/mt8183/gpio.c:

https://review.coreboot.org/#/c/30974/2/src/soc/mediatek/mt8183/gpio.c@107 
PS2, Line 107: 	void *reg = GPIO_TO_IOCFG_BASE(gpio.base) + EH_RSEL_OFFSET;
> If I understand this right, there are a few EH_RSEL registers (one per IOCFG base) where all the EH  […]

Or is it important that only I2C bus pins get this setting, and pins that could be muxed to I2C but are doing something else on our board must not get it? Your code doesn't make any of this clear.

[wang qii (Code Review)]

wang qii has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30974 )

Change subject: mediatek/mt8183: Support gpio eh and rsel setting for I2C
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/#/c/30974/2/src/soc/mediatek/mt8183/gpio.c 
File src/soc/mediatek/mt8183/gpio.c:

https://review.coreboot.org/#/c/30974/2/src/soc/mediatek/mt8183/gpio.c@107 
PS2, Line 107: 	void *reg = GPIO_TO_IOCFG_BASE(gpio.base) + EH_RSEL_OFFSET;
> Or is it important that only I2C bus pins get this setting, and pins that could be muxed to I2C but  […]

This APIs is provided to facilitate adjustment of different boards and different speed specifications during the coreboot phase. If there is no HS mode (more than 1MHz) requirement, all the EH values can be set to 0 and all the RSEL values can be set to 3 at once.

[wang qii (Code Review)]

wang qii has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30974 )

Change subject: mediatek/mt8183: Support gpio eh and rsel setting for I2C
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/#/c/30974/2/src/soc/mediatek/mt8183/gpio.c 
File src/soc/mediatek/mt8183/gpio.c:

https://review.coreboot.org/#/c/30974/2/src/soc/mediatek/mt8183/gpio.c@107 
PS2, Line 107: 	void *reg = GPIO_TO_IOCFG_BASE(gpio.base) + EH_RSEL_OFFSET;
> This APIs is provided to facilitate adjustment of different boards and different speed specification […]

What is your brilliant opinion? Which way is better?

[Julius Werner (Code Review)]

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30974 )

Change subject: mediatek/mt8183: Support gpio eh and rsel setting for I2C
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/#/c/30974/2/src/soc/mediatek/mt8183/gpio.c 
File src/soc/mediatek/mt8183/gpio.c:

https://review.coreboot.org/#/c/30974/2/src/soc/mediatek/mt8183/gpio.c@107 
PS2, Line 107: 	void *reg = GPIO_TO_IOCFG_BASE(gpio.base) + EH_RSEL_OFFSET;
> What is your brilliant opinion? Which way is better?

Yes, since it seems like we don't need HS I2C for Kukui, please just hardcode all values to the defaults (0 and 3) for now. Let's not add all these complicated lookup tables until we need them.

[wang qii (Code Review)]

Hello Julius Werner, You-Cheng Syu, Tristan Hsieh, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/30974

to look at the new patch set (#3).

Change subject: mediatek/mt8183: Support gpio eh and rsel setting for I2C
......................................................................

mediatek/mt8183: Support gpio eh and rsel setting for I2C

The setting of these registers are only for i2c pin.

BUG=b:80501386
BRANCH=none
TEST=Boot correctly on Kukui

Change-Id: I518ca07645fe55aa55e94e4f98178baa0b74a882
Signed-off-by: jg_poxu 
---
M src/soc/mediatek/mt8183/gpio.c
M src/soc/mediatek/mt8183/include/soc/gpio.h
2 files changed, 60 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/30974/3

[wang qii (Code Review)]

Hello Julius Werner, You-Cheng Syu, Tristan Hsieh, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/30974

to look at the new patch set (#5).

Change subject: mediatek/mt8183: Support gpio eh and rsel setting for I2C
......................................................................

mediatek/mt8183: Support gpio eh and rsel setting for I2C

The setting of these registers are only for i2c pin.

BUG=b:80501386
BRANCH=none
TEST=Boot correctly on Kukui

Change-Id: I518ca07645fe55aa55e94e4f98178baa0b74a882
Signed-off-by: jg_poxu 
---
M src/soc/mediatek/mt8183/gpio.c
M src/soc/mediatek/mt8183/include/soc/gpio.h
2 files changed, 62 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/30974/5

[Julius Werner (Code Review)]

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30974 )

Change subject: mediatek/mt8183: Support gpio eh and rsel setting for I2C
......................................................................

Patch Set 5: Code-Review+2

(2 comments)

LGTM (although I can't see where you're using it from yet?)

https://review.coreboot.org/#/c/30974/5/src/soc/mediatek/mt8183/gpio.c 
File src/soc/mediatek/mt8183/gpio.c:

https://review.coreboot.org/#/c/30974/5/src/soc/mediatek/mt8183/gpio.c@77 
PS5, Line 77: SCL0_EH
nit: maybe call them SCL0_EH_SHIFT/SCL0_RSEL_SHIFT to be clearer about what this is?

https://review.coreboot.org/#/c/30974/5/src/soc/mediatek/mt8183/gpio.c@109 
PS5, Line 109: void gpio_set_i2c_eh_rsel(void)
Where are you calling this from? (I'd suggest bootblock_soc_init().)

[wang qii (Code Review)]

wang qii has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30974 )

Change subject: mediatek/mt8183: Support gpio eh and rsel setting for I2C
......................................................................

Patch Set 5:

(2 comments)

https://review.coreboot.org/#/c/30974/5/src/soc/mediatek/mt8183/gpio.c 
File src/soc/mediatek/mt8183/gpio.c:

https://review.coreboot.org/#/c/30974/5/src/soc/mediatek/mt8183/gpio.c@77 
PS5, Line 77: SCL0_EH
> nit: maybe call them SCL0_EH_SHIFT/SCL0_RSEL_SHIFT to be clearer about what this is?

We would like to use a simple name here. If you like that way, we will modify it.

https://review.coreboot.org/#/c/30974/5/src/soc/mediatek/mt8183/gpio.c@109 
PS5, Line 109: void gpio_set_i2c_eh_rsel(void)
> Where are you calling this from? (I'd suggest bootblock_soc_init(). […]

https://review.coreboot.org/c/coreboot/+/30976/7/src/soc/mediatek/mt8183/mt8...

[Julius Werner (Code Review)]

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30974 )

Change subject: mediatek/mt8183: Support gpio eh and rsel setting for I2C
......................................................................

Patch Set 5:

(2 comments)

https://review.coreboot.org/#/c/30974/5/src/soc/mediatek/mt8183/gpio.c 
File src/soc/mediatek/mt8183/gpio.c:

https://review.coreboot.org/#/c/30974/5/src/soc/mediatek/mt8183/gpio.c@77 
PS5, Line 77: SCL0_EH
> We would like to use a simple name here. If you like that way, we will modify it.

Sure, I don't care that much.

https://review.coreboot.org/#/c/30974/5/src/soc/mediatek/mt8183/gpio.c@109 
PS5, Line 109: void gpio_set_i2c_eh_rsel(void)
> https://review.coreboot.org/c/coreboot/+/30976/7/src/soc/mediatek/mt8183/mt8.... […]

Ah, okay... yeah, that works.

[Julius Werner (Code Review)]

Julius Werner has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30974 )

Change subject: mediatek/mt8183: Support gpio eh and rsel setting for I2C
......................................................................

mediatek/mt8183: Support gpio eh and rsel setting for I2C

The setting of these registers are only for i2c pin.

BUG=b:80501386
BRANCH=none
TEST=Boot correctly on Kukui

Change-Id: I518ca07645fe55aa55e94e4f98178baa0b74a882
Signed-off-by: jg_poxu 
Reviewed-on: https://review.coreboot.org/c/30974
Tested-by: build bot (Jenkins) 
Reviewed-by: Julius Werner 
---
M src/soc/mediatek/mt8183/gpio.c
M src/soc/mediatek/mt8183/include/soc/gpio.h
2 files changed, 62 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Julius Werner: Looks good to me, approved

diff --git a/src/soc/mediatek/mt8183/gpio.c b/src/soc/mediatek/mt8183/gpio.c
index d555c33..173bf5a 100644
--- a/src/soc/mediatek/mt8183/gpio.c
+++ b/src/soc/mediatek/mt8183/gpio.c
@@ -19,6 +19,7 @@
 enum {
    EN_OFFSET = 0x60,
    SEL_OFFSET = 0x80,
+	EH_RSEL_OFFSET = 0xF0,
 };

static void gpio_set_pull_pupd(gpio_t gpio, enum pull_enable enable,
@@ -67,3 +68,63 @@
    else
    	gpio_set_pull_en_sel(gpio, enable, select);
 }
+
+enum {
+	EH_VAL = 0x0,
+	RSEL_VAL = 0x3,
+	EH_MASK = 0x7,
+	RSEL_MASK = 0x3,
+	SCL0_EH = 19,
+	SCL0_RSEL = 15,
+	SDA0_EH = 9,
+	SDA0_RSEL = 5,
+	SCL1_EH = 22,
+	SCL1_RSEL = 17,
+	SDA1_EH = 12,
+	SDA1_RSEL = 7,
+	SCL2_EH = 24,
+	SCL2_RSEL = 20,
+	SDA2_EH = 14,
+	SDA2_RSEL = 10,
+	SCL3_EH = 12,
+	SCL3_RSEL = 10,
+	SDA3_EH = 7,
+	SDA3_RSEL = 5,
+	SCL4_EH = 27,
+	SCL4_RSEL = 22,
+	SDA4_EH = 17,
+	SDA4_RSEL = 12,
+	SCL5_EH = 20,
+	SCL5_RSEL = 18,
+	SDA5_EH = 15,
+	SDA5_RSEL = 13,
+};
+
+#define I2C_EH_RSL_MASK(name) \
+	(EH_MASK << name##_EH | RSEL_MASK << name##_RSEL)
+
+#define I2C_EH_RSL_VAL(name) \
+	(EH_VAL << name##_EH | RSEL_VAL << name##_RSEL)
+
+void gpio_set_i2c_eh_rsel(void)
+{
+	clrsetbits_le32((void *)IOCFG_RB_BASE + EH_RSEL_OFFSET,
+		I2C_EH_RSL_MASK(SCL0) | I2C_EH_RSL_MASK(SDA0) |
+		I2C_EH_RSL_MASK(SCL1) | I2C_EH_RSL_MASK(SDA1),
+		I2C_EH_RSL_VAL(SCL0) | I2C_EH_RSL_VAL(SDA0) |
+		I2C_EH_RSL_VAL(SCL1) | I2C_EH_RSL_VAL(SDA1));
+
+	clrsetbits_le32((void *)IOCFG_RM_BASE + EH_RSEL_OFFSET,
+		I2C_EH_RSL_MASK(SCL2) | I2C_EH_RSL_MASK(SDA2) |
+		I2C_EH_RSL_MASK(SCL4) | I2C_EH_RSL_MASK(SDA4),
+		I2C_EH_RSL_VAL(SCL2) | I2C_EH_RSL_VAL(SDA2) |
+		I2C_EH_RSL_VAL(SCL4) | I2C_EH_RSL_VAL(SDA4));
+
+	clrsetbits_le32((void *)IOCFG_BL_BASE + EH_RSEL_OFFSET,
+		I2C_EH_RSL_MASK(SCL3) | I2C_EH_RSL_MASK(SDA3),
+		I2C_EH_RSL_VAL(SCL3) | I2C_EH_RSL_VAL(SDA3));
+
+	clrsetbits_le32((void *)IOCFG_LB_BASE + EH_RSEL_OFFSET,
+		I2C_EH_RSL_MASK(SCL5) | I2C_EH_RSL_MASK(SDA5),
+		I2C_EH_RSL_VAL(SCL5) | I2C_EH_RSL_VAL(SDA5));
+}
diff --git a/src/soc/mediatek/mt8183/include/soc/gpio.h b/src/soc/mediatek/mt8183/include/soc/gpio.h
index c3c8dda..5a98953 100644
--- a/src/soc/mediatek/mt8183/include/soc/gpio.h
+++ b/src/soc/mediatek/mt8183/include/soc/gpio.h
@@ -616,5 +616,6 @@
 check_member(gpio_regs, mode[22].val, 0x460);

static struct gpio_regs *const mtk_gpio = (void *)(GPIO_BASE);
+void gpio_set_i2c_eh_rsel(void);

#endif