Change in ...coreboot[master]: [TEST_ONLY, DO_NOT_MERGE] mb/google/octopus: Create phasal variant - coreboot-gerrit

21 Jan 2019

Raymond Chung has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31023
Change subject: [TEST_ONLY, DO_NOT_MERGE] mb/google/octopus: Create phasal variant
......................................................................
[TEST_ONLY, DO_NOT_MERGE] mb/google/octopus: Create phasal variant
This creates a phasal variant for octopus. Nothing is set in the variant
files here; everything is picked up from baseboard.
BUG=b:None
TEST=None
Change-Id: Id2c26195d44a268df2aff64b224c4376f0e9059e
Signed-off-by: “raymondchung” <“raymondchung@ami.corp-partner.google.com”>
---
M src/mainboard/google/octopus/Kconfig
M src/mainboard/google/octopus/Kconfig.name
A src/mainboard/google/octopus/variants/phasal/Makefile.inc
A src/mainboard/google/octopus/variants/phasal/gpio.c
A src/mainboard/google/octopus/variants/phasal/include/variant/acpi/dptf.asl
A src/mainboard/google/octopus/variants/phasal/include/variant/ec.h
A src/mainboard/google/octopus/variants/phasal/include/variant/gpio.h
A src/mainboard/google/octopus/variants/phasal/overridetree.cb
A src/mainboard/google/octopus/variants/phasal/variant.c
9 files changed, 358 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/31023/1

diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig
index a237741..a62cd19 100644
--- a/src/mainboard/google/octopus/Kconfig
+++ b/src/mainboard/google/octopus/Kconfig
@@ -56,6 +56,7 @@
    default "meep" if BOARD_GOOGLE_MEEP
    default "ampton" if BOARD_GOOGLE_AMPTON
    default "casta" if BOARD_GOOGLE_CASTA
+	default "phasal" if BOARD_GOOGLE_PHASAL
    default "octopus" if BOARD_GOOGLE_OCTOPUS
config DEVICETREE
@@ -76,6 +77,7 @@
    default "Meep" if BOARD_GOOGLE_MEEP
    default "Ampton" if BOARD_GOOGLE_AMPTON
    default "Casta" if BOARD_GOOGLE_CASTA
+	default "Phasal" if BOARD_GOOGLE_PHASAL
    default "Octopus" if BOARD_GOOGLE_OCTOPUS
config MAINBOARD_FAMILY
@@ -93,6 +95,7 @@
    default "MEEP TEST 1118" if BOARD_GOOGLE_MEEP
    default "AMPTON TEST 1285" if BOARD_GOOGLE_AMPTON
    default "CASTA TEST 8105" if BOARD_GOOGLE_CASTA
+	default "PHASAL TEST 7167" if BOARD_GOOGLE_PHASAL
    default "OCTOPUS TEST 6859" if BOARD_GOOGLE_OCTOPUS
config MAX_CPUS
diff --git a/src/mainboard/google/octopus/Kconfig.name b/src/mainboard/google/octopus/Kconfig.name
index 498da36..71e5197 100644
--- a/src/mainboard/google/octopus/Kconfig.name
+++ b/src/mainboard/google/octopus/Kconfig.name
@@ -52,3 +52,9 @@
    select BASEBOARD_OCTOPUS_LAPTOP
    select BOARD_GOOGLE_BASEBOARD_OCTOPUS
    select NHLT_DA7219 if INCLUDE_NHLT_BLOBS
+
+config BOARD_GOOGLE_PHASAL
+	bool "->  Phasal"
+	select BASEBOARD_OCTOPUS_LAPTOP
+	select BOARD_GOOGLE_BASEBOARD_OCTOPUS
+	select NHLT_DA7219 if INCLUDE_NHLT_BLOBS
diff --git a/src/mainboard/google/octopus/variants/phasal/Makefile.inc b/src/mainboard/google/octopus/variants/phasal/Makefile.inc
new file mode 100644
index 0000000..d54ed40
--- /dev/null
+++ b/src/mainboard/google/octopus/variants/phasal/Makefile.inc
@@ -0,0 +1,4 @@
+bootblock-y += gpio.c
+
+ramstage-y += variant.c
+ramstage-y += gpio.c
diff --git a/src/mainboard/google/octopus/variants/phasal/gpio.c b/src/mainboard/google/octopus/variants/phasal/gpio.c
new file mode 100644
index 0000000..322b44b
--- /dev/null
+++ b/src/mainboard/google/octopus/variants/phasal/gpio.c
@@ -0,0 +1,86 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <boardid.h>
+#include <gpio.h>
+#include <soc/gpio.h>
+#include <ec/google/chromeec/ec.h>
+#include <console/console.h>
+
+#define SKU_UNKNOWN            0xFFFFFFFF
+
+static const struct pad_config default_override_table[] = {
+	PAD_NC(GPIO_52, UP_20K),
+	PAD_NC(GPIO_53, UP_20K),
+	PAD_NC(GPIO_67, UP_20K),
+	PAD_NC(GPIO_117, UP_20K),
+	PAD_NC(GPIO_143, UP_20K),
+
+	/* EN_PP3300_TOUCHSCREEN */
+	PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0,
+					DISPUPD),
+
+	PAD_NC(GPIO_161, DN_20K),
+
+	/* EN_PP3300_WLAN_L */
+	PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_178, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD),
+
+	PAD_NC(GPIO_213, DN_20K),
+	PAD_NC(GPIO_214, DN_20K),
+};
+
+static const struct pad_config sku1_default_override_table[] = {
+       /* disable I2C7 SCL and SDA */
+	PAD_NC(GPIO_114, UP_20K),     /* LPSS_I2C7_SDA */
+	PAD_NC(GPIO_115, UP_20K),     /* LPSS_I2C7_SCL */
+
+	PAD_NC(GPIO_52, UP_20K),
+	PAD_NC(GPIO_53, UP_20K),
+	PAD_NC(GPIO_67, UP_20K),
+	PAD_NC(GPIO_117, UP_20K),
+	PAD_NC(GPIO_143, UP_20K),
+
+	/* EN_PP3300_TOUCHSCREEN */
+	PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0,
+					DISPUPD),
+
+	PAD_NC(GPIO_161, DN_20K),
+
+	/* EN_PP3300_WLAN_L */
+	PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_178, 0, DEEP, NONE, Tx0RxDCRx0,
+					DISPUPD),
+
+	PAD_NC(GPIO_213, DN_20K),
+	PAD_NC(GPIO_214, DN_20K),
+};
+
+const struct pad_config *variant_override_gpio_table(size_t *num)
+{
+	const struct pad_config *c;
+	uint32_t sku_id = SKU_UNKNOWN;
+
+	google_chromeec_cbi_get_sku_id(&sku_id);
+	if (sku_id == 1) {
+		c = sku1_default_override_table;
+		*num = ARRAY_SIZE(sku1_default_override_table);
+	} else {
+		c = default_override_table;
+		*num = ARRAY_SIZE(default_override_table);
+	}
+
+	return c;
+}
diff --git a/src/mainboard/google/octopus/variants/phasal/include/variant/acpi/dptf.asl b/src/mainboard/google/octopus/variants/phasal/include/variant/acpi/dptf.asl
new file mode 100644
index 0000000..cc17d56
--- /dev/null
+++ b/src/mainboard/google/octopus/variants/phasal/include/variant/acpi/dptf.asl
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/acpi/dptf.asl>
diff --git a/src/mainboard/google/octopus/variants/phasal/include/variant/ec.h b/src/mainboard/google/octopus/variants/phasal/include/variant/ec.h
new file mode 100644
index 0000000..16f931b
--- /dev/null
+++ b/src/mainboard/google/octopus/variants/phasal/include/variant/ec.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_EC_H
+#define MAINBOARD_EC_H
+
+#include <baseboard/ec.h>
+
+#endif
diff --git a/src/mainboard/google/octopus/variants/phasal/include/variant/gpio.h b/src/mainboard/google/octopus/variants/phasal/include/variant/gpio.h
new file mode 100644
index 0000000..1fd1e11
--- /dev/null
+++ b/src/mainboard/google/octopus/variants/phasal/include/variant/gpio.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#include <baseboard/gpio.h>
+
+#endif /* MAINBOARD_GPIO_H */
diff --git a/src/mainboard/google/octopus/variants/phasal/overridetree.cb b/src/mainboard/google/octopus/variants/phasal/overridetree.cb
new file mode 100644
index 0000000..b131173
--- /dev/null
+++ b/src/mainboard/google/octopus/variants/phasal/overridetree.cb
@@ -0,0 +1,164 @@
+chip soc/intel/apollolake
+
+	# EMMC Tx CMD Delay
+	# Refer to EDS-Vol2-16.32.
+	# [14:8] steps of delay for DDR mode, each 125ps.
+	# [6:0] steps of delay for SDR mode, each 125ps.
+	register "emmc_tx_cmd_cntl" = "0x505"
+
+	# EMMC TX DATA Delay 1
+	# Refer to EDS-Vol2-16.33.
+	# [14:8] steps of delay for HS400, each 125ps.
+	# [6:0] steps of delay for SDR104/HS200, each 125ps.
+	register "emmc_tx_data_cntl1" = "0x0b0c"
+
+	# EMMC TX DATA Delay 2
+	# Refer to EDS-Vol2-16.34.
+	# [30:24] steps of delay for SDR50, each 125ps.
+	# [22:16] steps of delay for DDR50, each 125ps.
+	# [14:8] steps of delay for SDR25/HS50, each 125ps.
+	# [6:0] steps of delay for SDR12, each 125ps.
+	register "emmc_tx_data_cntl2" = "0x1c282929"
+
+	# EMMC RX CMD/DATA Delay 1
+	# Refer to EDS-Vol2-16.35.
+	# [30:24] steps of delay for SDR50, each 125ps.
+	# [22:16] steps of delay for DDR50, each 125ps.
+	# [14:8] steps of delay for SDR25/HS50, each 125ps.
+	# [6:0] steps of delay for SDR12, each 125ps.
+	register "emmc_rx_cmd_data_cntl1" = "0x00181b1b"
+
+	# EMMC RX CMD/DATA Delay 2
+	# Refer to EDS-Vol2-16.37.
+	# [17:16] stands for Rx Clock before Output Buffer
+	# [14:8] steps of delay for Auto Tuning Mode, each 125ps.
+	# [6:0] steps of delay for HS200, each 125ps.
+	register "emmc_rx_cmd_data_cntl2" = "0x10028"
+
+	# EMMC Rx Strobe Delay
+	# Refer to EDS-Vol2-16.36.
+	# [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps.
+	# [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps.
+	register "emmc_rx_strobe_cntl" = "0x0b0b"
+
+	# Intel Common SoC Config
+	#+-------------------+---------------------------+
+	#| Field             |  Value                    |
+	#+-------------------+---------------------------+
+	#| GSPI0             | cr50 TPM. Early init is   |
+	#|                   | required to set up a BAR  |
+	#|                   | for TPM communication     |
+	#|                   | before memory is up       |
+	#| I2C0              | Digitizer                 |
+	#| I2C5              | Audio                     |
+	#| I2C6              | Trackpad                  |
+	#| I2C7              | Touchscreen               |
+	#+-------------------+---------------------------+
+	register "common_soc_config" = "{
+		.gspi[0] = {
+			.speed_mhz = 1,
+			.early_init = 1,
+		},
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 66,
+			.fall_time_ns = 90,
+		},
+		.i2c[5] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 104,
+			.fall_time_ns = 52,
+		},
+		.i2c[6] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 66,
+			.fall_time_ns = 90,
+			.data_hold_time_ns = 350,
+		},
+		.i2c[7] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 76,
+			.fall_time_ns = 164,
+		},
+	}"
+
+	device domain 0 on
+		device pci 16.0 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""WCOM50C1""
+				register "generic.desc" = ""WCOM Digitizer""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_139_IRQ)"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)"
+				register "generic.reset_delay_ms" = "20"
+				register "generic.has_power_resource" = "1"
+				register "hid_desc_reg_offset" = "0x1"
+				device i2c 0x9 on end
+			end
+		end	# - I2C 0
+		device pci 17.1 on
+			chip drivers/i2c/da7219
+				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)"
+				register "btn_cfg" = "50"
+				register "mic_det_thr" = "500"
+				register "jack_ins_deb" = "20"
+				register "jack_det_rate" = ""32ms_64ms""
+				register "jack_rem_deb" = "1"
+				register "a_d_btn_thr" = "0xa"
+				register "d_b_btn_thr" = "0x16"
+				register "b_c_btn_thr" = "0x21"
+				register "c_mic_btn_thr" = "0x3e"
+				register "btn_avg" = "4"
+				register "adc_1bit_rpt" = "1"
+				register "micbias_lvl" = "2600"
+				register "mic_amp_in_sel" = ""diff""
+				device i2c 1a on end
+			end
+		end	# - I2C 5
+		device pci 17.2 on
+			chip drivers/i2c/generic
+				register "hid" = ""ELAN0000""
+				register "desc" = ""ELAN Touchpad""
+				register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)"
+				register "wake" = "GPE0_DW3_27"
+				register "probed" = "1"
+				device i2c 15 on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""PNP0C50""
+				register "generic.desc" = ""Synaptics Touchpad""
+				register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)"
+				register "generic.wake" = "GPE0_DW3_27"
+				register "generic.probed" = "1"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 0x2c on end
+			end
+		end	# - I2C 6
+		device pci 17.3 on
+			chip drivers/i2c/generic
+				register "hid" = ""ELAN0001""
+				register "desc" = ""ELAN Touchscreen""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)"
+				register "probed" = "1"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)"
+				register "reset_delay_ms" = "20"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)"
+				register "enable_delay_ms" = "1"
+				register "has_power_resource" = "1"
+				device i2c 10 on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""SYTS7817""
+				register "generic.desc" = ""Synaptics Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)"
+				register "generic.probed" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)"
+				register "generic.reset_delay_ms" = "45"
+				register "generic.has_power_resource" = "1"
+				register "generic.disable_gpio_export_in_crs" = "1"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 20 on end
+			end
+		end	# - I2C 7
+	end
+end
diff --git a/src/mainboard/google/octopus/variants/phasal/variant.c b/src/mainboard/google/octopus/variants/phasal/variant.c
new file mode 100644
index 0000000..22f4f71
--- /dev/null
+++ b/src/mainboard/google/octopus/variants/phasal/variant.c
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variants.h>
+#include <soc/pci_devs.h>
+#include <string.h>
+#include <ec/google/chromeec/ec.h>
+
+#define SKU_UNKNOWN     0xFFFFFFFF
+
+void variant_update_devtree(struct device *dev)
+{
+	uint32_t sku_id = SKU_UNKNOWN;
+	struct device *touchscreen_i2c_host;
+
+	touchscreen_i2c_host = pcidev_path_on_root(PCH_DEVFN_I2C7);
+
+	if (touchscreen_i2c_host == NULL)
+		return;
+
+	/* SKU ID 1 does not have a touchscreen device, hence disable it. */
+	google_chromeec_cbi_get_sku_id(&sku_id);
+	if (sku_id == 1)
+		touchscreen_i2c_host->enabled = 0;
+}
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Id2c26195d44a268df2aff64b224c4376f0e9059e
Gerrit-Change-Number: 31023
Gerrit-PatchSet: 1
Gerrit-Owner: Raymond Chung raymondchung@ami.corp-partner.google.com
Gerrit-MessageType: newchange



    