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Change subject: soc/intel/alderlake: Hook up FSP hyper-threading setting to option API
......................................................................
Patch Set 14: Code-Review+2
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Change subject: soc/intel/alderlake: provide a list of D-states to enter LPM
......................................................................
Patch Set 18:
(6 comments)
File src/soc/intel/alderlake/acpi.c:
https://review.coreboot.org/c/coreboot/+/63969/comment/82c6a953_41d29403
PS18, Line 183: // Index based on PCI_DEVFN() values
coreboot doesn't really use `//` style comments:
`/* Index based on PCI_DEVFN() values */`
https://review.coreboot.org/c/coreboot/+/63969/comment/afe4cedc_74ff9f52
PS18, Line 187:
nit: extra space
https://review.coreboot.org/c/coreboot/+/63969/comment/3033c9be_aab8faab
PS18, Line 247: if (!dev || !dev->enabled)
nit:
`if (!is_dev_enabled(dev))`
https://review.coreboot.org/c/coreboot/+/63969/comment/287569b7_d500e8f1
PS18, Line 255: int
nit:
`size_t`
https://review.coreboot.org/c/coreboot/+/63969/comment/527e7d11_0bee0d46
PS18, Line 269: uint8_t
any particular reason this is 8 bits? why not `unsigned int` ?
File src/soc/intel/common/block/acpi/pep.c:
https://review.coreboot.org/c/coreboot/+/63969/comment/a229dff3_7d5310b6
PS18, Line 77: lpi_get_constraints
suggestion:
rename this function now to
`soc_lpi_get_constraints()`
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Change subject: mb/google/deltaur: Remove mainboard from tree
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
Patchset:
PS1:
Thanks for cleaning up
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Change subject: [WIP,UNTESTED] soc/amd/common/include/espi: add more decode ranges
......................................................................
Patch Set 2:
(2 comments)
File src/soc/amd/common/block/include/amdblocks/espi.h:
https://review.coreboot.org/c/coreboot/+/64054/comment/99856408_245a94ae
PS1, Line 17: #define ESPI_GENERIC_IO_WIN_LOW_COUNT 4
: #define ESPI_GENERIC_IO_WIN_EXT_COUNT (3 * 4)
> i wonder if i really need those or if i should just provide the number of ranges by the ifdef below […]
Done
File src/soc/amd/common/block/lpc/espi_util.c:
https://review.coreboot.org/c/coreboot/+/64054/comment/9c20773f_9d783f4e
PS1, Line 77: ESPI_DECODE_MMIO_RANGE_EN
> ESPI_DECODE_MMIO_RANGE_EXT_EN
Done
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/64054
to look at the new patch set (#2).
Change subject: [WIP,UNTESTED] soc/amd/common/include/espi: add more decode ranges
......................................................................
[WIP,UNTESTED] soc/amd/common/include/espi: add more decode ranges
Sabrina has more eSPI decode ranges than Picasso or Cezanne. To support
these additional ranges, introduce a new Kconfig option
SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES that can be selected by
the SoCs that support the additional eSPI IO/MMIO decode ranges.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Ib761cdf201c35805d68cf5e8e462607ffd9fa017
---
M src/soc/amd/common/block/include/amdblocks/espi.h
M src/soc/amd/common/block/lpc/Kconfig
M src/soc/amd/common/block/lpc/espi_def.h
M src/soc/amd/common/block/lpc/espi_util.c
4 files changed, 95 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/64054/2
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Change subject: [WIP,UNTESTED] soc/amd/common/include/espi: add more decode ranges
......................................................................
Patch Set 1:
(1 comment)
File src/soc/amd/common/block/lpc/espi_util.c:
https://review.coreboot.org/c/coreboot/+/64054/comment/01e18aef_13c2d9a5
PS1, Line 77: ESPI_DECODE_MMIO_RANGE_EN
ESPI_DECODE_MMIO_RANGE_EXT_EN
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Change subject: mb/google/brask/variants/moli: disable ASPM on pcie_rp 6
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> Ack, I'd appreciate if you could share this information
Sure, I will share what I can, FYI I don't know anyone on the i225 team offhand , so I it may take some time to find the right people first 😄
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Change subject: drivers/intel/usb4: Add Type-C port device attachment check
......................................................................
Patch Set 8:
(1 comment)
File src/drivers/intel/usb4/retimer/retimer.c:
https://review.coreboot.org/c/coreboot/+/63848/comment/b5362fd4_ebb910dd
PS8, Line 71: acpigen_disable_tx_gpio(power_gpio);
> Ack. […]
Yes, -1 is returned here as required by fwupd in which fwupd has its logic to differentiate DA from NDA.
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Change subject: mb/google/brask/variants/moli: disable ASPM on pcie_rp 6
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
Patchset:
PS2:
> Let's get this in now to unblock development, but I've asked Intel for some clarification in the bug […]
Ack, I'd appreciate if you could share this information
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Change subject: mb/google/brask/variants/moli: disable ASPM on pcie_rp 6
......................................................................
Patch Set 2: Code-Review+2
(2 comments)
Patchset:
PS2:
> We also observed the same behavior on prodrive/atlas (ADL-P). […]
Interesting, the datasheet I can find for the i225 says it supports L0-L3 link states
PS2:
Let's get this in now to unblock development, but I've asked Intel for some clarification in the bug.
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