coreboot-gerrit May 2022

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Change in coreboot[master]: soc/intel/adl: Send EOP early in the boot sequence
by Angel Pons (Code Review) 04 May '22

04 May '22

Attention is currently required from: Maulik V Vaghela. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62272 ) Change subject: soc/intel/adl: Send EOP early in the boot sequence ...................................................................... Patch Set 11: (1 comment) Patchset: PS11: This seems to cause issues with the ME disable logic, as EOP is now sent before `me_disable` is checked. -- To view, visit https://review.coreboot.org/c/coreboot/+/62272 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9401d5e36ad43cdc0dfe947aabc82528d824df9b Gerrit-Change-Number: 62272 Gerrit-PatchSet: 11 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Comment-Date: Wed, 04 May 2022 21:01:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/adl: Send EOP early in the boot sequence
by Tim Crawford (Code Review) 04 May '22

04 May '22

Attention is currently required from: Maulik V Vaghela. Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62272 ) Change subject: soc/intel/adl: Send EOP early in the boot sequence ...................................................................... Patch Set 11: (1 comment) Patchset: PS11: This change causes disabling CSME on ADL to fail, because now the message is sent after EOP. -- To view, visit https://review.coreboot.org/c/coreboot/+/62272 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9401d5e36ad43cdc0dfe947aabc82528d824df9b Gerrit-Change-Number: 62272 Gerrit-PatchSet: 11 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Comment-Date: Wed, 04 May 2022 20:57:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: provide a list of D-states to enter LPM
by Tarun Tuli (Code Review) 04 May '22

04 May '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Angel Pons. Hello Lance Zhao, build bot (Jenkins), Subrata Banik, Matt DeVillier, Tim Wawrzynczak, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63969 to look at the new patch set (#19). Change subject: soc/intel/alderlake: provide a list of D-states to enter LPM ...................................................................... soc/intel/alderlake: provide a list of D-states to enter LPM Implement sub-function 1 (Get Device Constraints) of the Low Power S0 Idle Device-Specific Method (_DSM). This provides a way in which to describe various devices required D-states to enter LPM (S0ix). The information can be used to help in diagnostics and understanding of S0ix entry failure. This implementation adds support for ADL. Other SoC's could be ported to be included as well. If they aren't, they will default to the existing behavior of a single hardcoded device to ensure compatibility with Windows. TEST=Built and tested on brya by verifying SSDT contents Change-Id: Ibe46a0583c522a8adf0a015cd3a698f694482437 Signed-off-by: Tarun Tuli <taruntuli(a)google.com> --- M src/include/acpi/acpi.h M src/soc/intel/alderlake/acpi.c M src/soc/intel/common/block/acpi/pep.c 3 files changed, 177 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/63969/19 -- To view, visit https://review.coreboot.org/c/coreboot/+/63969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe46a0583c522a8adf0a015cd3a698f694482437 Gerrit-Change-Number: 63969 Gerrit-PatchSet: 19 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/mtl: Do initial Meteor Lake SoC commit till bootblock
by Tim Wawrzynczak (Code Review) 04 May '22

04 May '22

Attention is currently required from: Felix Singer, Jamie Ryu, Subrata Banik, Wonkyu Kim, Ethan Tsao, Ravishankar Sarawadi, Paul Menzel, Angel Pons, Raj Astekar. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62772 ) Change subject: soc/intel/mtl: Do initial Meteor Lake SoC commit till bootblock ...................................................................... Patch Set 13: (5 comments) File src/soc/intel/meteorlake/Kconfig: https://review.coreboot.org/c/coreboot/+/62772/comment/f45b244d_535bc228 PS13, Line 51: Platform FSP integration guide document Is this available yet? File src/soc/intel/meteorlake/bootblock/soc_die.c: https://review.coreboot.org/c/coreboot/+/62772/comment/208f7334_f0b394b4 PS13, Line 101: soc_die_early_iorange_init does this need to be public? File src/soc/intel/meteorlake/include/soc/iomap.h: https://review.coreboot.org/c/coreboot/+/62772/comment/dd345fcb_cd0e0cea PS13, Line 63: : #define IOE_PCR_ABOVE_4G_BASE_ADDR 0x3fff0000000 : #define IOE_P2SB_BAR IOE_PCR_ABOVE_4G_BASE_ADDR : #define IOE_P2SB_SIZE (256 * MiB) : : #define IOM_BASE_ADDR 0x3fff0aa0000 : #define IOM_BASE_SIZE 0x1600 : #define IOM_BASE_ADDR_MAX 0x3fff0aa15ff does coreboot need to access these MMIO ranges? File src/soc/intel/meteorlake/include/soc/pci_devs.h: https://review.coreboot.org/c/coreboot/+/62772/comment/31cf649a_8f43fdda PS13, Line 186: //#define PCH_DEV_SLOT_LPC PCI_DEV_SLOT_ESPI not needed? File src/soc/intel/meteorlake/include/soc/pcr_ids.h: https://review.coreboot.org/c/coreboot/+/62772/comment/f09d644f_0a4d4bb5 PS13, Line 5: /* nit: missing a blank line before `/*` -- To view, visit https://review.coreboot.org/c/coreboot/+/62772 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26479fcc3a3f9c6f8ebf5f198ab0809f0b4a2cc4 Gerrit-Change-Number: 62772 Gerrit-PatchSet: 13 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ethan Tsao <ethan.tsao(a)intel.corp-partner.google.com> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Wed, 04 May 2022 20:34:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Hook up FSP hyper-threading setting to option API
by Subrata Banik (Code Review) 04 May '22

04 May '22

Attention is currently required from: Felix Singer, Nico Huber, Michael Niewöhner. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60547 ) Change subject: soc/intel/alderlake: Hook up FSP hyper-threading setting to option API ...................................................................... Patch Set 14: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60547 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I520a936b4c3a8997ba2c6bea0126b3bbcc5d68ce Gerrit-Change-Number: 60547 Gerrit-PatchSet: 14 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Wed, 04 May 2022 20:23:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: provide a list of D-states to enter LPM
by Tim Wawrzynczak (Code Review) 04 May '22

04 May '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Angel Pons. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63969 ) Change subject: soc/intel/alderlake: provide a list of D-states to enter LPM ...................................................................... Patch Set 18: (6 comments) File src/soc/intel/alderlake/acpi.c: https://review.coreboot.org/c/coreboot/+/63969/comment/82c6a953_41d29403 PS18, Line 183: // Index based on PCI_DEVFN() values coreboot doesn't really use `//` style comments: `/* Index based on PCI_DEVFN() values */` https://review.coreboot.org/c/coreboot/+/63969/comment/afe4cedc_74ff9f52 PS18, Line 187: nit: extra space https://review.coreboot.org/c/coreboot/+/63969/comment/3033c9be_aab8faab PS18, Line 247: if (!dev || !dev->enabled) nit: `if (!is_dev_enabled(dev))` https://review.coreboot.org/c/coreboot/+/63969/comment/287569b7_d500e8f1 PS18, Line 255: int nit: `size_t` https://review.coreboot.org/c/coreboot/+/63969/comment/527e7d11_0bee0d46 PS18, Line 269: uint8_t any particular reason this is 8 bits? why not `unsigned int` ? File src/soc/intel/common/block/acpi/pep.c: https://review.coreboot.org/c/coreboot/+/63969/comment/a229dff3_7d5310b6 PS18, Line 77: lpi_get_constraints suggestion: rename this function now to `soc_lpi_get_constraints()` -- To view, visit https://review.coreboot.org/c/coreboot/+/63969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe46a0583c522a8adf0a015cd3a698f694482437 Gerrit-Change-Number: 63969 Gerrit-PatchSet: 18 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 04 May 2022 20:17:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/deltaur: Remove mainboard from tree
by Felix Singer (Code Review) 04 May '22

04 May '22

Attention is currently required from: Subrata Banik, Selma Bensaid, Tim Wawrzynczak, Nick Vaccaro. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64056 ) Change subject: mb/google/deltaur: Remove mainboard from tree ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: Thanks for cleaning up -- To view, visit https://review.coreboot.org/c/coreboot/+/64056 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb12a95ff56c3437cb88df8ef3f6ae115ad53446 Gerrit-Change-Number: 64056 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Wed, 04 May 2022 20:13:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP,UNTESTED] soc/amd/common/include/espi: add more decode ranges
by Felix Held (Code Review) 04 May '22

04 May '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64054 ) Change subject: [WIP,UNTESTED] soc/amd/common/include/espi: add more decode ranges ...................................................................... Patch Set 2: (2 comments) File src/soc/amd/common/block/include/amdblocks/espi.h: https://review.coreboot.org/c/coreboot/+/64054/comment/99856408_245a94ae PS1, Line 17: #define ESPI_GENERIC_IO_WIN_LOW_COUNT 4 : #define ESPI_GENERIC_IO_WIN_EXT_COUNT (3 * 4) > i wonder if i really need those or if i should just provide the number of ranges by the ifdef below […] Done File src/soc/amd/common/block/lpc/espi_util.c: https://review.coreboot.org/c/coreboot/+/64054/comment/9c20773f_9d783f4e PS1, Line 77: ESPI_DECODE_MMIO_RANGE_EN > ESPI_DECODE_MMIO_RANGE_EXT_EN Done -- To view, visit https://review.coreboot.org/c/coreboot/+/64054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib761cdf201c35805d68cf5e8e462607ffd9fa017 Gerrit-Change-Number: 64054 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Wed, 04 May 2022 19:52:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP,UNTESTED] soc/amd/common/include/espi: add more decode ranges
by Felix Held (Code Review) 04 May '22

04 May '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/64054 to look at the new patch set (#2). Change subject: [WIP,UNTESTED] soc/amd/common/include/espi: add more decode ranges ...................................................................... [WIP,UNTESTED] soc/amd/common/include/espi: add more decode ranges Sabrina has more eSPI decode ranges than Picasso or Cezanne. To support these additional ranges, introduce a new Kconfig option SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES that can be selected by the SoCs that support the additional eSPI IO/MMIO decode ranges. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ib761cdf201c35805d68cf5e8e462607ffd9fa017 --- M src/soc/amd/common/block/include/amdblocks/espi.h M src/soc/amd/common/block/lpc/Kconfig M src/soc/amd/common/block/lpc/espi_def.h M src/soc/amd/common/block/lpc/espi_util.c 4 files changed, 95 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/64054/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/64054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib761cdf201c35805d68cf5e8e462607ffd9fa017 Gerrit-Change-Number: 64054 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [WIP,UNTESTED] soc/amd/common/include/espi: add more decode ranges
by Felix Held (Code Review) 04 May '22

04 May '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64054 ) Change subject: [WIP,UNTESTED] soc/amd/common/include/espi: add more decode ranges ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/common/block/lpc/espi_util.c: https://review.coreboot.org/c/coreboot/+/64054/comment/01e18aef_13c2d9a5 PS1, Line 77: ESPI_DECODE_MMIO_RANGE_EN ESPI_DECODE_MMIO_RANGE_EXT_EN -- To view, visit https://review.coreboot.org/c/coreboot/+/64054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib761cdf201c35805d68cf5e8e462607ffd9fa017 Gerrit-Change-Number: 64054 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Wed, 04 May 2022 19:31:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit May 2022