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Change subject: soc/amd/common/include/espi: reduce visibility of IO/MMIO decode defines
......................................................................
Patch Set 2: Code-Review+1
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Change subject: soc/amd/common/include/espi: reduce visibility of IO/MMIO decode defines
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/64053/comment/f3b5999a_77eebf08
PS1, Line 9: ans
> typo?
fixed
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/64053
to look at the new patch set (#2).
Change subject: soc/amd/common/include/espi: reduce visibility of IO/MMIO decode defines
......................................................................
soc/amd/common/include/espi: reduce visibility of IO/MMIO decode defines
The eSPI decode range defines aren't and shouldn't be used directly from
outside of the common AMD eSPI code which provides functions to abstract
the register access, so move the defines from amdblocks/espi.h to
espi_def.h inside the common AMD LPC/eSPI support directory to limit the
visibility. The special I/O range decode bits need to stay in
amdblocks/espi.h since those are used in the devicetree. Also update the
indentation in espi_def.h so that the defines line up properly.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Ic4ea30a1a6f10e94d88bf3b29f86dee2da6b39b5
---
M src/soc/amd/common/block/include/amdblocks/espi.h
M src/soc/amd/common/block/lpc/espi_def.h
2 files changed, 63 insertions(+), 60 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/64053/2
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Change subject: soc/amd/common/include/espi: reduce visibility of IO/MMIO decode defines
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/intel/alderlake: Hook up FSP hyper-threading setting to option API
......................................................................
Patch Set 14:
(1 comment)
Patchset:
PS14:
> Tested disabling hyperthreading on google/redrix. […]
Awesome, thanks!
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Change subject: soc/amd/common/include/espi: generalize IO/MMIO decode range macros
......................................................................
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Change subject: soc/intel/tigerlake: Add enum for `DdiPortXConfig`
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Change subject: cpu/x86/mp_init.c: Add wait_finished_mp_run_on_all_cpus
......................................................................
Patch Set 4:
(1 comment)
File src/cpu/x86/mp_init.c:
https://review.coreboot.org/c/coreboot/+/63566/comment/84db8011_55f49f9f
PS4, Line 994: if (lcb.logical_cpu_number && (cur_cpu !=
: lcb.logical_cpu_number))
: continue;
> Here you'll skip clearing the busy bit. […]
+1
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