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Change subject: soc/intel/adl: Send EOP early in the boot sequence
......................................................................
Patch Set 11:
(1 comment)
Patchset:
PS11:
> This seems to cause issues with the ME disable logic, as EOP is now sent before `me_disable` is checked.
can you please help to understand this problem little better?
Are you seeing PMC IPC to disable HECI1 device is failing as EOP is send early ?
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Change subject: mb/google/brya/: Add PEG and initial Nvidia dGPU ASL support
......................................................................
Patch Set 6:
(1 comment)
File src/mainboard/google/brya/acpi/peg.asl:
https://review.coreboot.org/c/coreboot/+/62931/comment/a9826503_48240d5b
PS5, Line 7: 0xff
> I'd use 0x100
I changed it in my mind, but not in the file apparently 😋 fixed
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Hello build bot (Jenkins), Subrata Banik, Ivy Jian, Angel Pons, Eric Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/62931
to look at the new patch set (#7).
Change subject: mb/google/brya/: Add PEG and initial Nvidia dGPU ASL support
......................................................................
mb/google/brya/: Add PEG and initial Nvidia dGPU ASL support
Some brya variants will use a GN20 series Nvidia GPU, which requires
quite a bit of ACPI support code to be written for it. This patch
lands a decent bit of the initial code for it on the brya platform,
including:
1) PEG RTD3 methods
2) DGPU power operations (RTD3 and GCOFF, NVJT _DSM and other Methods)
3) NVOP _DSM method
There will be more support to come later, this is all written to
specifications from the Nvidia Software Design Guide for GN20.
BUG=b:214581763
TEST=build patch train
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Change-Id: Ifce1610210e9636e87dda4b55c8287334adfcc42
---
M src/mainboard/google/brya/Kconfig
A src/mainboard/google/brya/acpi/gpu_defines.h
A src/mainboard/google/brya/acpi/gpu_top.asl
A src/mainboard/google/brya/acpi/nvjt.asl
A src/mainboard/google/brya/acpi/nvop.asl
A src/mainboard/google/brya/acpi/peg.asl
A src/mainboard/google/brya/acpi/power.asl
A src/mainboard/google/brya/acpi/utility.asl
M src/mainboard/google/brya/dsdt.asl
9 files changed, 719 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/62931/7
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Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63969 )
Change subject: soc/intel/alderlake: provide a list of D-states to enter LPM
......................................................................
Patch Set 19:
(6 comments)
File src/soc/intel/alderlake/acpi.c:
https://review.coreboot.org/c/coreboot/+/63969/comment/8466beb9_483ff385
PS18, Line 183: // Index based on PCI_DEVFN() values
> coreboot doesn't really use `//` style comments: […]
Done
https://review.coreboot.org/c/coreboot/+/63969/comment/ff17f87e_318950a1
PS18, Line 187:
> nit: extra space
Done
https://review.coreboot.org/c/coreboot/+/63969/comment/ad1daae4_7cbbfc55
PS18, Line 247: if (!dev || !dev->enabled)
> nit: […]
Done
https://review.coreboot.org/c/coreboot/+/63969/comment/e9b9848c_626c2726
PS18, Line 255: int
> nit: […]
Done
https://review.coreboot.org/c/coreboot/+/63969/comment/08d8a2c3_983c04a0
PS18, Line 269: uint8_t
> any particular reason this is 8 bits? why not `unsigned int` ?
Done
File src/soc/intel/common/block/acpi/pep.c:
https://review.coreboot.org/c/coreboot/+/63969/comment/e96db403_b4fe3b5e
PS18, Line 77: lpi_get_constraints
> suggestion: […]
Done
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Change subject: mb/google/brya/var/agah: Add GPU power sequencing
......................................................................
Patch Set 8: Code-Review+2
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Change subject: mb/google/brya/: Add PEG and initial Nvidia dGPU ASL support
......................................................................
Patch Set 6:
(1 comment)
File src/mainboard/google/brya/acpi/peg.asl:
https://review.coreboot.org/c/coreboot/+/62931/comment/a83f47f2_7b5e6365
PS5, Line 7: 0xff
> I guess it could be 0xe3 to be precise, but you're right, 0xff seems off by one ;)
I'd use 0x100
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Change subject: soc/intel/adl: Send EOP early in the boot sequence
......................................................................
Patch Set 11:
(1 comment)
Patchset:
PS11:
This seems to cause issues with the ME disable logic, as EOP is now sent before `me_disable` is checked.
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Change subject: soc/intel/adl: Send EOP early in the boot sequence
......................................................................
Patch Set 11:
(1 comment)
Patchset:
PS11:
This change causes disabling CSME on ADL to fail, because now the message is sent after EOP.
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Hello Lance Zhao, build bot (Jenkins), Subrata Banik, Matt DeVillier, Tim Wawrzynczak, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63969
to look at the new patch set (#19).
Change subject: soc/intel/alderlake: provide a list of D-states to enter LPM
......................................................................
soc/intel/alderlake: provide a list of D-states to enter LPM
Implement sub-function 1 (Get Device Constraints)
of the Low Power S0 Idle Device-Specific Method (_DSM).
This provides a way in which to describe various devices required
D-states to enter LPM (S0ix). The information can be used to help
in diagnostics and understanding of S0ix entry failure.
This implementation adds support for ADL. Other SoC's could be
ported to be included as well. If they aren't, they will default
to the existing behavior of a single hardcoded device to ensure
compatibility with Windows.
TEST=Built and tested on brya by verifying SSDT contents
Change-Id: Ibe46a0583c522a8adf0a015cd3a698f694482437
Signed-off-by: Tarun Tuli <taruntuli(a)google.com>
---
M src/include/acpi/acpi.h
M src/soc/intel/alderlake/acpi.c
M src/soc/intel/common/block/acpi/pep.c
3 files changed, 177 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/63969/19
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