Change in coreboot[master]: sc7280: Add PCIe host controller driver

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Ravi Kumar Bokka, Nico Huber, Furquan Shaikh, Paul Menzel, Julius Werner, Prasad Malisetty, mturney mturney.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53902 )

Change subject: sc7280: Add PCIe host controller driver
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Patch Set 89:

(5 comments)

File src/soc/qualcomm/sc7280/include/soc/addressmap.h:

https://review.coreboot.org/c/coreboot/+/53902/comment/790b635c_d471bd20 
PS89, Line 78: 0x100000
I thought that it turned out this was actually 4K?

File src/soc/qualcomm/sc7280/pcie_host.c:

https://review.coreboot.org/c/coreboot/+/53902/comment/1039815a_fbfd05de 
PS89, Line 34: db
dbi

https://review.coreboot.org/c/coreboot/+/53902/comment/1029a818_5c625999 
PS89, Line 55: gpio_t perst;
what if there is more than one endpoint downstream of the RC? would they still always use the same PERST# GPIO?

https://review.coreboot.org/c/coreboot/+/53902/comment/f62ac335_79017604 
PS89, Line 110: static const struct qcom_qmp_phy_init_tbl sc7280_qmp_pcie_serdes_tbl[] = {
Are all of these static SERDES and PCIe RX/TX tables chipset specific, or possily board specific?

https://review.coreboot.org/c/coreboot/+/53902/comment/7794a962_57393036 
PS89, Line 424: mdelay(100);
              : 	gpio_set(perst, 1);
              : 	mdelay(50);
same here, I think it's up to the mainboard specific code to ensure these delays are met.