coreboot-gerrit May 2022

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Change in coreboot[master]: [WIP,UNTESTED] soc/amd/common/include/espi: add more decode ranges
by Felix Held (Code Review) 04 May '22

04 May '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64054 ) Change subject: [WIP,UNTESTED] soc/amd/common/include/espi: add more decode ranges ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/common/block/include/amdblocks/espi.h: https://review.coreboot.org/c/coreboot/+/64054/comment/8015910a_9e7a8632 PS1, Line 17: #define ESPI_GENERIC_IO_WIN_LOW_COUNT 4 : #define ESPI_GENERIC_IO_WIN_EXT_COUNT (3 * 4) i wonder if i really need those or if i should just provide the number of ranges by the ifdef below and use ESPI_DECODE_RANGE_TO_REG_GROUP in the code instead of checking if the index is < ESPI_GENERIC_IO_WIN_LOW_COUNT. mainly pushed this patch in its current form as RFC -- To view, visit https://review.coreboot.org/c/coreboot/+/64054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib761cdf201c35805d68cf5e8e462607ffd9fa017 Gerrit-Change-Number: 64054 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Wed, 04 May 2022 18:53:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Move FSP_HYPERTHREADING to common Intel Kconfig
by Tim Wawrzynczak (Code Review) 04 May '22

04 May '22

Attention is currently required from: Felix Singer, Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Christian Walter, Arthur Heymans, Michael Niewöhner, Tim Chu. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60543 ) Change subject: soc/intel/skylake: Move FSP_HYPERTHREADING to common Intel Kconfig ...................................................................... Patch Set 8: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/60543 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I892d48b488cbf828057f0e9be9edc4352c58bbe7 Gerrit-Change-Number: 60543 Gerrit-PatchSet: 8 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 04 May 2022 18:53:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Hook up FSP hyper-threading setting to option API
by Tim Wawrzynczak (Code Review) 04 May '22

04 May '22

Attention is currently required from: Felix Singer, Nico Huber, Michael Niewöhner. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60547 ) Change subject: soc/intel/alderlake: Hook up FSP hyper-threading setting to option API ...................................................................... Patch Set 14: Code-Review+2 (1 comment) Patchset: PS14: Tested disabling hyperthreading on google/redrix. When disabled, the core count went from 12 (4+8) to 10 (2+8) -- To view, visit https://review.coreboot.org/c/coreboot/+/60547 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I520a936b4c3a8997ba2c6bea0126b3bbcc5d68ce Gerrit-Change-Number: 60547 Gerrit-PatchSet: 14 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Wed, 04 May 2022 18:52:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/agah: Add GPU power sequencing
by Tim Wawrzynczak (Code Review) 04 May '22

04 May '22

Attention is currently required from: Ivy Jian, Angel Pons, Nick Vaccaro. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62384 ) Change subject: mb/google/brya/var/agah: Add GPU power sequencing ...................................................................... Patch Set 7: (2 comments) File src/mainboard/google/brya/variants/agah/variant.c: https://review.coreboot.org/c/coreboot/+/62384/comment/9c764039_3bb5c347 PS6, Line 47: > Why is this a tab? oops https://review.coreboot.org/c/coreboot/+/62384/comment/e5374d34_9034ac17 PS6, Line 119: gpu_powered_on = dgpu_power_sequence_on() == CB_SUCCESS; > `dgpu_power_sequence_on()` already sets `gpu_powered_on` d'oh! fixed -- To view, visit https://review.coreboot.org/c/coreboot/+/62384 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1072be12ef58af5859e2a2d19c4a9c1adc0b0f88 Gerrit-Change-Number: 62384 Gerrit-PatchSet: 7 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Wed, 04 May 2022 18:50:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/sabrina/Kconfig: select extended eSPI decode range support
by Felix Held (Code Review) 04 May '22

04 May '22

1 0

Change in coreboot[master]: [WIP,UNTESTED] soc/amd/common/include/espi: add more decode ranges
by Felix Held (Code Review) 04 May '22

04 May '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64054 ) Change subject: [WIP,UNTESTED] soc/amd/common/include/espi: add more decode ranges ...................................................................... [WIP,UNTESTED] soc/amd/common/include/espi: add more decode ranges Sabrina has more eSPI decode ranges than Picasso or Cezanne. To support these additional ranges, introduce a new Kconfig option SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES that can be selected by the SoCs that support the additional eSPI IO/MMIO decode ranges. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ib761cdf201c35805d68cf5e8e462607ffd9fa017 --- M src/soc/amd/common/block/include/amdblocks/espi.h M src/soc/amd/common/block/lpc/Kconfig M src/soc/amd/common/block/lpc/espi_def.h M src/soc/amd/common/block/lpc/espi_util.c 4 files changed, 103 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/64054/1 diff --git a/src/soc/amd/common/block/include/amdblocks/espi.h b/src/soc/amd/common/block/include/amdblocks/espi.h index 9717688..6c811e7 100644 --- a/src/soc/amd/common/block/include/amdblocks/espi.h +++ b/src/soc/amd/common/block/include/amdblocks/espi.h @@ -14,11 +14,23 @@ #define ESPI_DECODE_IO_0X60_0X64_EN (1 << 1) #define ESPI_DECODE_IO_0X2E_0X2F_EN (1 << 0) -#define ESPI_GENERIC_IO_WIN_COUNT 4 +#define ESPI_GENERIC_IO_WIN_LOW_COUNT 4 +#define ESPI_GENERIC_IO_WIN_EXT_COUNT (3 * 4) #define ESPI_GENERIC_IO_MAX_WIN_SIZE 0x100 -#define ESPI_GENERIC_MMIO_WIN_COUNT 4 +#define ESPI_GENERIC_MMIO_WIN_LOW_COUNT 4 +#define ESPI_GENERIC_MMIO_WIN_EXT_COUNT 1 #define ESPI_GENERIC_MMIO_MAX_WIN_SIZE 0x10000 +/* The extended IO/MMIO decode ranges are only available in SoCs that select + SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES */ +#if CONFIG(SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES) +#define ESPI_GENERIC_IO_WIN_TOTAL_COUNT (ESPI_GENERIC_IO_WIN_LOW_COUNT + ESPI_GENERIC_IO_WIN_EXT_COUNT) +#define ESPI_GENERIC_MMIO_WIN_TOTAL_COUNT (ESPI_GENERIC_MMIO_WIN_LOW_COUNT + ESPI_GENERIC_MMIO_WIN_EXT_COUNT) +#else +#define ESPI_GENERIC_IO_WIN_TOTAL_COUNT ESPI_GENERIC_IO_WIN_LOW_COUNT +#define ESPI_GENERIC_MMIO_WIN_TOTAL_COUNT ESPI_GENERIC_MMIO_WIN_LOW_COUNT +#endif + #define ESPI_SLAVE0_CONFIG 0x68 #define ESPI_CRC_CHECKING_EN (1 << 31) #define ESPI_ALERT_MODE (1 << 30) @@ -69,7 +81,7 @@ struct { uint16_t base; size_t size; - } generic_io_range[ESPI_GENERIC_IO_WIN_COUNT]; + } generic_io_range[ESPI_GENERIC_IO_WIN_TOTAL_COUNT]; /* Slave configuration parameters */ enum espi_io_mode io_mode; diff --git a/src/soc/amd/common/block/lpc/Kconfig b/src/soc/amd/common/block/lpc/Kconfig index b1db1bd..2de83a5 100644 --- a/src/soc/amd/common/block/lpc/Kconfig +++ b/src/soc/amd/common/block/lpc/Kconfig @@ -36,6 +36,13 @@ Select this option if platform supports eSPI using D14F3 configuration registers. +config SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES + bool + depends on SOC_AMD_COMMON_BLOCK_HAS_ESPI + help + Select this if the platform supports 16 instead of 4 eSPI IO decode + ranges and 5 instead of 4 eSPI MMIO decode ranges. + config SOC_AMD_COMMON_BLOCK_HAS_ESPI_ALERT_ENABLE bool depends on SOC_AMD_COMMON_BLOCK_HAS_ESPI diff --git a/src/soc/amd/common/block/lpc/espi_def.h b/src/soc/amd/common/block/lpc/espi_def.h index dc398a9..cec2054 100644 --- a/src/soc/amd/common/block/lpc/espi_def.h +++ b/src/soc/amd/common/block/lpc/espi_def.h @@ -41,6 +41,8 @@ #define ESPI_SW_RST (1 << 0) /* bits in ESPI_DECODE 0x40 */ +#define ESPI_DECODE_MMIO_RANGE_EXT_EN(range) (1 << (((range) & 3) + 28)) +#define ESPI_DECODE_IO_RANGE_EXT_EN(range) (1 << ((range) + 16)) #define ESPI_DECODE_MMIO_RANGE_EN(range) (1 << (((range) & 3) + 12)) #define ESPI_DECODE_IO_RANGE_EN(range) (1 << (((range) & 3) + 8)) @@ -64,6 +66,20 @@ #define ESPI_STATUS_WAIT_TIMEOUT (1 << 1) #define ESPI_STATUS_BUS_ERROR (1 << 0) +/* The extended IO/MMIO decode ranges are only available in SoCs that select + SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES */ +#define ESPI_IO_BASE_REG2 0x80 +#define ESPI_IO_BASE_REG3 0x84 +#define ESPI_IO_SIZE1 0x88 +#define ESPI_IO_BASE_REG4 0x8c +#define ESPI_IO_BASE_REG5 0x90 +#define ESPI_IO_SIZE2 0x94 +#define ESPI_IO_BASE_REG6 0xb0 +#define ESPI_IO_BASE_REG7 0xb4 +#define ESPI_IO_SIZE3 0xb8 +#define ESPI_MMIO_BASE_REG4 0xbc +#define ESPI_MMIO_SIZE_REG2 0xc0 + #define ESPI_RXVW_POLARITY 0xac #define ESPI_IO_RANGE_BASE_REG(base, range) ((base) + ((range) & 3) * 2) @@ -71,4 +87,8 @@ #define ESPI_MMIO_RANGE_BASE_REG(base, range) ((base) + ((range) & 3) * 4) #define ESPI_MMIO_RANGE_SIZE_REG(base, range) ((base) + ((range) & 3) * 2) +/* There are up to 4 I/O decode ranges per I/O decoda range register group */ +#define ESPI_DECODE_RANGE_TO_REG_GROUP(range) ((range) / 4) +#define ESPI_DECODE_RANGE_TO_REG_OFFSET(range) ((range) % 4) + #endif /* AMD_BLOCK_ESPI_DEF_H */ diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index a5f43f4..f2a3fe6 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -62,32 +62,80 @@ static inline uint32_t espi_decode_io_range_en_bit(unsigned int idx) { - return ESPI_DECODE_IO_RANGE_EN(idx); + if (idx < ESPI_GENERIC_IO_WIN_LOW_COUNT) { + return ESPI_DECODE_IO_RANGE_EN(idx); + } else { + return ESPI_DECODE_IO_RANGE_EXT_EN(idx - ESPI_GENERIC_IO_WIN_LOW_COUNT); + } } static inline uint32_t espi_decode_mmio_range_en_bit(unsigned int idx) { - return ESPI_DECODE_MMIO_RANGE_EN(idx); + if (idx < ESPI_GENERIC_MMIO_WIN_LOW_COUNT) { + return ESPI_DECODE_MMIO_RANGE_EN(idx); + } else { + return ESPI_DECODE_MMIO_RANGE_EN(idx - ESPI_GENERIC_MMIO_WIN_LOW_COUNT); + } } static inline unsigned int espi_io_range_base_reg(unsigned int idx) { - return ESPI_IO_RANGE_BASE_REG(ESPI_IO_BASE_REG0, idx); + unsigned int reg_base; + switch (ESPI_DECODE_RANGE_TO_REG_GROUP(idx)) { + case 0: + reg_base = ESPI_IO_BASE_REG0; + break; + case 1: + reg_base = ESPI_IO_BASE_REG2; + break; + case 2: + reg_base = ESPI_IO_BASE_REG4; + break; + default: /* case 3 */ + reg_base = ESPI_IO_BASE_REG6; + break; + } + return ESPI_IO_RANGE_BASE_REG(reg_base, ESPI_DECODE_RANGE_TO_REG_OFFSET(idx)); } static inline unsigned int espi_io_range_size_reg(unsigned int idx) { - return ESPI_IO_RANGE_SIZE_REG(ESPI_IO_SIZE0, idx); + unsigned int reg_base; + switch (ESPI_DECODE_RANGE_TO_REG_GROUP(idx)) { + case 0: + reg_base = ESPI_IO_SIZE0; + break; + case 1: + reg_base = ESPI_IO_SIZE1; + break; + case 2: + reg_base = ESPI_IO_SIZE2; + break; + default: /* case 3 */ + reg_base = ESPI_IO_SIZE3; + break; + } + return ESPI_IO_RANGE_SIZE_REG(reg_base, ESPI_DECODE_RANGE_TO_REG_OFFSET(idx)); } static inline unsigned int espi_mmio_range_base_reg(unsigned int idx) { - return ESPI_MMIO_RANGE_BASE_REG(ESPI_MMIO_BASE_REG0, idx); + if (idx < ESPI_GENERIC_MMIO_WIN_LOW_COUNT) { + return ESPI_MMIO_RANGE_BASE_REG(ESPI_MMIO_BASE_REG0, idx); + } else { + return ESPI_MMIO_RANGE_BASE_REG(ESPI_MMIO_BASE_REG4, + idx - ESPI_GENERIC_MMIO_WIN_LOW_COUNT); + } } static inline unsigned int espi_mmio_range_size_reg(unsigned int idx) { - return ESPI_MMIO_RANGE_SIZE_REG(ESPI_MMIO_SIZE_REG0, idx); + if (idx < ESPI_GENERIC_MMIO_WIN_LOW_COUNT) { + return ESPI_MMIO_RANGE_SIZE_REG(ESPI_MMIO_BASE_REG0, idx); + } else { + return ESPI_MMIO_RANGE_SIZE_REG(ESPI_MMIO_BASE_REG2, + idx - ESPI_GENERIC_MMIO_WIN_LOW_COUNT); + } } static void espi_enable_decode(uint32_t decode_en) @@ -111,7 +159,7 @@ { int i; - for (i = 0; i < ESPI_GENERIC_IO_WIN_COUNT; i++) { + for (i = 0; i < ESPI_GENERIC_IO_WIN_TOTAL_COUNT; i++) { if (!espi_is_decode_enabled(espi_decode_io_range_en_bit(i))) continue; @@ -126,7 +174,7 @@ { int i; - for (i = 0; i < ESPI_GENERIC_IO_WIN_COUNT; i++) { + for (i = 0; i < ESPI_GENERIC_IO_WIN_TOTAL_COUNT; i++) { if (!espi_is_decode_enabled(espi_decode_io_range_en_bit(i))) return i; } @@ -144,11 +192,11 @@ else espi_write16(ESPI_DECODE, 0); - for (idx = 0; idx < ESPI_GENERIC_IO_WIN_COUNT; idx++) { + for (idx = 0; idx < ESPI_GENERIC_IO_WIN_TOTAL_COUNT; idx++) { espi_write16(espi_io_range_base_reg(idx), 0); espi_write8(espi_io_range_size_reg(idx), 0); } - for (idx = 0; idx < ESPI_GENERIC_MMIO_WIN_COUNT; idx++) { + for (idx = 0; idx < ESPI_GENERIC_MMIO_WIN_TOTAL_COUNT; idx++) { espi_write32(espi_mmio_range_base_reg(idx), 0); espi_write16(espi_mmio_range_size_reg(idx), 0); } @@ -248,7 +296,7 @@ { int i; - for (i = 0; i < ESPI_GENERIC_MMIO_WIN_COUNT; i++) { + for (i = 0; i < ESPI_GENERIC_MMIO_WIN_TOTAL_COUNT; i++) { if (!espi_is_decode_enabled(espi_decode_mmio_range_en_bit(i))) continue; @@ -263,7 +311,7 @@ { int i; - for (i = 0; i < ESPI_GENERIC_MMIO_WIN_COUNT; i++) { + for (i = 0; i < ESPI_GENERIC_MMIO_WIN_TOTAL_COUNT; i++) { if (!espi_is_decode_enabled(espi_decode_mmio_range_en_bit(i))) return i; } @@ -339,7 +387,7 @@ espi_enable_decode(cfg->std_io_decode_bitmap); - for (i = 0; i < ESPI_GENERIC_IO_WIN_COUNT; i++) { + for (i = 0; i < ESPI_GENERIC_IO_WIN_TOTAL_COUNT; i++) { if (cfg->generic_io_range[i].size == 0) continue; if (espi_open_generic_io_window(cfg->generic_io_range[i].base, -- To view, visit https://review.coreboot.org/c/coreboot/+/64054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib761cdf201c35805d68cf5e8e462607ffd9fa017 Gerrit-Change-Number: 64054 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/include/espi: reduce visibility of IO/MMIO decode defines
by Felix Held (Code Review) 04 May '22

04 May '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64053 ) Change subject: soc/amd/common/include/espi: reduce visibility of IO/MMIO decode defines ...................................................................... soc/amd/common/include/espi: reduce visibility of IO/MMIO decode defines The eSPI decode range defines aren't ans shouldn't be used directly from outside of the common AMD eSPI code which provides functions to abstract the register access, so move the defines from amdblocks/espi.h to espi_def.h inside the common AMD LPC/eSPI support directory to limit the visibility. The special I/O range decode bits need to stay in amdblocks/espi.h since those are used in the devicetree. Also update the indentation in espi_def.h so that the defines line up properly. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ic4ea30a1a6f10e94d88bf3b29f86dee2da6b39b5 --- M src/soc/amd/common/block/include/amdblocks/espi.h M src/soc/amd/common/block/lpc/espi_def.h 2 files changed, 63 insertions(+), 60 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/64053/1 diff --git a/src/soc/amd/common/block/include/amdblocks/espi.h b/src/soc/amd/common/block/include/amdblocks/espi.h index 45a220e..9717688 100644 --- a/src/soc/amd/common/block/include/amdblocks/espi.h +++ b/src/soc/amd/common/block/include/amdblocks/espi.h @@ -9,27 +9,11 @@ #define ESPI_OFFSET_FROM_BAR 0x10000 #define ESPI_DECODE 0x40 -#define ESPI_DECODE_MMIO_RANGE_EN(range) (1 << (((range) & 3) + 12)) -#define ESPI_DECODE_IO_RANGE_EN(range) (1 << (((range) & 3) + 8)) +/* more bits defined in soc/common/amd/blocks/lpc/espi_def.h */ #define ESPI_DECODE_IO_0x80_EN (1 << 2) #define ESPI_DECODE_IO_0X60_0X64_EN (1 << 1) #define ESPI_DECODE_IO_0X2E_0X2F_EN (1 << 0) -#define ESPI_IO_BASE_REG0 0x44 -#define ESPI_IO_BASE_REG1 0x48 -#define ESPI_IO_SIZE0 0x4c -#define ESPI_MMIO_BASE_REG0 0x50 -#define ESPI_MMIO_BASE_REG1 0x54 -#define ESPI_MMIO_BASE_REG2 0x58 -#define ESPI_MMIO_BASE_REG3 0x5c -#define ESPI_MMIO_SIZE_REG0 0x60 -#define ESPI_MMIO_SIZE_REG1 0x64 - -#define ESPI_IO_RANGE_BASE_REG(base, range) ((base) + ((range) & 3) * 2) -#define ESPI_IO_RANGE_SIZE_REG(base, range) ((base) + ((range) & 3)) -#define ESPI_MMIO_RANGE_BASE_REG(base, range) ((base) + ((range) & 3) * 4) -#define ESPI_MMIO_RANGE_SIZE_REG(base, range) ((base) + ((range) & 3) * 2) - #define ESPI_GENERIC_IO_WIN_COUNT 4 #define ESPI_GENERIC_IO_MAX_WIN_SIZE 0x100 #define ESPI_GENERIC_MMIO_WIN_COUNT 4 diff --git a/src/soc/amd/common/block/lpc/espi_def.h b/src/soc/amd/common/block/lpc/espi_def.h index ef61a13..dc398a9 100644 --- a/src/soc/amd/common/block/lpc/espi_def.h +++ b/src/soc/amd/common/block/lpc/espi_def.h @@ -3,53 +3,72 @@ #ifndef AMD_BLOCK_ESPI_DEF_H #define AMD_BLOCK_ESPI_DEF_H -#define ESPI_DN_TX_HDR0 0x00 -#define ESPI_DN_TX_HDR1 0x04 -#define ESPI_DN_TX_HDR2 0x08 -#define ESPI_DN_TX_DATA 0x0c +#define ESPI_DN_TX_HDR0 0x00 +#define ESPI_DN_TX_HDR1 0x04 +#define ESPI_DN_TX_HDR2 0x08 +#define ESPI_DN_TX_DATA 0x0c -#define ESPI_MASTER_CAP 0x2c -#define ESPI_VW_MAX_SIZE_SHIFT 13 -#define ESPI_VW_MAX_SIZE_MASK (0x3f << ESPI_VW_MAX_SIZE_SHIFT) +#define ESPI_MASTER_CAP 0x2c +#define ESPI_VW_MAX_SIZE_SHIFT 13 +#define ESPI_VW_MAX_SIZE_MASK (0x3f << ESPI_VW_MAX_SIZE_SHIFT) -#define ESPI_GLOBAL_CONTROL_0 0x30 -#define ESPI_WAIT_CNT_SHIFT 24 -#define ESPI_WAIT_CNT_MASK (0x3f << ESPI_WAIT_CNT_SHIFT) -#define ESPI_WDG_CNT_SHIFT 8 -#define ESPI_WDG_CNT_MASK (0xffff << ESPI_WDG_CNT_SHIFT) -#define ESPI_AL_IDLE_TIMER_SHIFT 4 -#define ESPI_AL_IDLE_TIMER_MASK (0x7 << ESPI_AL_IDLE_TIMER_SHIFT) -#define ESPI_AL_STOP_EN (1 << 3) -#define ESPI_PR_CLKGAT_EN (1 << 2) -#define ESPI_WAIT_CHKEN (1 << 1) -#define ESPI_WDG_EN (1 << 0) +#define ESPI_GLOBAL_CONTROL_0 0x30 +#define ESPI_WAIT_CNT_SHIFT 24 +#define ESPI_WAIT_CNT_MASK (0x3f << ESPI_WAIT_CNT_SHIFT) +#define ESPI_WDG_CNT_SHIFT 8 +#define ESPI_WDG_CNT_MASK (0xffff << ESPI_WDG_CNT_SHIFT) +#define ESPI_AL_IDLE_TIMER_SHIFT 4 +#define ESPI_AL_IDLE_TIMER_MASK (0x7 << ESPI_AL_IDLE_TIMER_SHIFT) +#define ESPI_AL_STOP_EN (1 << 3) +#define ESPI_PR_CLKGAT_EN (1 << 2) +#define ESPI_WAIT_CHKEN (1 << 1) +#define ESPI_WDG_EN (1 << 0) -#define ESPI_GLOBAL_CONTROL_1 0x34 -#define ESPI_ALERT_ENABLE (1 << 20) /* Sabrina and later SoCs */ -#define ESPI_RGCMD_INT_MAP_SHIFT 13 -#define ESPI_RGCMD_INT_MAP_MASK (0x1f << ESPI_RGCMD_INT_MAP_SHIFT) -#define ESPI_RGCMD_INT(irq) ((irq) << ESPI_RGCMD_INT_MAP_SHIFT) -#define ESPI_RGCMD_INT_SMI (0x1f << ESPI_RGCMD_INT_MAP_SHIFT) -#define ESPI_ERR_INT_MAP_SHIFT 8 -#define ESPI_ERR_INT_MAP_MASK (0x1f << ESPI_ERR_INT_MAP_SHIFT) -#define ESPI_ERR_INT(irq) ((irq) << ESPI_ERR_INT_MAP_SHIFT) -#define ESPI_ERR_INT_SMI (0x1f << ESPI_ERR_INT_MAP_SHIFT) -#define ESPI_SUB_DECODE_SLV_SHIFT 3 -#define ESPI_SUB_DECODE_SLV_MASK (0x3 << ESPI_SUB_DECODE_SLV_SHIFT) -#define ESPI_SUB_DECODE_EN (1 << 2) -#define ESPI_BUS_MASTER_EN (1 << 1) -#define ESPI_SW_RST (1 << 0) +#define ESPI_GLOBAL_CONTROL_1 0x34 +#define ESPI_ALERT_ENABLE (1 << 20) /* Sabrina and later SoCs */ +#define ESPI_RGCMD_INT_MAP_SHIFT 13 +#define ESPI_RGCMD_INT_MAP_MASK (0x1f << ESPI_RGCMD_INT_MAP_SHIFT) +#define ESPI_RGCMD_INT(irq) ((irq) << ESPI_RGCMD_INT_MAP_SHIFT) +#define ESPI_RGCMD_INT_SMI (0x1f << ESPI_RGCMD_INT_MAP_SHIFT) +#define ESPI_ERR_INT_MAP_SHIFT 8 +#define ESPI_ERR_INT_MAP_MASK (0x1f << ESPI_ERR_INT_MAP_SHIFT) +#define ESPI_ERR_INT(irq) ((irq) << ESPI_ERR_INT_MAP_SHIFT) +#define ESPI_ERR_INT_SMI (0x1f << ESPI_ERR_INT_MAP_SHIFT) +#define ESPI_SUB_DECODE_SLV_SHIFT 3 +#define ESPI_SUB_DECODE_SLV_MASK (0x3 << ESPI_SUB_DECODE_SLV_SHIFT) +#define ESPI_SUB_DECODE_EN (1 << 2) +#define ESPI_BUS_MASTER_EN (1 << 1) +#define ESPI_SW_RST (1 << 0) -#define ESPI_SLAVE0_INT_EN 0x6c -#define ESPI_SLAVE0_INT_STS 0x70 -#define ESPI_STATUS_DNCMD_COMPLETE (1 << 28) -#define ESPI_STATUS_NON_FATAL_ERROR (1 << 6) -#define ESPI_STATUS_FATAL_ERROR (1 << 5) -#define ESPI_STATUS_NO_RESPONSE (1 << 4) -#define ESPI_STATUS_CRC_ERR (1 << 2) -#define ESPI_STATUS_WAIT_TIMEOUT (1 << 1) -#define ESPI_STATUS_BUS_ERROR (1 << 0) +/* bits in ESPI_DECODE 0x40 */ +#define ESPI_DECODE_MMIO_RANGE_EN(range) (1 << (((range) & 3) + 12)) +#define ESPI_DECODE_IO_RANGE_EN(range) (1 << (((range) & 3) + 8)) -#define ESPI_RXVW_POLARITY 0xac +#define ESPI_IO_BASE_REG0 0x44 +#define ESPI_IO_BASE_REG1 0x48 +#define ESPI_IO_SIZE0 0x4c +#define ESPI_MMIO_BASE_REG0 0x50 +#define ESPI_MMIO_BASE_REG1 0x54 +#define ESPI_MMIO_BASE_REG2 0x58 +#define ESPI_MMIO_BASE_REG3 0x5c +#define ESPI_MMIO_SIZE_REG0 0x60 +#define ESPI_MMIO_SIZE_REG1 0x64 + +#define ESPI_SLAVE0_INT_EN 0x6c +#define ESPI_SLAVE0_INT_STS 0x70 +#define ESPI_STATUS_DNCMD_COMPLETE (1 << 28) +#define ESPI_STATUS_NON_FATAL_ERROR (1 << 6) +#define ESPI_STATUS_FATAL_ERROR (1 << 5) +#define ESPI_STATUS_NO_RESPONSE (1 << 4) +#define ESPI_STATUS_CRC_ERR (1 << 2) +#define ESPI_STATUS_WAIT_TIMEOUT (1 << 1) +#define ESPI_STATUS_BUS_ERROR (1 << 0) + +#define ESPI_RXVW_POLARITY 0xac + +#define ESPI_IO_RANGE_BASE_REG(base, range) ((base) + ((range) & 3) * 2) +#define ESPI_IO_RANGE_SIZE_REG(base, range) ((base) + ((range) & 3)) +#define ESPI_MMIO_RANGE_BASE_REG(base, range) ((base) + ((range) & 3) * 4) +#define ESPI_MMIO_RANGE_SIZE_REG(base, range) ((base) + ((range) & 3) * 2) #endif /* AMD_BLOCK_ESPI_DEF_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/64053 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4ea30a1a6f10e94d88bf3b29f86dee2da6b39b5 Gerrit-Change-Number: 64053 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/include/espi: generalize IO/MMIO decode range macros
by Felix Held (Code Review) 04 May '22

04 May '22

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64052 ) Change subject: soc/amd/common/include/espi: generalize IO/MMIO decode range macros ...................................................................... soc/amd/common/include/espi: generalize IO/MMIO decode range macros Sabrina has more eSPI decode ranges than Picasso or Cezanne. Those registers are however not in one block where it's easy to calculate the addresses of a register from the index of the decode range. Within one group of decode range registers it's still easy to calculate the register address, so move the base address from within the macro to the instantiation of the macro as a preparation for adding the support for the additional ranges. TEST=Timeless build results in identical binary for Mandolin Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Id309d955fa3558d660db37a2075240f938361e83 --- M src/soc/amd/common/block/include/amdblocks/espi.h M src/soc/amd/common/block/lpc/espi_util.c 2 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/64052/1 diff --git a/src/soc/amd/common/block/include/amdblocks/espi.h b/src/soc/amd/common/block/include/amdblocks/espi.h index cfba50b..45a220e 100644 --- a/src/soc/amd/common/block/include/amdblocks/espi.h +++ b/src/soc/amd/common/block/include/amdblocks/espi.h @@ -25,10 +25,10 @@ #define ESPI_MMIO_SIZE_REG0 0x60 #define ESPI_MMIO_SIZE_REG1 0x64 -#define ESPI_IO_RANGE_BASE(range) (ESPI_IO_BASE_REG0 + ((range) & 3) * 2) -#define ESPI_IO_RANGE_SIZE(range) (ESPI_IO_SIZE0 + ((range) & 3)) -#define ESPI_MMIO_RANGE_BASE(range) (ESPI_MMIO_BASE_REG0 + ((range) & 3) * 4) -#define ESPI_MMIO_RANGE_SIZE(range) (ESPI_MMIO_SIZE_REG0 + ((range) & 3) * 2) +#define ESPI_IO_RANGE_BASE_REG(base, range) ((base) + ((range) & 3) * 2) +#define ESPI_IO_RANGE_SIZE_REG(base, range) ((base) + ((range) & 3)) +#define ESPI_MMIO_RANGE_BASE_REG(base, range) ((base) + ((range) & 3) * 4) +#define ESPI_MMIO_RANGE_SIZE_REG(base, range) ((base) + ((range) & 3) * 2) #define ESPI_GENERIC_IO_WIN_COUNT 4 #define ESPI_GENERIC_IO_MAX_WIN_SIZE 0x100 diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index c4d15e4..a5f43f4 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -72,22 +72,22 @@ static inline unsigned int espi_io_range_base_reg(unsigned int idx) { - return ESPI_IO_RANGE_BASE(idx); + return ESPI_IO_RANGE_BASE_REG(ESPI_IO_BASE_REG0, idx); } static inline unsigned int espi_io_range_size_reg(unsigned int idx) { - return ESPI_IO_RANGE_SIZE(idx); + return ESPI_IO_RANGE_SIZE_REG(ESPI_IO_SIZE0, idx); } static inline unsigned int espi_mmio_range_base_reg(unsigned int idx) { - return ESPI_MMIO_RANGE_BASE(idx); + return ESPI_MMIO_RANGE_BASE_REG(ESPI_MMIO_BASE_REG0, idx); } static inline unsigned int espi_mmio_range_size_reg(unsigned int idx) { - return ESPI_MMIO_RANGE_SIZE(idx); + return ESPI_MMIO_RANGE_SIZE_REG(ESPI_MMIO_SIZE_REG0, idx); } static void espi_enable_decode(uint32_t decode_en) -- To view, visit https://review.coreboot.org/c/coreboot/+/64052 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id309d955fa3558d660db37a2075240f938361e83 Gerrit-Change-Number: 64052 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/x86/smbios.c: Allow creating entries for empty DIMM slots
by Angel Pons (Code Review) 04 May '22

04 May '22

Attention is currently required from: Arthur Heymans, Marc Jones, Nico Huber, Jonathan Zhang, lichenchen.carl, Nill Ge. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64035 ) Change subject: arch/x86/smbios.c: Allow creating entries for empty DIMM slots ...................................................................... Patch Set 1: (1 comment) File src/arch/x86/smbios.c: https://review.coreboot.org/c/coreboot/+/64035/comment/fbadf60e_b28ffde1 PS1, Line 291: t->form_factor = 0x2; /* Unknown */ > Hmmm, if we expect that location info is filled for empty slots, should […] The default implementation for `smbios_fill_dimm_locator()` just provides a generic name, and mainboards can override it. Looks like `form_factor` is derived from SPD data. -- To view, visit https://review.coreboot.org/c/coreboot/+/64035 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17ae83edf94483bd2eeef5524ff82721c196b8ba Gerrit-Change-Number: 64035 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: lichenchen.carl <lichenchen.carl(a)bytedance.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: lichenchen.carl <lichenchen.carl(a)bytedance.com> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 04 May 2022 18:25:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: Add Raptor Lake device IDs
by Bora Guvendik (Code Review) 04 May '22

04 May '22

Attention is currently required from: Eran Mitrani, Nick Vaccaro. Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63750 ) Change subject: soc/intel: Add Raptor Lake device IDs ...................................................................... Patch Set 8: (1 comment) File src/include/device/pci_ids.h: https://review.coreboot.org/c/coreboot/+/63750/comment/019a8176_356b2be1 PS7, Line 3011: #define PCI_DID_INTEL_ADP_P_ESPI_32 0x5181 : #define PCI_DID_INTEL_ADP_P_ESPI_33 0x5182 : #define PCI_DID_INTEL_ADP_S_ESPI_0 0x7a80 : #define PCI_DID_INTEL_ADP_S_ESPI_1 0x7a81 : #define PCI_DID_INTEL_ADP_S_ESPI_2 0x7a82 : #define PCI_DID_INTEL_ADP_S_ESPI_3 0x7a83 : #define PCI_DID_INTEL_ADP_S_ESPI_4 0x7a84 : #define PCI_DID_INTEL_ADP_S_ESPI_5 0x7a85 : #define PCI_DID_INTEL_ADP_S_ESPI_6 0x7a86 : #define PCI_DID_INTEL_ADP_S_ESPI_7 0x7a87 : #define PCI_DID_INTEL_ADP_S_ESPI_8 0x7a88 : #define PCI_DID_INTEL_ADP_S_ESPI_9 0x7a89 : #define PCI_DID_INTEL_ADP_S_ESPI_10 0x7a8a : #define PCI_DID_INTEL_ADP_S_ESPI_11 0x7a8b : #define PCI_DID_INTEL_ADP_S_ESPI_12 0x7a8c : #define PCI_DID_INTEL_ADP_S_ESPI_13 0x7a8d : #define PCI_DID_INTEL_ADP_S_ESPI_14 0x7a8e : #define PCI_DID_INTEL_ADP_S_ESPI_15 0x7a8f : #define PCI_DID_INTEL_ADP_S_ESPI_16 0x7a90 : #define PCI_DID_INTEL_ADP_S_ESPI_17 0x7a91 : #define PCI_DID_INTEL_ADP_S_ESPI_18 0x7a92 : #define PCI_DID_INTEL_ADP_S_ESPI_19 0x7a93 : #define PCI_DID_INTEL_ADP_S_ESPI_20 0x7a94 : #define PCI_DID_INTEL_ADP_S_ESPI_21 0x7a95 : #define PCI_DID_INTEL_ADP_S_ESPI_22 0x7a96 : #define PCI_DID_INTEL_ADP_S_ESPI_23 0x7a97 : #define PCI_DID_INTEL_ADP_S_ESPI_24 0x7a98 : #define PCI_DID_INTEL_ADP_S_ESPI_25 0x7a99 : #define PCI_DID_INTEL_ADP_S_ESPI_26 0x7a9a : #define PCI_DID_INTEL_ADP_S_ESPI_27 0x7a9b : #define PCI_DID_INTEL_ADP_S_ESPI_28 0x7a9c : #define PCI_DID_INTEL_ADP_S_ESPI_29 0x7a9d : #define PCI_DID_INTEL_ADP_S_ESPI_30 0x7a9e : #define PCI_DID_INTEL_ADP_S_ESPI_31 0x7a9f : #define PCI_DID_INTEL_ADP_M_N_ESPI_0 0x5480 : #define PCI_DID_INTEL_ADP_M_N_ESPI_1 0x5481 : #define PCI_DID_INTEL_ADP_M_N_ESPI_2 0x5482 : #define PCI_DID_INTEL_ADP_M_N_ESPI_3 0x5483 : #define PCI_DID_INTEL_ADP_M_N_ESPI_4 0x5484 : #define PCI_DID_INTEL_ADP_M_N_ESPI_5 0x5485 : #define PCI_DID_INTEL_ADP_M_N_ESPI_6 0x5486 : #define PCI_DID_INTEL_ADP_M_N_ESPI_7 0x5487 : #define PCI_DID_INTEL_ADP_M_N_ESPI_8 0x5488 : #define PCI_DID_INTEL_ADP_M_N_ESPI_9 0x5489 : #define PCI_DID_INTEL_ADP_M_N_ESPI_10 0x548a : #define PCI_DID_INTEL_ADP_M_N_ESPI_11 0x548b : #define PCI_DID_INTEL_ADP_M_N_ESPI_12 0x548c : #define PCI_DID_INTEL_ADP_M_N_ESPI_13 0x548d : #define PCI_DID_INTEL_ADP_M_N_ESPI_14 0x548e : #define PCI_DID_INTEL_ADP_M_N_ESPI_15 0x548f : #define PCI_DID_INTEL_ADP_M_N_ESPI_16 0x5490 : #define PCI_DID_INTEL_ADP_M_N_ESPI_17 0x5491 : #define PCI_DID_INTEL_ADP_M_N_ESPI_18 0x5492 : #define PCI_DID_INTEL_ADP_M_N_ESPI_19 0x5493 : #define PCI_DID_INTEL_ADP_M_N_ESPI_20 0x5494 : #define PCI_DID_INTEL_ADP_M_N_ESPI_21 0x5495 : #define PCI_DID_INTEL_ADP_M_N_ESPI_22 0x5496 : #define PCI_DID_INTEL_ADP_M_N_ESPI_23 0x5497 : #define PCI_DID_INTEL_ADP_M_N_ESPI_24 0x5498 : #define PCI_DID_INTEL_ADP_M_N_ESPI_25 0x5499 : #define PCI_DID_INTEL_ADP_M_N_ESPI_26 0x549a : #define PCI_DID_INTEL_ADP_M_N_ESPI_27 0x549b : #define PCI_DID_INTEL_ADP_M_N_ESPI_28 0x548c : #define PCI_DID_INTEL_ADP_M_N_ESPI_29 0x549d : #define PCI_DID_INTEL_ADP_M_N_ESPI_30 0x549e : #define PCI_DID_INTEL_ADP_M_N_ESPI_31 0x549f : > I renamed 3 of them since they were overlapping with ADL-P / M […] marking it resolved -- To view, visit https://review.coreboot.org/c/coreboot/+/63750 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39e655dec2314a672ea63ba90d8bb3fc53bf77ba Gerrit-Change-Number: 63750 Gerrit-PatchSet: 8 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Wed, 04 May 2022 18:22:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bora Guvendik <bora.guvendik(a)intel.com> Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: comment

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