coreboot-gerrit May 2022

coreboot-gerrit@coreboot.org

1 participants
6162 discussions

Change in coreboot[master]: soc/amd/common/block/psp/psp_gen2: use SMN access to PSP
by Felix Held (Code Review) 04 May '22

04 May '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/64034 ) Change subject: soc/amd/common/block/psp/psp_gen2: use SMN access to PSP ...................................................................... soc/amd/common/block/psp/psp_gen2: use SMN access to PSP Since we can't rely on the MMIO base address in the PSP_ADDR_MSR MSR to access the PSP mailbox registers, switch to using the SMN mapping of the PSP mailbox registers. The PSP SMN base address is taken from the amdgpu driver in the Linux kernel. BUG=b:229779018 TEST=Mandolin still boots successfully and there are no errors/warnings about possibly PSP-related things. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I9d17e523e9ae8d8e14ecedc37131a81f82351487 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64034 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/common/block/psp/Kconfig M src/soc/amd/common/block/psp/psp_gen2.c 2 files changed, 26 insertions(+), 40 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Fred Reitberger: Looks good to me, but someone else must approve diff --git a/src/soc/amd/common/block/psp/Kconfig b/src/soc/amd/common/block/psp/Kconfig index 3249174..22ebb68 100644 --- a/src/soc/amd/common/block/psp/Kconfig +++ b/src/soc/amd/common/block/psp/Kconfig @@ -14,6 +14,7 @@ config SOC_AMD_COMMON_BLOCK_PSP_GEN2 bool select SOC_AMD_COMMON_BLOCK_PSP + select SOC_AMD_COMMON_BLOCK_SMN help Used by the PSP in AMD family 17h, 19h and possibly newer CPUs. diff --git a/src/soc/amd/common/block/psp/psp_gen2.c b/src/soc/amd/common/block/psp/psp_gen2.c index 80650cb..820d44d 100644 --- a/src/soc/amd/common/block/psp/psp_gen2.c +++ b/src/soc/amd/common/block/psp/psp_gen2.c @@ -2,16 +2,16 @@ #include <bootstate.h> #include <console/console.h> -#include <cpu/amd/msr.h> -#include <cpu/x86/msr.h> -#include <device/mmio.h> #include <timer.h> #include <amdblocks/psp.h> -#include <soc/iomap.h> +#include <amdblocks/smn.h> #include "psp_def.h" +#define SMN_PSP_PUBLIC_BASE 0x3800000 + #define PSP_MAILBOX_COMMAND_OFFSET 0x10570 /* 4 bytes */ -#define PSP_MAILBOX_BUFFER_OFFSET 0x10574 /* 8 bytes */ +#define PSP_MAILBOX_BUFFER_L_OFFSET 0x10574 /* 4 bytes */ +#define PSP_MAILBOX_BUFFER_H_OFFSET 0x10578 /* 4 bytes */ #define CORE_2_PSP_MSG_38_OFFSET 0x10998 /* 4 byte */ #define CORE_2_PSP_MSG_38_FUSE_SPL BIT(12) @@ -27,45 +27,40 @@ } __packed fields; }; -static uintptr_t soc_get_psp_base_address(void) -{ - uintptr_t psp_mmio = rdmsr(PSP_ADDR_MSR).lo; - if (!psp_mmio) - printk(BIOS_ERR, "PSP: PSP_ADDR_MSR uninitialized\n"); - return psp_mmio; -} - -static u16 rd_mbox_sts(uintptr_t psp_mmio) +static u16 rd_mbox_sts(void) { union pspv2_mbox_command tmp; - tmp.val = read32p(psp_mmio + PSP_MAILBOX_COMMAND_OFFSET); + tmp.val = smn_read32(SMN_PSP_PUBLIC_BASE + PSP_MAILBOX_COMMAND_OFFSET); return tmp.fields.mbox_status; } -static void wr_mbox_cmd(uintptr_t psp_mmio, u8 cmd) +static void wr_mbox_cmd(u8 cmd) { union pspv2_mbox_command tmp = { .val = 0 }; /* Write entire 32-bit area to begin command execution */ tmp.fields.mbox_command = cmd; - write32p(psp_mmio + PSP_MAILBOX_COMMAND_OFFSET, tmp.val); + smn_write32(SMN_PSP_PUBLIC_BASE + PSP_MAILBOX_COMMAND_OFFSET, tmp.val); } -static u8 rd_mbox_recovery(uintptr_t psp_mmio) +static u8 rd_mbox_recovery(void) { union pspv2_mbox_command tmp; - tmp.val = read32p(psp_mmio + PSP_MAILBOX_COMMAND_OFFSET); + tmp.val = smn_read32(SMN_PSP_PUBLIC_BASE + PSP_MAILBOX_COMMAND_OFFSET); return !!tmp.fields.recovery; } -static void wr_mbox_buffer_ptr(uintptr_t psp_mmio, void *buffer) +static void wr_mbox_buffer_ptr(void *buffer) { - write64p(psp_mmio + PSP_MAILBOX_BUFFER_OFFSET, (uintptr_t)buffer); + const uint32_t buf_addr_h = (uint64_t)(uintptr_t)buffer >> 32; + const uint32_t buf_addr_l = (uint64_t)(uintptr_t)buffer & 0xffffffff; + smn_write32(SMN_PSP_PUBLIC_BASE + PSP_MAILBOX_BUFFER_H_OFFSET, buf_addr_h); + smn_write32(SMN_PSP_PUBLIC_BASE + PSP_MAILBOX_BUFFER_L_OFFSET, buf_addr_l); } -static int wait_command(uintptr_t psp_mmio, bool wait_for_ready) +static int wait_command(bool wait_for_ready) { union pspv2_mbox_command and_mask = { .val = ~0 }; union pspv2_mbox_command expected = { .val = 0 }; @@ -83,7 +78,7 @@ stopwatch_init_msecs_expire(&sw, PSP_CMD_TIMEOUT); do { - tmp = read32p(psp_mmio + PSP_MAILBOX_COMMAND_OFFSET); + tmp = smn_read32(SMN_PSP_PUBLIC_BASE + PSP_MAILBOX_COMMAND_OFFSET); tmp &= ~and_mask.val; if (tmp == expected.val) return 0; @@ -94,27 +89,23 @@ int send_psp_command(u32 command, void *buffer) { - uintptr_t psp_mmio = soc_get_psp_base_address(); - if (!psp_mmio) - return -PSPSTS_NOBASE; - - if (rd_mbox_recovery(psp_mmio)) + if (rd_mbox_recovery()) return -PSPSTS_RECOVERY; - if (wait_command(psp_mmio, true)) + if (wait_command(true)) return -PSPSTS_CMD_TIMEOUT; /* set address of command-response buffer and write command register */ - wr_mbox_buffer_ptr(psp_mmio, buffer); - wr_mbox_cmd(psp_mmio, command); + wr_mbox_buffer_ptr(buffer); + wr_mbox_cmd(command); /* PSP clears command register when complete. All commands except * SxInfo set the Ready bit. */ - if (wait_command(psp_mmio, command != MBOX_BIOS_CMD_SX_INFO)) + if (wait_command(command != MBOX_BIOS_CMD_SX_INFO)) return -PSPSTS_CMD_TIMEOUT; /* check delivery status */ - if (rd_mbox_sts(psp_mmio)) + if (rd_mbox_sts()) return -PSPSTS_SEND_ERROR; return 0; @@ -122,13 +113,7 @@ enum cb_err soc_read_c2p38(uint32_t *msg_38_value) { - uintptr_t psp_mmio = soc_get_psp_base_address(); - - if (!psp_mmio) { - printk(BIOS_WARNING, "PSP: PSP_ADDR_MSR uninitialized\n"); - return CB_ERR; - } - *msg_38_value = read32p(psp_mmio + CORE_2_PSP_MSG_38_OFFSET); + *msg_38_value = smn_read32(SMN_PSP_PUBLIC_BASE + CORE_2_PSP_MSG_38_OFFSET); return CB_SUCCESS; } -- To view, visit https://review.coreboot.org/c/coreboot/+/64034 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d17e523e9ae8d8e14ecedc37131a81f82351487 Gerrit-Change-Number: 64034 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mainboard/msi/ms7d25: Add FIVR configuration
by Michał Żygowski (Code Review) 04 May '22

04 May '22

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64051 ) Change subject: mainboard/msi/ms7d25: Add FIVR configuration ...................................................................... mainboard/msi/ms7d25: Add FIVR configuration Reflect the vendor's firmware FIVR settings. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I97b3b4f9470267961c138fea70703606373f6d52 --- M src/mainboard/msi/ms7d25/devicetree.cb 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/64051/1 diff --git a/src/mainboard/msi/ms7d25/devicetree.cb b/src/mainboard/msi/ms7d25/devicetree.cb index afe6054..301be36 100644 --- a/src/mainboard/msi/ms7d25/devicetree.cb +++ b/src/mainboard/msi/ms7d25/devicetree.cb @@ -84,6 +84,13 @@ register "hybrid_storage_mode" = "1" register "dmi_power_optimize_disable" = "1" + # FIVR configuration + register "fivr_rfi_frequency" = "1394" + register "fivr_spread_spectrum" = "FIVR_SS_1_5" + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + }" + #FIXME: check if this is used by CPU RP2 register "pcie_clk_config_flag[11]" = "PCIE_CLK_FREE_RUNNING" register "pcie_clk_config_flag[16]" = "PCIE_CLK_FREE_RUNNING" -- To view, visit https://review.coreboot.org/c/coreboot/+/64051 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97b3b4f9470267961c138fea70703606373f6d52 Gerrit-Change-Number: 64051 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mainboard/msi/ms7d25: Fill board-specific SMBIOS data
by Michał Żygowski (Code Review) 04 May '22

04 May '22

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64050 ) Change subject: mainboard/msi/ms7d25: Fill board-specific SMBIOS data ...................................................................... mainboard/msi/ms7d25: Fill board-specific SMBIOS data Add board connectors and headers descriptions to SMBIOS. Specify mainboard feature flags and system wakeup type as in vendor firmware. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ie64be21ff302274769b77550c29e58d4ea1376d1 --- M src/mainboard/msi/ms7d25/mainboard.c 1 file changed, 362 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/64050/1 diff --git a/src/mainboard/msi/ms7d25/mainboard.c b/src/mainboard/msi/ms7d25/mainboard.c index 2d35a53..803e500 100644 --- a/src/mainboard/msi/ms7d25/mainboard.c +++ b/src/mainboard/msi/ms7d25/mainboard.c @@ -3,6 +3,7 @@ #include <acpi/acpi.h> #include <device/device.h> #include <soc/ramstage.h> +#include <smbios.h> #include <string.h> #include "gpio.h" @@ -18,9 +19,14 @@ } -static void mainboard_enable(struct device *dev) +u8 smbios_mainboard_feature_flags(void) { + return SMBIOS_FEATURE_FLAGS_HOSTING_BOARD | SMBIOS_FEATURE_FLAGS_REPLACEABLE; +} +smbios_wakeup_type smbios_system_wakeup_type(void) +{ + return SMBIOS_WAKEUP_TYPE_POWER_SWITCH; } void mainboard_silicon_init_params(FSP_S_CONFIG *params) @@ -106,6 +112,361 @@ params->SataLedEnable = 1; } +#if CONFIG(GENERATE_SMBIOS_TABLES) +static const struct port_information smbios_type8_info[] = { + { + .internal_reference_designator = "PS2_USB1", + .internal_connector_type = CONN_NONE, + .external_reference_designator = "Keyboard", + .external_connector_type = CONN_PS_2, + .port_type = TYPE_KEYBOARD_PORT + }, + { + .internal_reference_designator = "PS2_USB1", + .internal_connector_type = CONN_NONE, + .external_reference_designator = "PS2Mouse", + .external_connector_type = CONN_PS_2, + .port_type = TYPE_MOUSE_PORT + }, + { + .internal_reference_designator = "PS2_USB1", + .internal_connector_type = CONN_NONE, + .external_reference_designator = "USB 2.0 Type-A", + .external_connector_type = CONN_ACCESS_BUS_USB, + .port_type = TYPE_USB + }, + { + .internal_reference_designator = "PS2_USB1", + .internal_connector_type = CONN_NONE, + .external_reference_designator = "USB 2.0 Type-A (Flash BIOS)", + .external_connector_type = CONN_ACCESS_BUS_USB, + .port_type = TYPE_USB + }, + { + .internal_reference_designator = "JTPM1 - TPM HDR", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_OTHER_PORT + }, + { + .internal_reference_designator = "LAN_USB1", + .internal_connector_type = CONN_NONE, + .external_reference_designator = "Ethernet", + .external_connector_type = CONN_RJ_45, + .port_type = TYPE_NETWORK_PORT + }, + { + .internal_reference_designator = "LAN_USB1", + .internal_connector_type = CONN_NONE, + .external_reference_designator = "USB 3.2 Gen2x2 Type-C", + .external_connector_type = CONN_USB_TYPE_C, + .port_type = TYPE_USB + }, + { + .internal_reference_designator = "LAN_USB1", + .internal_connector_type = CONN_NONE, + .external_reference_designator = "USB 3.2 Gen2 Type-A", + .external_connector_type = CONN_ACCESS_BUS_USB, + .port_type = TYPE_USB + }, + { + .internal_reference_designator = "SATA1", + .internal_connector_type = CONN_SAS_SATA, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_SATA + }, + { + .internal_reference_designator = "SATA2", + .internal_connector_type = CONN_SAS_SATA, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_SATA + }, + { + .internal_reference_designator = "SATA3", + .internal_connector_type = CONN_SAS_SATA, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_SATA + }, + { + .internal_reference_designator = "SATA4", + .internal_connector_type = CONN_SAS_SATA, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_SATA + }, + { + .internal_reference_designator = "SATA5", + .internal_connector_type = CONN_SAS_SATA, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_SATA + }, + { + .internal_reference_designator = "SATA6", + .internal_connector_type = CONN_SAS_SATA, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_SATA + }, + { + .internal_reference_designator = "JTBT1", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_THUNDERBOLT + }, + { + .internal_reference_designator = "JC1 - CHASSIS INTRUSION", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_OTHER_PORT + }, + { + .internal_reference_designator = "JAUD1 - FRONT AUDIO", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_AUDIO_PORT + }, + { + .internal_reference_designator = "AUDIO1 - REAR AUDIO", + .internal_connector_type = CONN_NONE, + .external_reference_designator = "Audio", + .external_connector_type = CONN_OTHER, + .port_type = TYPE_AUDIO_PORT + }, + { + .internal_reference_designator = "JFP1 - FRONT PANEL", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_OTHER_PORT + }, + { + .internal_reference_designator = "JFP2 - PC SPEAKER", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_OTHER_PORT + }, + { + .internal_reference_designator = "JBAT1 - CLEAR CMOS", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_OTHER_PORT + }, + { + .internal_reference_designator = "JDASH1 - TUNING CONTROLLER", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_OTHER_PORT + }, + { + .internal_reference_designator = "JRGB1 - 5050 RGB LED", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_OTHER_PORT + }, + { + .internal_reference_designator = "JRAINBOW1 - WS2812B RGB LED", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_OTHER_PORT + }, + { + .internal_reference_designator = "JRAINBOW2 - WS2812B RGB LED", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_OTHER_PORT + }, + { + .internal_reference_designator = "CPU_FAN1", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_OTHER_PORT + }, + { + .internal_reference_designator = "PUMP_FAN1", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_OTHER_PORT + }, + { + .internal_reference_designator = "SYS_FAN1", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_OTHER_PORT + }, + { + .internal_reference_designator = "SYS_FAN2", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_OTHER_PORT + }, + { + .internal_reference_designator = "SYS_FAN3", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_OTHER_PORT + }, + { + .internal_reference_designator = "SYS_FAN4", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_OTHER_PORT + }, + { + .internal_reference_designator = "SYS_FAN5", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_OTHER_PORT + }, + { + .internal_reference_designator = "SYS_FAN6", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_OTHER_PORT + }, + { + .internal_reference_designator = "DP_HDMI1", + .internal_connector_type = CONN_NONE, + .external_reference_designator = "HDMI", + .external_connector_type = CONN_OTHER, + .port_type = TYPE_VIDEO_PORT + }, + { + .internal_reference_designator = "DP_HDMI1", + .internal_connector_type = CONN_NONE, + .external_reference_designator = "Display Port", + .external_connector_type = CONN_OTHER, + .port_type = TYPE_VIDEO_PORT + }, + { + .internal_reference_designator = "USB2", + .internal_connector_type = CONN_NONE, + .external_reference_designator = "USB 2.0 Type-A (Upper)", + .external_connector_type = CONN_ACCESS_BUS_USB, + .port_type = TYPE_USB + }, + { + .internal_reference_designator = "USB2", + .internal_connector_type = CONN_NONE, + .external_reference_designator = "USB 2.0 Type-A (Lower)", + .external_connector_type = CONN_ACCESS_BUS_USB, + .port_type = TYPE_USB + }, + { + .internal_reference_designator = "USB2", + .internal_connector_type = CONN_NONE, + .external_reference_designator = "USB 3.2 Gen1 Type-A (Upper)", + .external_connector_type = CONN_ACCESS_BUS_USB, + .port_type = TYPE_USB + }, + { + .internal_reference_designator = "USB2", + .internal_connector_type = CONN_NONE, + .external_reference_designator = "USB 3.2 Gen1 Type-A (Lower)", + .external_connector_type = CONN_ACCESS_BUS_USB, + .port_type = TYPE_USB + }, + { + .internal_reference_designator = "JUSB1 - USB 2.0 ", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_USB + }, + { + .internal_reference_designator = "JUSB2 - USB 2.0", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_USB + }, + { + .internal_reference_designator = "JUSB3 - USB 3.2 GEN 1", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_USB + }, + { + .internal_reference_designator = "JUSB4 - USB 3.2 GEN 1", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_USB + }, + { + .internal_reference_designator = "JUSB5 - USB-C", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_USB + }, + { + .internal_reference_designator = "ATX_PWR1", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_OTHER_PORT + }, + { + .internal_reference_designator = "CPU_PWR1", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_OTHER_PORT + }, + { + .internal_reference_designator = "CPU_PWR2", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_OTHER_PORT + }, +}; + +static int mainboard_smbios_data(struct device *dev, int *handle, unsigned long *current) +{ + int len = 0; + + // add port information + len += smbios_write_type8( + current, handle, + smbios_type8_info, + ARRAY_SIZE(smbios_type8_info) + ); + + return len; +} +#endif + +static void mainboard_enable(struct device *dev) +{ +#if CONFIG(GENERATE_SMBIOS_TABLES) + dev->ops->get_smbios_data = mainboard_smbios_data; +#endif +} + struct chip_operations mainboard_ops = { .init = mainboard_init, .enable_dev = mainboard_enable, -- To view, visit https://review.coreboot.org/c/coreboot/+/64050 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie64be21ff302274769b77550c29e58d4ea1376d1 Gerrit-Change-Number: 64050 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: drivers/crb: Add SMBIOS hook to generate type 43 TPM Device
by Michał Żygowski (Code Review) 04 May '22

04 May '22

Attention is currently required from: Christian Walter. Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64049 ) Change subject: drivers/crb: Add SMBIOS hook to generate type 43 TPM Device ...................................................................... drivers/crb: Add SMBIOS hook to generate type 43 TPM Device Example for Alder Lake PTT: Handle 0x004C, DMI type 43, 31 bytes TPM Device Vendor ID: INTC Specification Version: 2.0 Firmware Revision: 600.18 Description: Intel iTPM Characteristics: TPM Device characteristics not supported OEM-specific Information: 0x00000000 TEST=Execute dmidecode and see the tpye 43 is populated with PTT on MSI PRO Z690-A WIFI DDR4 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I05289f98969bd431017aff1aa77be5806d6f1838 --- M src/drivers/crb/tis.c M src/security/tpm/tss/tcg-2.0/tss_structures.h 2 files changed, 95 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/64049/1 diff --git a/src/drivers/crb/tis.c b/src/drivers/crb/tis.c index 800d145..5e1530e 100644 --- a/src/drivers/crb/tis.c +++ b/src/drivers/crb/tis.c @@ -5,6 +5,10 @@ #include <acpi/acpigen.h> #include <device/device.h> #include <drivers/intel/ptt/ptt.h> +#include <security/tpm/tss.h> +#include <endian.h> +#include <smbios.h> +#include <string.h> #include "tpm.h" #include "chip.h" @@ -123,6 +127,89 @@ return "TPM"; } +#if CONFIG(GENERATE_SMBIOS_TABLES) +static int tpm_get_cap(uint32_t property, uint32_t *value) +{ + TPMS_CAPABILITY_DATA cap_data; + int i; + uint32_t status; + + if (!value) + return -1; + + status = tlcl_get_capability(TPM_CAP_TPM_PROPERTIES, property, 1, &cap_data); + + if (status) + return -1; + + for (i = 0 ; i < cap_data.data.tpmProperties.count; i++) { + if (cap_data.data.tpmProperties.tpmProperty[i].property == property) { + *value = cap_data.data.tpmProperties.tpmProperty[i].value; + return 0; + } + } + + return -1; +} + +static int smbios_write_type43_tpm(struct device *dev, int *handle, unsigned long *current) +{ + struct tpm2_info info; + uint32_t tpm_manuf, tpm_family; + uint32_t fw_ver1, fw_ver2; + uint8_t major_spec_ver, minor_spec_ver; + + tpm2_get_info(&info); + + /* If any of these have invalid values, assume TPM not present or disabled */ + if (info.vendor_id == 0 || info.vendor_id == 0xFFFF || + info.device_id == 0 || info.device_id == 0xFFFF) { + printk(BIOS_DEBUG, "%s: Invalid Vendor ID/Device ID\n", __func__); + return 0; + } + + /* Vendor ID is the value returned by TPM2_GetCapabiltiy TPM_PT_MANUFACTURER */ + if (tpm_get_cap(TPM_PT_MANUFACTURER, &tpm_manuf)) { + printk(BIOS_DEBUG, "TPM2_GetCap TPM_PT_MANUFACTURER failed\n"); + return 0; + } + + tpm_manuf = be32toh(tpm_manuf); + + if (tpm_get_cap(TPM_PT_FIRMWARE_VERSION_1, &fw_ver1)) { + printk(BIOS_DEBUG, "TPM2_GetCap TPM_PT_FIRMWARE_VERSION_1 failed\n"); + return 0; + } + + if (tpm_get_cap(TPM_PT_FIRMWARE_VERSION_2, &fw_ver2)) { + printk(BIOS_DEBUG, "TPM2_GetCap TPM_PT_FIRMWARE_VERSION_2 failed\n"); + return 0; + } + + if (tpm_get_cap(TPM_PT_FAMILY_INDICATOR, &tpm_family)) { + printk(BIOS_DEBUG, "TPM2_GetCap TPM_PT_FAMILY_INDICATOR failed\n"); + return 0; + } + + tpm_family = be32toh(tpm_family); + + if (!strncmp((char *)&tpm_family, "2.0", 4)) { + major_spec_ver = 2; + minor_spec_ver = 0; + } else if (!strncmp((char *)&tpm_family, "1.2", 4)) { + major_spec_ver = 1; + minor_spec_ver = 2; + } else { + printk(BIOS_ERR, "%s: Invalid TPM family\n", __func__); + return 0; + } + + return smbios_write_type43(current, handle, tpm_manuf, major_spec_ver, minor_spec_ver, + fw_ver1, fw_ver2, tis_get_dev_name(&info), + SMBIOS_TPM_DEVICE_CHARACTERISTICS_NOT_SUPPORTED, 0); +} +#endif + static struct device_operations __unused crb_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, @@ -130,7 +217,9 @@ .acpi_name = crb_tpm_acpi_name, .acpi_fill_ssdt = crb_tpm_fill_ssdt, #endif - +#if CONFIG(GENERATE_SMBIOS_TABLES) + .get_smbios_data = smbios_write_type43_tpm, +#endif }; static void enable_dev(struct device *dev) diff --git a/src/security/tpm/tss/tcg-2.0/tss_structures.h b/src/security/tpm/tss/tcg-2.0/tss_structures.h index c0e354d..cb02830 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_structures.h +++ b/src/security/tpm/tss/tcg-2.0/tss_structures.h @@ -177,6 +177,11 @@ /* TPM Property capability constants. */ typedef uint32_t TPM_PT; #define PT_GROUP 0x00000100 +#define PT_FIXED (PT_GROUP * 1) +#define TPM_PT_FAMILY_INDICATOR ((TPM_PT)(PT_FIXED + 0)) +#define TPM_PT_MANUFACTURER ((TPM_PT)(PT_FIXED + 5)) +#define TPM_PT_FIRMWARE_VERSION_1 ((TPM_PT)(PT_FIXED + 11)) +#define TPM_PT_FIRMWARE_VERSION_2 ((TPM_PT)(PT_FIXED + 12)) #define PT_VAR (PT_GROUP * 2) #define TPM_PT_PERMANENT ((TPM_PT)(PT_VAR + 0)) -- To view, visit https://review.coreboot.org/c/coreboot/+/64049 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I05289f98969bd431017aff1aa77be5806d6f1838 Gerrit-Change-Number: 64049 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: smbios: Add API to generate SMBIOS type 43 TPM Device
by Michał Żygowski (Code Review) 04 May '22

04 May '22

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64048 ) Change subject: smbios: Add API to generate SMBIOS type 43 TPM Device ...................................................................... smbios: Add API to generate SMBIOS type 43 TPM Device Based on DMTF SMBIOS Specification 3.1.0. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ia2db29f8bc4cfbc6648bb2cabad074d9ea583ca9 --- M src/arch/x86/smbios.c M src/include/smbios.h 2 files changed, 48 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/64048/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index c48ce86..0998bbe 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -1287,6 +1287,29 @@ return len; } +int smbios_write_type43(unsigned long *current, int *handle, const u32 vendor_id, + const u8 major_spec_ver, const u8 minor_spec_ver, + const u32 fw_ver1, const u32 fw_ver2, const char *description, + const u64 characteristics, const u32 oem_defined) +{ + struct smbios_type43 *t = smbios_carve_table(*current, SMBIOS_TPM_DEVICE, + sizeof(*t), *handle); + + t->vendor_id = vendor_id; + t->major_spec_ver = major_spec_ver; + t->minor_spec_ver = minor_spec_ver; + t->fw_ver1 = fw_ver1; + t->fw_ver2 = fw_ver2; + t->characteristics = characteristics; + t->oem_defined = oem_defined; + t->description = smbios_add_string(t->eos, description); + + const int len = smbios_full_table_len(&t->header, t->eos); + *current += len; + *handle += 1; + return len; +} + unsigned long smbios_write_tables(unsigned long current) { struct smbios_entry *se; diff --git a/src/include/smbios.h b/src/include/smbios.h index 4e53771..0210665 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -35,6 +35,11 @@ const char *name, u8 instance, u16 segment, u8 bus, u8 device, u8 function, u8 device_type); +int smbios_write_type43(unsigned long *current, int *handle, const u32 vendor_id, + const u8 major_spec_ver, const u8 minor_spec_ver, + const u32 fw_ver1, const u32 fw_ver2, const char *description, + const u64 characteristics, const u32 oem_defined); + struct device; int get_smbios_data(struct device *dev, int *handle, unsigned long *current); @@ -253,6 +258,7 @@ SMBIOS_SYSTEM_BOOT_INFORMATION = 32, SMBIOS_IPMI_DEVICE_INFORMATION = 38, SMBIOS_ONBOARD_DEVICES_EXTENDED_INFORMATION = 41, + SMBIOS_TPM_DEVICE = 43, SMBIOS_END_OF_TABLE = 127, } smbios_struct_type_t; @@ -970,6 +976,25 @@ u8 eos[2]; } __packed; + +#define SMBIOS_TPM_DEVICE_CHARACTERISTICS_NOT_SUPPORTED (1ULL << 2) +#define SMBIOS_TPM_DEVICE_FAMILY_CONFIGURABLE_VIA_FW_UPD (1ULL << 3) +#define SMBIOS_TPM_DEVICE_FAMILY_CONFIGURABLE_VIA_PLATFORM_SW_SUPPORT (1ULL << 4) +#define SMBIOS_TPM_DEVICE_FAMILY_CONFIGURABLE_VIA_OEM_PROPRIETARY (1ULL << 5) + +struct smbios_type43 { + struct smbios_header header; + u32 vendor_id; + u8 major_spec_ver; + u8 minor_spec_ver; + u32 fw_ver1; + u32 fw_ver2; + u8 description; + u64 characteristics; + u32 oem_defined; + u8 eos[2]; +} __packed; + struct smbios_type127 { struct smbios_header header; u8 eos[2]; -- To view, visit https://review.coreboot.org/c/coreboot/+/64048 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia2db29f8bc4cfbc6648bb2cabad074d9ea583ca9 Gerrit-Change-Number: 64048 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mb/google/brask/variants/moli: fix tcss_usb3 port
by Tim Wawrzynczak (Code Review) 04 May '22

04 May '22

Attention is currently required from: Casper Chang. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64039 ) Change subject: mb/google/brask/variants/moli: fix tcss_usb3 port ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/64039/comment/5a27590d_4bcf70fa PS1, Line 9: proto please try not to mention board phases in public commit messages https://review.coreboot.org/c/coreboot/+/64039/comment/f9382689_0c4415b7 PS1, Line 12: emerge-brask coreboot, extra comma -- To view, visit https://review.coreboot.org/c/coreboot/+/64039 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8faa4a353d8d617fce7aa70922bf027e6e11b38 Gerrit-Change-Number: 64039 Gerrit-PatchSet: 1 Gerrit-Owner: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Attention: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Comment-Date: Wed, 04 May 2022 15:46:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/brya/var/crota: setting for codec reset pin in overridetree
by Tim Wawrzynczak (Code Review) 04 May '22

04 May '22

Attention is currently required from: Terry Chen. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64043 ) Change subject: mb/google/brya/var/crota: setting for codec reset pin in overridetree ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/64043/comment/30791ff6_4a678d78 PS1, Line 7: setting for codec reset pin in overridetree `Fix codec reset pin in overridetree` -- To view, visit https://review.coreboot.org/c/coreboot/+/64043 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica3467fbc8639526bee071d56af854de5e07091e Gerrit-Change-Number: 64043 Gerrit-PatchSet: 1 Gerrit-Owner: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Comment-Date: Wed, 04 May 2022 15:45:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/tigerlake: Add enum for `DdiPortXConfig`
by Angel Pons (Code Review) 04 May '22

04 May '22

Attention is currently required from: Felix Singer, Tim Crawford, Jeremy Soller, Tim Wawrzynczak, Nick Vaccaro, Michael Niewöhner. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64047 ) Change subject: soc/intel/tigerlake: Add enum for `DdiPortXConfig` ...................................................................... soc/intel/tigerlake: Add enum for `DdiPortXConfig` Add an enum for `DdiPortXConfig` devicetree options. Note that setting these options to zero does not disable the corresponding DDI port, but instead indicates that no LFP (Local Flat Panel, i.e. internal LCD) is connected to it. Change-Id: I9ea10141e51bf29ea44199dcd1b55b63ec771c0a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb M src/mainboard/google/deltaur/variants/baseboard/devicetree.cb M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/mainboard/system76/darp7/devicetree.cb M src/mainboard/system76/galp5/devicetree.cb M src/mainboard/system76/gaze16/devicetree.cb M src/mainboard/system76/lemp10/devicetree.cb M src/mainboard/system76/oryp8/devicetree.cb M src/soc/intel/tigerlake/chip.h 11 files changed, 25 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/64047/1 diff --git a/src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb b/src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb index 3809754..e89414b 100644 --- a/src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb +++ b/src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb @@ -23,11 +23,11 @@ device ref igpu on register "gfx" = "GMA_DEFAULT_PANEL(0)" # eDP - register "DdiPortAConfig" = "1" + register "DdiPortAConfig" = "DDI_PORT_CFG_EDP" register "DdiPortAHpd" = "1" register "DdiPortADdc" = "0" # HDMI - register "DdiPortBConfig" = "0" + register "DdiPortBConfig" = "DDI_PORT_CFG_NO_LFP" register "DdiPortBHpd" = "1" register "DdiPortBDdc" = "1" end diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb index f5dc019..6603baf 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -116,7 +116,7 @@ register "TcssXhciEn" = "1" # DisplayPort - register "DdiPortAConfig" = "1" # eDP + register "DdiPortAConfig" = "DDI_PORT_CFG_EDP" register "DdiPortAHpd" = "1" # Disable PM to allow for shorter irq pulses diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 5e5a586..9f3987e 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -239,8 +239,8 @@ register "TcssAuxOri" = "0" # DP port - register "DdiPortAConfig" = "1" # eDP - register "DdiPortBConfig" = "0" + register "DdiPortAConfig" = "DDI_PORT_CFG_EDP" + register "DdiPortBConfig" = "DDI_PORT_CFG_NO_LFP" register "DdiPortAHpd" = "1" register "DdiPortBHpd" = "1" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 2c9a548..1af05c4 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -68,7 +68,7 @@ register "SataPortsEnable[1]" = "1" # enabling EDP in PortA - register "DdiPortAConfig" = "1" + register "DdiPortAConfig" = "DDI_PORT_CFG_EDP" register "DdiPortBHpd" = "1" register "DdiPort1Hpd" = "1" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index d19747a..ad1a45d 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -65,7 +65,7 @@ register "PcieClkSrcUsage[3]" = "0x8" # enabling EDP in PortA - register "DdiPortAConfig" = "1" + register "DdiPortAConfig" = "DDI_PORT_CFG_EDP" register "DdiPortAHpd" = "1" register "DdiPortADdc" = "0" diff --git a/src/mainboard/system76/darp7/devicetree.cb b/src/mainboard/system76/darp7/devicetree.cb index 4b7ad23..dd35616 100644 --- a/src/mainboard/system76/darp7/devicetree.cb +++ b/src/mainboard/system76/darp7/devicetree.cb @@ -94,12 +94,12 @@ device ref system_agent on end device ref igpu on # DDIA is eDP - register "DdiPortAConfig" = "1" + register "DdiPortAConfig" = "DDI_PORT_CFG_EDP" register "DdiPortAHpd" = "1" register "DdiPortADdc" = "0" # DDIB is HDMI - register "DdiPortBConfig" = "0" + register "DdiPortBConfig" = "DDI_PORT_CFG_NO_LFP" register "DdiPortBHpd" = "1" register "DdiPortBDdc" = "1" diff --git a/src/mainboard/system76/galp5/devicetree.cb b/src/mainboard/system76/galp5/devicetree.cb index 81163b6..5650f20 100644 --- a/src/mainboard/system76/galp5/devicetree.cb +++ b/src/mainboard/system76/galp5/devicetree.cb @@ -94,12 +94,12 @@ device ref system_agent on end device ref igpu on # DDIA is eDP - register "DdiPortAConfig" = "1" + register "DdiPortAConfig" = "DDI_PORT_CFG_EDP" register "DdiPortAHpd" = "1" register "DdiPortADdc" = "0" # DDIB is HDMI - register "DdiPortBConfig" = "0" + register "DdiPortBConfig" = "DDI_PORT_CFG_NO_LFP" register "DdiPortBHpd" = "1" register "DdiPortBDdc" = "1" diff --git a/src/mainboard/system76/gaze16/devicetree.cb b/src/mainboard/system76/gaze16/devicetree.cb index a92f044..fbab7fb 100644 --- a/src/mainboard/system76/gaze16/devicetree.cb +++ b/src/mainboard/system76/gaze16/devicetree.cb @@ -87,12 +87,12 @@ device ref system_agent on end device ref igpu on # DDIA is eDP - register "DdiPortAConfig" = "1" + register "DdiPortAConfig" = "DDI_PORT_CFG_EDP" register "DdiPortAHpd" = "1" register "DdiPortADdc" = "0" # DDIB is HDMI - register "DdiPortBConfig" = "0" + register "DdiPortBConfig" = "DDI_PORT_CFG_NO_LFP" register "DdiPortBHpd" = "1" register "DdiPortBDdc" = "1" end diff --git a/src/mainboard/system76/lemp10/devicetree.cb b/src/mainboard/system76/lemp10/devicetree.cb index e84c405..74bd7da 100644 --- a/src/mainboard/system76/lemp10/devicetree.cb +++ b/src/mainboard/system76/lemp10/devicetree.cb @@ -94,12 +94,12 @@ device ref system_agent on end device ref igpu on # DDIA is eDP - register "DdiPortAConfig" = "1" + register "DdiPortAConfig" = "DDI_PORT_CFG_EDP" register "DdiPortAHpd" = "1" register "DdiPortADdc" = "0" # DDIB is HDMI - register "DdiPortBConfig" = "0" + register "DdiPortBConfig" = "DDI_PORT_CFG_NO_LFP" register "DdiPortBHpd" = "1" register "DdiPortBDdc" = "1" diff --git a/src/mainboard/system76/oryp8/devicetree.cb b/src/mainboard/system76/oryp8/devicetree.cb index 65b6e87..ec01d8a 100644 --- a/src/mainboard/system76/oryp8/devicetree.cb +++ b/src/mainboard/system76/oryp8/devicetree.cb @@ -105,7 +105,7 @@ end device ref igpu on # DDIA is eDP - register "DdiPortAConfig" = "1" + register "DdiPortAConfig" = "DDI_PORT_CFG_EDP" register "DdiPortAHpd" = "1" register "DdiPortADdc" = "0" end diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 1f36e27..746cfa2 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -92,6 +92,12 @@ SLEW_FAST_16 }; +enum ddi_port_config { + DDI_PORT_CFG_NO_LFP = 0, + DDI_PORT_CFG_EDP = 1, + DDI_PORT_CFG_MIPI_DSI = 2, +}; + struct soc_intel_tigerlake_config { /* Common struct containing soc config data required by common code */ @@ -367,13 +373,9 @@ */ uint8_t gpio_pm[TOTAL_GPIO_COMM]; - /* DP config */ - /* - * Port config - * 0:Disabled, 1:eDP, 2:MIPI DSI - */ - uint8_t DdiPortAConfig; - uint8_t DdiPortBConfig; + /* DDI port config */ + enum ddi_port_config DdiPortAConfig; + enum ddi_port_config DdiPortBConfig; /* Enable(1)/Disable(0) HPD */ uint8_t DdiPortAHpd; -- To view, visit https://review.coreboot.org/c/coreboot/+/64047 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ea10141e51bf29ea44199dcd1b55b63ec771c0a Gerrit-Change-Number: 64047 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: cpu/intel/model_2065x: Drop unused function declaration
by Angel Pons (Code Review) 04 May '22

04 May '22

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64046 ) Change subject: cpu/intel/model_2065x: Drop unused function declaration ...................................................................... cpu/intel/model_2065x: Drop unused function declaration Looks like the `set_power_limits()` declaration is copy-pasta leftovers from `cpu/intel/model_206ax`. As it's unused, get rid of it. Change-Id: I81704e883e52fea42488f52be116b6fcc2c6af4b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/model_2065x/model_2065x.h 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/64046/1 diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index 251fd75..92cc55c 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -53,9 +53,6 @@ /* Lock MSRs */ void intel_model_2065x_finalize_smm(void); -/* Configure power limits for turbo mode */ -void set_power_limits(u8 power_limit_1_time); - /* Sanity check config options. */ #if (CONFIG_SMM_TSEG_SIZE <= CONFIG_SMM_RESERVED_SIZE) # error "CONFIG_SMM_TSEG_SIZE <= CONFIG_SMM_RESERVED_SIZE" -- To view, visit https://review.coreboot.org/c/coreboot/+/64046 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81704e883e52fea42488f52be116b6fcc2c6af4b Gerrit-Change-Number: 64046 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: util/amdfwtool: Add IKEK key for Trusted Application
by Felix Held (Code Review) 04 May '22

04 May '22

Attention is currently required from: Bao Zheng, Avinash Alevoor, Karthik Ramasubramanian. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64040 ) Change subject: util/amdfwtool: Add IKEK key for Trusted Application ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/64040 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d05792cfd98fa9c38f5deef1ac3282625983eeb Gerrit-Change-Number: 64040 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Avinash Alevoor Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-CC: Mohan Viswanathan Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Avinash Alevoor Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 04 May 2022 15:27:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit May 2022