coreboot-gerrit May 2022

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Change in coreboot[master]: nb/amd/agesa/family14: Clean up fx_devs stuff
by Nico Huber (Code Review) 04 May '22

04 May '22

Attention is currently required from: Angel Pons, Arthur Heymans, Kyösti Mälkki, Felix Held. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64009 ) Change subject: nb/amd/agesa/family14: Clean up fx_devs stuff ...................................................................... Patch Set 1: (3 comments) File src/northbridge/amd/agesa/family14/northbridge.c: https://review.coreboot.org/c/coreboot/+/64009/comment/f092a0b3_e4c59214 PS1, Line 78: if (fx_devs == 0) > I'm not sure if fx_devs have been populated when this gets called. […] It's redundant with the `if` inside get_fx_devs(). Anyway, doesn't matter if the cleanup continues. https://review.coreboot.org/c/coreboot/+/64009/comment/71860ced_06a64f60 PS1, Line 86: if (fx_devs == 0) > I'm not sure if fx_devs have been populated when this gets called. […] Same. https://review.coreboot.org/c/coreboot/+/64009/comment/91a73434_8727581e PS1, Line 88: for (i = 0; i < fx_devs; i++) { > I'm not sure if fx_devs have been populated when this gets called. […] After calling get_fx_devs() above, `fx_devs` is always `>= 1` (unless we are dead). Anyway... -- To view, visit https://review.coreboot.org/c/coreboot/+/64009 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8475d42627c48336c98afdfe659f3bbfb173c3c Gerrit-Change-Number: 64009 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 04 May 2022 16:33:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: Allow creating meminfo for empty DIMM slots
by Nico Huber (Code Review) 04 May '22

04 May '22

Attention is currently required from: Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Christian Walter, Angel Pons, Arthur Heymans, Tim Chu. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64036 ) Change subject: soc/intel/xeon_sp/cpx: Allow creating meminfo for empty DIMM slots ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/64036/comment/1fdf29cd_0813233f PS1, Line 9: Introduce the mainboard-defined `mainboard_dimm_slot_exists()` function > > Wouldn't a simple Kconfig number do? It's hard to tell without seeing […] I imagined something like this but didn't know if it exists :) -- To view, visit https://review.coreboot.org/c/coreboot/+/64036 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d9c41dd7d981842ca6f0294d9e6b0fedc0c98e4 Gerrit-Change-Number: 64036 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 04 May 2022 16:27:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86/smbios.c: Allow creating entries for empty DIMM slots
by Nico Huber (Code Review) 04 May '22

04 May '22

Attention is currently required from: Arthur Heymans, Marc Jones, Jonathan Zhang, Angel Pons, lichenchen.carl, Nill Ge. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64035 ) Change subject: arch/x86/smbios.c: Allow creating entries for empty DIMM slots ...................................................................... Patch Set 1: (2 comments) File src/arch/x86/smbios.c: https://review.coreboot.org/c/coreboot/+/64035/comment/78c36aa5_5ad615c8 PS1, Line 281: *current > I just reused the signature of `create_smbios_type17_for_dimm()`. […] Ack. I just noticed the whole file is full of such odd patterns. https://review.coreboot.org/c/coreboot/+/64035/comment/b144c163_46969ae6 PS1, Line 291: t->form_factor = 0x2; /* Unknown */ > It could be SO-DIMM in some cases. Hmmm, if we expect that location info is filled for empty slots, should we expect `form_factor` to be filled too? -- To view, visit https://review.coreboot.org/c/coreboot/+/64035 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17ae83edf94483bd2eeef5524ff82721c196b8ba Gerrit-Change-Number: 64035 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: lichenchen.carl <lichenchen.carl(a)bytedance.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: lichenchen.carl <lichenchen.carl(a)bytedance.com> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 04 May 2022 16:25:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: provide a list of D-states to enter LPM
by Tarun Tuli (Code Review) 04 May '22

04 May '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Angel Pons. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63969 ) Change subject: soc/intel/alderlake: provide a list of D-states to enter LPM ...................................................................... Patch Set 18: (4 comments) Patchset: PS18: Resolving these as the changes have been made. Feel free to comment on the updated approaches if needed. File src/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/63969/comment/bef44188_49a94090 PS17, Line 1485: __weak uint8_t soc_lpi_get_constraints(void) { return 0; } > In patchset 18 Done File src/soc/intel/alderlake/acpi.c: https://review.coreboot.org/c/coreboot/+/63969/comment/55168402_aa6dbc42 PS12, Line 179: min_pci_d_states > Implemented in patch set #15 Done File src/soc/intel/alderlake/acpi.c: https://review.coreboot.org/c/coreboot/+/63969/comment/156ce4c7_daa1d8ff PS13, Line 116: typedef enum { : D0, /* 0 */ : D1, /* 1 */ : D2, /* 2 */ : D3, /* 3 */ : UNDEF : } D_STATES; > I didn't ultimately use it as it also it doesn't seem safe as it also has unsupported values (ACPI_D […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe46a0583c522a8adf0a015cd3a698f694482437 Gerrit-Change-Number: 63969 Gerrit-PatchSet: 18 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 04 May 2022 16:23:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tarun Tuli <taruntuli(a)google.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/psp/psp_gen2: use SMN access to PSP
by Felix Held (Code Review) 04 May '22

04 May '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/64034 ) Change subject: soc/amd/common/block/psp/psp_gen2: use SMN access to PSP ...................................................................... soc/amd/common/block/psp/psp_gen2: use SMN access to PSP Since we can't rely on the MMIO base address in the PSP_ADDR_MSR MSR to access the PSP mailbox registers, switch to using the SMN mapping of the PSP mailbox registers. The PSP SMN base address is taken from the amdgpu driver in the Linux kernel. BUG=b:229779018 TEST=Mandolin still boots successfully and there are no errors/warnings about possibly PSP-related things. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I9d17e523e9ae8d8e14ecedc37131a81f82351487 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64034 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/common/block/psp/Kconfig M src/soc/amd/common/block/psp/psp_gen2.c 2 files changed, 26 insertions(+), 40 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Fred Reitberger: Looks good to me, but someone else must approve diff --git a/src/soc/amd/common/block/psp/Kconfig b/src/soc/amd/common/block/psp/Kconfig index 3249174..22ebb68 100644 --- a/src/soc/amd/common/block/psp/Kconfig +++ b/src/soc/amd/common/block/psp/Kconfig @@ -14,6 +14,7 @@ config SOC_AMD_COMMON_BLOCK_PSP_GEN2 bool select SOC_AMD_COMMON_BLOCK_PSP + select SOC_AMD_COMMON_BLOCK_SMN help Used by the PSP in AMD family 17h, 19h and possibly newer CPUs. diff --git a/src/soc/amd/common/block/psp/psp_gen2.c b/src/soc/amd/common/block/psp/psp_gen2.c index 80650cb..820d44d 100644 --- a/src/soc/amd/common/block/psp/psp_gen2.c +++ b/src/soc/amd/common/block/psp/psp_gen2.c @@ -2,16 +2,16 @@ #include <bootstate.h> #include <console/console.h> -#include <cpu/amd/msr.h> -#include <cpu/x86/msr.h> -#include <device/mmio.h> #include <timer.h> #include <amdblocks/psp.h> -#include <soc/iomap.h> +#include <amdblocks/smn.h> #include "psp_def.h" +#define SMN_PSP_PUBLIC_BASE 0x3800000 + #define PSP_MAILBOX_COMMAND_OFFSET 0x10570 /* 4 bytes */ -#define PSP_MAILBOX_BUFFER_OFFSET 0x10574 /* 8 bytes */ +#define PSP_MAILBOX_BUFFER_L_OFFSET 0x10574 /* 4 bytes */ +#define PSP_MAILBOX_BUFFER_H_OFFSET 0x10578 /* 4 bytes */ #define CORE_2_PSP_MSG_38_OFFSET 0x10998 /* 4 byte */ #define CORE_2_PSP_MSG_38_FUSE_SPL BIT(12) @@ -27,45 +27,40 @@ } __packed fields; }; -static uintptr_t soc_get_psp_base_address(void) -{ - uintptr_t psp_mmio = rdmsr(PSP_ADDR_MSR).lo; - if (!psp_mmio) - printk(BIOS_ERR, "PSP: PSP_ADDR_MSR uninitialized\n"); - return psp_mmio; -} - -static u16 rd_mbox_sts(uintptr_t psp_mmio) +static u16 rd_mbox_sts(void) { union pspv2_mbox_command tmp; - tmp.val = read32p(psp_mmio + PSP_MAILBOX_COMMAND_OFFSET); + tmp.val = smn_read32(SMN_PSP_PUBLIC_BASE + PSP_MAILBOX_COMMAND_OFFSET); return tmp.fields.mbox_status; } -static void wr_mbox_cmd(uintptr_t psp_mmio, u8 cmd) +static void wr_mbox_cmd(u8 cmd) { union pspv2_mbox_command tmp = { .val = 0 }; /* Write entire 32-bit area to begin command execution */ tmp.fields.mbox_command = cmd; - write32p(psp_mmio + PSP_MAILBOX_COMMAND_OFFSET, tmp.val); + smn_write32(SMN_PSP_PUBLIC_BASE + PSP_MAILBOX_COMMAND_OFFSET, tmp.val); } -static u8 rd_mbox_recovery(uintptr_t psp_mmio) +static u8 rd_mbox_recovery(void) { union pspv2_mbox_command tmp; - tmp.val = read32p(psp_mmio + PSP_MAILBOX_COMMAND_OFFSET); + tmp.val = smn_read32(SMN_PSP_PUBLIC_BASE + PSP_MAILBOX_COMMAND_OFFSET); return !!tmp.fields.recovery; } -static void wr_mbox_buffer_ptr(uintptr_t psp_mmio, void *buffer) +static void wr_mbox_buffer_ptr(void *buffer) { - write64p(psp_mmio + PSP_MAILBOX_BUFFER_OFFSET, (uintptr_t)buffer); + const uint32_t buf_addr_h = (uint64_t)(uintptr_t)buffer >> 32; + const uint32_t buf_addr_l = (uint64_t)(uintptr_t)buffer & 0xffffffff; + smn_write32(SMN_PSP_PUBLIC_BASE + PSP_MAILBOX_BUFFER_H_OFFSET, buf_addr_h); + smn_write32(SMN_PSP_PUBLIC_BASE + PSP_MAILBOX_BUFFER_L_OFFSET, buf_addr_l); } -static int wait_command(uintptr_t psp_mmio, bool wait_for_ready) +static int wait_command(bool wait_for_ready) { union pspv2_mbox_command and_mask = { .val = ~0 }; union pspv2_mbox_command expected = { .val = 0 }; @@ -83,7 +78,7 @@ stopwatch_init_msecs_expire(&sw, PSP_CMD_TIMEOUT); do { - tmp = read32p(psp_mmio + PSP_MAILBOX_COMMAND_OFFSET); + tmp = smn_read32(SMN_PSP_PUBLIC_BASE + PSP_MAILBOX_COMMAND_OFFSET); tmp &= ~and_mask.val; if (tmp == expected.val) return 0; @@ -94,27 +89,23 @@ int send_psp_command(u32 command, void *buffer) { - uintptr_t psp_mmio = soc_get_psp_base_address(); - if (!psp_mmio) - return -PSPSTS_NOBASE; - - if (rd_mbox_recovery(psp_mmio)) + if (rd_mbox_recovery()) return -PSPSTS_RECOVERY; - if (wait_command(psp_mmio, true)) + if (wait_command(true)) return -PSPSTS_CMD_TIMEOUT; /* set address of command-response buffer and write command register */ - wr_mbox_buffer_ptr(psp_mmio, buffer); - wr_mbox_cmd(psp_mmio, command); + wr_mbox_buffer_ptr(buffer); + wr_mbox_cmd(command); /* PSP clears command register when complete. All commands except * SxInfo set the Ready bit. */ - if (wait_command(psp_mmio, command != MBOX_BIOS_CMD_SX_INFO)) + if (wait_command(command != MBOX_BIOS_CMD_SX_INFO)) return -PSPSTS_CMD_TIMEOUT; /* check delivery status */ - if (rd_mbox_sts(psp_mmio)) + if (rd_mbox_sts()) return -PSPSTS_SEND_ERROR; return 0; @@ -122,13 +113,7 @@ enum cb_err soc_read_c2p38(uint32_t *msg_38_value) { - uintptr_t psp_mmio = soc_get_psp_base_address(); - - if (!psp_mmio) { - printk(BIOS_WARNING, "PSP: PSP_ADDR_MSR uninitialized\n"); - return CB_ERR; - } - *msg_38_value = read32p(psp_mmio + CORE_2_PSP_MSG_38_OFFSET); + *msg_38_value = smn_read32(SMN_PSP_PUBLIC_BASE + CORE_2_PSP_MSG_38_OFFSET); return CB_SUCCESS; } -- To view, visit https://review.coreboot.org/c/coreboot/+/64034 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d17e523e9ae8d8e14ecedc37131a81f82351487 Gerrit-Change-Number: 64034 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mainboard/msi/ms7d25: Add FIVR configuration
by Michał Żygowski (Code Review) 04 May '22

04 May '22

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64051 ) Change subject: mainboard/msi/ms7d25: Add FIVR configuration ...................................................................... mainboard/msi/ms7d25: Add FIVR configuration Reflect the vendor's firmware FIVR settings. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I97b3b4f9470267961c138fea70703606373f6d52 --- M src/mainboard/msi/ms7d25/devicetree.cb 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/64051/1 diff --git a/src/mainboard/msi/ms7d25/devicetree.cb b/src/mainboard/msi/ms7d25/devicetree.cb index afe6054..301be36 100644 --- a/src/mainboard/msi/ms7d25/devicetree.cb +++ b/src/mainboard/msi/ms7d25/devicetree.cb @@ -84,6 +84,13 @@ register "hybrid_storage_mode" = "1" register "dmi_power_optimize_disable" = "1" + # FIVR configuration + register "fivr_rfi_frequency" = "1394" + register "fivr_spread_spectrum" = "FIVR_SS_1_5" + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + }" + #FIXME: check if this is used by CPU RP2 register "pcie_clk_config_flag[11]" = "PCIE_CLK_FREE_RUNNING" register "pcie_clk_config_flag[16]" = "PCIE_CLK_FREE_RUNNING" -- To view, visit https://review.coreboot.org/c/coreboot/+/64051 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97b3b4f9470267961c138fea70703606373f6d52 Gerrit-Change-Number: 64051 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mainboard/msi/ms7d25: Fill board-specific SMBIOS data
by Michał Żygowski (Code Review) 04 May '22

04 May '22

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64050 ) Change subject: mainboard/msi/ms7d25: Fill board-specific SMBIOS data ...................................................................... mainboard/msi/ms7d25: Fill board-specific SMBIOS data Add board connectors and headers descriptions to SMBIOS. Specify mainboard feature flags and system wakeup type as in vendor firmware. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ie64be21ff302274769b77550c29e58d4ea1376d1 --- M src/mainboard/msi/ms7d25/mainboard.c 1 file changed, 362 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/64050/1 diff --git a/src/mainboard/msi/ms7d25/mainboard.c b/src/mainboard/msi/ms7d25/mainboard.c index 2d35a53..803e500 100644 --- a/src/mainboard/msi/ms7d25/mainboard.c +++ b/src/mainboard/msi/ms7d25/mainboard.c @@ -3,6 +3,7 @@ #include <acpi/acpi.h> #include <device/device.h> #include <soc/ramstage.h> +#include <smbios.h> #include <string.h> #include "gpio.h" @@ -18,9 +19,14 @@ } -static void mainboard_enable(struct device *dev) +u8 smbios_mainboard_feature_flags(void) { + return SMBIOS_FEATURE_FLAGS_HOSTING_BOARD | SMBIOS_FEATURE_FLAGS_REPLACEABLE; +} +smbios_wakeup_type smbios_system_wakeup_type(void) +{ + return SMBIOS_WAKEUP_TYPE_POWER_SWITCH; } void mainboard_silicon_init_params(FSP_S_CONFIG *params) @@ -106,6 +112,361 @@ params->SataLedEnable = 1; } +#if CONFIG(GENERATE_SMBIOS_TABLES) +static const struct port_information smbios_type8_info[] = { + { + .internal_reference_designator = "PS2_USB1", + .internal_connector_type = CONN_NONE, + .external_reference_designator = "Keyboard", + .external_connector_type = CONN_PS_2, + .port_type = TYPE_KEYBOARD_PORT + }, + { + .internal_reference_designator = "PS2_USB1", + .internal_connector_type = CONN_NONE, + .external_reference_designator = "PS2Mouse", + .external_connector_type = CONN_PS_2, + .port_type = TYPE_MOUSE_PORT + }, + { + .internal_reference_designator = "PS2_USB1", + .internal_connector_type = CONN_NONE, + .external_reference_designator = "USB 2.0 Type-A", + .external_connector_type = CONN_ACCESS_BUS_USB, + .port_type = TYPE_USB + }, + { + .internal_reference_designator = "PS2_USB1", + .internal_connector_type = CONN_NONE, + .external_reference_designator = "USB 2.0 Type-A (Flash BIOS)", + .external_connector_type = CONN_ACCESS_BUS_USB, + .port_type = TYPE_USB + }, + { + .internal_reference_designator = "JTPM1 - TPM HDR", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_OTHER_PORT + }, + { + .internal_reference_designator = "LAN_USB1", + .internal_connector_type = CONN_NONE, + .external_reference_designator = "Ethernet", + .external_connector_type = CONN_RJ_45, + .port_type = TYPE_NETWORK_PORT + }, + { + .internal_reference_designator = "LAN_USB1", + .internal_connector_type = CONN_NONE, + .external_reference_designator = "USB 3.2 Gen2x2 Type-C", + .external_connector_type = CONN_USB_TYPE_C, + .port_type = TYPE_USB + }, + { + .internal_reference_designator = "LAN_USB1", + .internal_connector_type = CONN_NONE, + .external_reference_designator = "USB 3.2 Gen2 Type-A", + .external_connector_type = CONN_ACCESS_BUS_USB, + .port_type = TYPE_USB + }, + { + .internal_reference_designator = "SATA1", + .internal_connector_type = CONN_SAS_SATA, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_SATA + }, + { + .internal_reference_designator = "SATA2", + .internal_connector_type = CONN_SAS_SATA, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_SATA + }, + { + .internal_reference_designator = "SATA3", + .internal_connector_type = CONN_SAS_SATA, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_SATA + }, + { + .internal_reference_designator = "SATA4", + .internal_connector_type = CONN_SAS_SATA, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_SATA + }, + { + .internal_reference_designator = "SATA5", + .internal_connector_type = CONN_SAS_SATA, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_SATA + }, + { + .internal_reference_designator = "SATA6", + .internal_connector_type = CONN_SAS_SATA, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_SATA + }, + { + .internal_reference_designator = "JTBT1", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_THUNDERBOLT + }, + { + .internal_reference_designator = "JC1 - CHASSIS INTRUSION", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_OTHER_PORT + }, + { + .internal_reference_designator = "JAUD1 - FRONT AUDIO", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_AUDIO_PORT + }, + { + .internal_reference_designator = "AUDIO1 - REAR AUDIO", + .internal_connector_type = CONN_NONE, + .external_reference_designator = "Audio", + .external_connector_type = CONN_OTHER, + .port_type = TYPE_AUDIO_PORT + }, + { + .internal_reference_designator = "JFP1 - FRONT PANEL", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_OTHER_PORT + }, + { + .internal_reference_designator = "JFP2 - PC SPEAKER", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_OTHER_PORT + }, + { + .internal_reference_designator = "JBAT1 - CLEAR CMOS", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_OTHER_PORT + }, + { + .internal_reference_designator = "JDASH1 - TUNING CONTROLLER", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_OTHER_PORT + }, + { + .internal_reference_designator = "JRGB1 - 5050 RGB LED", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_OTHER_PORT + }, + { + .internal_reference_designator = "JRAINBOW1 - WS2812B RGB LED", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_OTHER_PORT + }, + { + .internal_reference_designator = "JRAINBOW2 - WS2812B RGB LED", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_OTHER_PORT + }, + { + .internal_reference_designator = "CPU_FAN1", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_OTHER_PORT + }, + { + .internal_reference_designator = "PUMP_FAN1", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_OTHER_PORT + }, + { + .internal_reference_designator = "SYS_FAN1", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_OTHER_PORT + }, + { + .internal_reference_designator = "SYS_FAN2", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_OTHER_PORT + }, + { + .internal_reference_designator = "SYS_FAN3", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_OTHER_PORT + }, + { + .internal_reference_designator = "SYS_FAN4", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_OTHER_PORT + }, + { + .internal_reference_designator = "SYS_FAN5", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_OTHER_PORT + }, + { + .internal_reference_designator = "SYS_FAN6", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_OTHER_PORT + }, + { + .internal_reference_designator = "DP_HDMI1", + .internal_connector_type = CONN_NONE, + .external_reference_designator = "HDMI", + .external_connector_type = CONN_OTHER, + .port_type = TYPE_VIDEO_PORT + }, + { + .internal_reference_designator = "DP_HDMI1", + .internal_connector_type = CONN_NONE, + .external_reference_designator = "Display Port", + .external_connector_type = CONN_OTHER, + .port_type = TYPE_VIDEO_PORT + }, + { + .internal_reference_designator = "USB2", + .internal_connector_type = CONN_NONE, + .external_reference_designator = "USB 2.0 Type-A (Upper)", + .external_connector_type = CONN_ACCESS_BUS_USB, + .port_type = TYPE_USB + }, + { + .internal_reference_designator = "USB2", + .internal_connector_type = CONN_NONE, + .external_reference_designator = "USB 2.0 Type-A (Lower)", + .external_connector_type = CONN_ACCESS_BUS_USB, + .port_type = TYPE_USB + }, + { + .internal_reference_designator = "USB2", + .internal_connector_type = CONN_NONE, + .external_reference_designator = "USB 3.2 Gen1 Type-A (Upper)", + .external_connector_type = CONN_ACCESS_BUS_USB, + .port_type = TYPE_USB + }, + { + .internal_reference_designator = "USB2", + .internal_connector_type = CONN_NONE, + .external_reference_designator = "USB 3.2 Gen1 Type-A (Lower)", + .external_connector_type = CONN_ACCESS_BUS_USB, + .port_type = TYPE_USB + }, + { + .internal_reference_designator = "JUSB1 - USB 2.0 ", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_USB + }, + { + .internal_reference_designator = "JUSB2 - USB 2.0", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_USB + }, + { + .internal_reference_designator = "JUSB3 - USB 3.2 GEN 1", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_USB + }, + { + .internal_reference_designator = "JUSB4 - USB 3.2 GEN 1", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_USB + }, + { + .internal_reference_designator = "JUSB5 - USB-C", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_USB + }, + { + .internal_reference_designator = "ATX_PWR1", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_OTHER_PORT + }, + { + .internal_reference_designator = "CPU_PWR1", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_OTHER_PORT + }, + { + .internal_reference_designator = "CPU_PWR2", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_OTHER_PORT + }, +}; + +static int mainboard_smbios_data(struct device *dev, int *handle, unsigned long *current) +{ + int len = 0; + + // add port information + len += smbios_write_type8( + current, handle, + smbios_type8_info, + ARRAY_SIZE(smbios_type8_info) + ); + + return len; +} +#endif + +static void mainboard_enable(struct device *dev) +{ +#if CONFIG(GENERATE_SMBIOS_TABLES) + dev->ops->get_smbios_data = mainboard_smbios_data; +#endif +} + struct chip_operations mainboard_ops = { .init = mainboard_init, .enable_dev = mainboard_enable, -- To view, visit https://review.coreboot.org/c/coreboot/+/64050 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie64be21ff302274769b77550c29e58d4ea1376d1 Gerrit-Change-Number: 64050 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/crb: Add SMBIOS hook to generate type 43 TPM Device
by Michał Żygowski (Code Review) 04 May '22

04 May '22

Attention is currently required from: Christian Walter. Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64049 ) Change subject: drivers/crb: Add SMBIOS hook to generate type 43 TPM Device ...................................................................... drivers/crb: Add SMBIOS hook to generate type 43 TPM Device Example for Alder Lake PTT: Handle 0x004C, DMI type 43, 31 bytes TPM Device Vendor ID: INTC Specification Version: 2.0 Firmware Revision: 600.18 Description: Intel iTPM Characteristics: TPM Device characteristics not supported OEM-specific Information: 0x00000000 TEST=Execute dmidecode and see the tpye 43 is populated with PTT on MSI PRO Z690-A WIFI DDR4 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I05289f98969bd431017aff1aa77be5806d6f1838 --- M src/drivers/crb/tis.c M src/security/tpm/tss/tcg-2.0/tss_structures.h 2 files changed, 95 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/64049/1 diff --git a/src/drivers/crb/tis.c b/src/drivers/crb/tis.c index 800d145..5e1530e 100644 --- a/src/drivers/crb/tis.c +++ b/src/drivers/crb/tis.c @@ -5,6 +5,10 @@ #include <acpi/acpigen.h> #include <device/device.h> #include <drivers/intel/ptt/ptt.h> +#include <security/tpm/tss.h> +#include <endian.h> +#include <smbios.h> +#include <string.h> #include "tpm.h" #include "chip.h" @@ -123,6 +127,89 @@ return "TPM"; } +#if CONFIG(GENERATE_SMBIOS_TABLES) +static int tpm_get_cap(uint32_t property, uint32_t *value) +{ + TPMS_CAPABILITY_DATA cap_data; + int i; + uint32_t status; + + if (!value) + return -1; + + status = tlcl_get_capability(TPM_CAP_TPM_PROPERTIES, property, 1, &cap_data); + + if (status) + return -1; + + for (i = 0 ; i < cap_data.data.tpmProperties.count; i++) { + if (cap_data.data.tpmProperties.tpmProperty[i].property == property) { + *value = cap_data.data.tpmProperties.tpmProperty[i].value; + return 0; + } + } + + return -1; +} + +static int smbios_write_type43_tpm(struct device *dev, int *handle, unsigned long *current) +{ + struct tpm2_info info; + uint32_t tpm_manuf, tpm_family; + uint32_t fw_ver1, fw_ver2; + uint8_t major_spec_ver, minor_spec_ver; + + tpm2_get_info(&info); + + /* If any of these have invalid values, assume TPM not present or disabled */ + if (info.vendor_id == 0 || info.vendor_id == 0xFFFF || + info.device_id == 0 || info.device_id == 0xFFFF) { + printk(BIOS_DEBUG, "%s: Invalid Vendor ID/Device ID\n", __func__); + return 0; + } + + /* Vendor ID is the value returned by TPM2_GetCapabiltiy TPM_PT_MANUFACTURER */ + if (tpm_get_cap(TPM_PT_MANUFACTURER, &tpm_manuf)) { + printk(BIOS_DEBUG, "TPM2_GetCap TPM_PT_MANUFACTURER failed\n"); + return 0; + } + + tpm_manuf = be32toh(tpm_manuf); + + if (tpm_get_cap(TPM_PT_FIRMWARE_VERSION_1, &fw_ver1)) { + printk(BIOS_DEBUG, "TPM2_GetCap TPM_PT_FIRMWARE_VERSION_1 failed\n"); + return 0; + } + + if (tpm_get_cap(TPM_PT_FIRMWARE_VERSION_2, &fw_ver2)) { + printk(BIOS_DEBUG, "TPM2_GetCap TPM_PT_FIRMWARE_VERSION_2 failed\n"); + return 0; + } + + if (tpm_get_cap(TPM_PT_FAMILY_INDICATOR, &tpm_family)) { + printk(BIOS_DEBUG, "TPM2_GetCap TPM_PT_FAMILY_INDICATOR failed\n"); + return 0; + } + + tpm_family = be32toh(tpm_family); + + if (!strncmp((char *)&tpm_family, "2.0", 4)) { + major_spec_ver = 2; + minor_spec_ver = 0; + } else if (!strncmp((char *)&tpm_family, "1.2", 4)) { + major_spec_ver = 1; + minor_spec_ver = 2; + } else { + printk(BIOS_ERR, "%s: Invalid TPM family\n", __func__); + return 0; + } + + return smbios_write_type43(current, handle, tpm_manuf, major_spec_ver, minor_spec_ver, + fw_ver1, fw_ver2, tis_get_dev_name(&info), + SMBIOS_TPM_DEVICE_CHARACTERISTICS_NOT_SUPPORTED, 0); +} +#endif + static struct device_operations __unused crb_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, @@ -130,7 +217,9 @@ .acpi_name = crb_tpm_acpi_name, .acpi_fill_ssdt = crb_tpm_fill_ssdt, #endif - +#if CONFIG(GENERATE_SMBIOS_TABLES) + .get_smbios_data = smbios_write_type43_tpm, +#endif }; static void enable_dev(struct device *dev) diff --git a/src/security/tpm/tss/tcg-2.0/tss_structures.h b/src/security/tpm/tss/tcg-2.0/tss_structures.h index c0e354d..cb02830 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_structures.h +++ b/src/security/tpm/tss/tcg-2.0/tss_structures.h @@ -177,6 +177,11 @@ /* TPM Property capability constants. */ typedef uint32_t TPM_PT; #define PT_GROUP 0x00000100 +#define PT_FIXED (PT_GROUP * 1) +#define TPM_PT_FAMILY_INDICATOR ((TPM_PT)(PT_FIXED + 0)) +#define TPM_PT_MANUFACTURER ((TPM_PT)(PT_FIXED + 5)) +#define TPM_PT_FIRMWARE_VERSION_1 ((TPM_PT)(PT_FIXED + 11)) +#define TPM_PT_FIRMWARE_VERSION_2 ((TPM_PT)(PT_FIXED + 12)) #define PT_VAR (PT_GROUP * 2) #define TPM_PT_PERMANENT ((TPM_PT)(PT_VAR + 0)) -- To view, visit https://review.coreboot.org/c/coreboot/+/64049 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I05289f98969bd431017aff1aa77be5806d6f1838 Gerrit-Change-Number: 64049 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: smbios: Add API to generate SMBIOS type 43 TPM Device
by Michał Żygowski (Code Review) 04 May '22

04 May '22

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64048 ) Change subject: smbios: Add API to generate SMBIOS type 43 TPM Device ...................................................................... smbios: Add API to generate SMBIOS type 43 TPM Device Based on DMTF SMBIOS Specification 3.1.0. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ia2db29f8bc4cfbc6648bb2cabad074d9ea583ca9 --- M src/arch/x86/smbios.c M src/include/smbios.h 2 files changed, 48 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/64048/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index c48ce86..0998bbe 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -1287,6 +1287,29 @@ return len; } +int smbios_write_type43(unsigned long *current, int *handle, const u32 vendor_id, + const u8 major_spec_ver, const u8 minor_spec_ver, + const u32 fw_ver1, const u32 fw_ver2, const char *description, + const u64 characteristics, const u32 oem_defined) +{ + struct smbios_type43 *t = smbios_carve_table(*current, SMBIOS_TPM_DEVICE, + sizeof(*t), *handle); + + t->vendor_id = vendor_id; + t->major_spec_ver = major_spec_ver; + t->minor_spec_ver = minor_spec_ver; + t->fw_ver1 = fw_ver1; + t->fw_ver2 = fw_ver2; + t->characteristics = characteristics; + t->oem_defined = oem_defined; + t->description = smbios_add_string(t->eos, description); + + const int len = smbios_full_table_len(&t->header, t->eos); + *current += len; + *handle += 1; + return len; +} + unsigned long smbios_write_tables(unsigned long current) { struct smbios_entry *se; diff --git a/src/include/smbios.h b/src/include/smbios.h index 4e53771..0210665 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -35,6 +35,11 @@ const char *name, u8 instance, u16 segment, u8 bus, u8 device, u8 function, u8 device_type); +int smbios_write_type43(unsigned long *current, int *handle, const u32 vendor_id, + const u8 major_spec_ver, const u8 minor_spec_ver, + const u32 fw_ver1, const u32 fw_ver2, const char *description, + const u64 characteristics, const u32 oem_defined); + struct device; int get_smbios_data(struct device *dev, int *handle, unsigned long *current); @@ -253,6 +258,7 @@ SMBIOS_SYSTEM_BOOT_INFORMATION = 32, SMBIOS_IPMI_DEVICE_INFORMATION = 38, SMBIOS_ONBOARD_DEVICES_EXTENDED_INFORMATION = 41, + SMBIOS_TPM_DEVICE = 43, SMBIOS_END_OF_TABLE = 127, } smbios_struct_type_t; @@ -970,6 +976,25 @@ u8 eos[2]; } __packed; + +#define SMBIOS_TPM_DEVICE_CHARACTERISTICS_NOT_SUPPORTED (1ULL << 2) +#define SMBIOS_TPM_DEVICE_FAMILY_CONFIGURABLE_VIA_FW_UPD (1ULL << 3) +#define SMBIOS_TPM_DEVICE_FAMILY_CONFIGURABLE_VIA_PLATFORM_SW_SUPPORT (1ULL << 4) +#define SMBIOS_TPM_DEVICE_FAMILY_CONFIGURABLE_VIA_OEM_PROPRIETARY (1ULL << 5) + +struct smbios_type43 { + struct smbios_header header; + u32 vendor_id; + u8 major_spec_ver; + u8 minor_spec_ver; + u32 fw_ver1; + u32 fw_ver2; + u8 description; + u64 characteristics; + u32 oem_defined; + u8 eos[2]; +} __packed; + struct smbios_type127 { struct smbios_header header; u8 eos[2]; -- To view, visit https://review.coreboot.org/c/coreboot/+/64048 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia2db29f8bc4cfbc6648bb2cabad074d9ea583ca9 Gerrit-Change-Number: 64048 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mb/google/brask/variants/moli: fix tcss_usb3 port
by Tim Wawrzynczak (Code Review) 04 May '22

04 May '22

Attention is currently required from: Casper Chang. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64039 ) Change subject: mb/google/brask/variants/moli: fix tcss_usb3 port ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/64039/comment/5a27590d_4bcf70fa PS1, Line 9: proto please try not to mention board phases in public commit messages https://review.coreboot.org/c/coreboot/+/64039/comment/f9382689_0c4415b7 PS1, Line 12: emerge-brask coreboot, extra comma -- To view, visit https://review.coreboot.org/c/coreboot/+/64039 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8faa4a353d8d617fce7aa70922bf027e6e11b38 Gerrit-Change-Number: 64039 Gerrit-PatchSet: 1 Gerrit-Owner: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Attention: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Comment-Date: Wed, 04 May 2022 15:46:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit May 2022