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Change subject: soc/intel/alderlake: Call into PMC IPC to inform PCI enumeration done
......................................................................
Patch Set 1: Code-Review+2
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Change subject: nb/amd/agesa/family14: Avoid caching fx devices
......................................................................
Patch Set 1:
(1 comment)
File src/northbridge/amd/agesa/family14/northbridge.c:
https://review.coreboot.org/c/coreboot/+/64010/comment/a113c528_12028c11
PS1, Line 44: struct device *f1_dev = get_fx_dev(1);
> If the devices are declared in the devicetree, you could also use […]
Oh, nice. I'll look into it.
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Change subject: nb/amd/agesa/family14: Clean up fx_devs stuff
......................................................................
Patch Set 1:
(4 comments)
File src/northbridge/amd/agesa/family14/northbridge.c:
https://review.coreboot.org/c/coreboot/+/64009/comment/2f32e861_44c10b1a
PS1, Line 78: if (fx_devs == 0)
> Not needed anymore.
I'm not sure if fx_devs have been populated when this gets called. In any case, this is dropped in CB:64010
https://review.coreboot.org/c/coreboot/+/64009/comment/0288cc7c_ed4b313a
PS1, Line 86: if (fx_devs == 0)
> Dito.
I'm not sure if fx_devs have been populated when this gets called. In any case, this is dropped in CB:64010
https://review.coreboot.org/c/coreboot/+/64009/comment/dc4499f2_aee701d6
PS1, Line 88: for (i = 0; i < fx_devs; i++) {
> Also not needed anymore.
I'm not sure if fx_devs have been populated when this gets called. In any case, this is dropped in CB:64010
https://review.coreboot.org/c/coreboot/+/64009/comment/13d62836_a1c898c4
PS1, Line 460: base = f1_read_config32(reg);
: limit = f1_read_config32(reg + 0x04);
> NB. […]
I don't know, maybe AGESA did. But it might also be copy-pasta, I haven't checked.
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Change subject: soc/intel/alderlake: Call into PMC IPC to inform PCI enumeration done
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/alderlake/lockdown.c:
https://review.coreboot.org/c/coreboot/+/63954/comment/fc340af7_ff438c2c
PS1, Line 41: /* Send PMC IPC to inform about PCI enumeration done */
: pmc_send_pci_enum_done();
> > I'd expand the comment, stating that FSP doesn't do this.
> >
> > Are there any plans to fix FSP?
>
> I havce raised a ticket for the fix
>
> > I guess we don't care as we won't be using FSP notify on ADL anyway.
>
> Yeah, that is my point as well and MTL has this function implemented in FSP, so we are good.
can we have a CR+2 vote here ?
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Change subject: soc/intel/cmn/blk/pmc: API to inform PMC about PCI enumeration done
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/common/block/pmc/pmclib.c:
https://review.coreboot.org/c/coreboot/+/63953/comment/ab0b9406_1786d049
PS3, Line 799: printk(BIOS_ERR, "PMC: Failed sending PCI Enumeration Done Command\n");
> > What are the consequences, and what should be done in this case? […]
Ack
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Change subject: soc/intel/cmn/blk/pmc: API to inform PMC about PCI enumeration done
......................................................................
Patch Set 3:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63953/comment/f99f3669_64f29be4
PS3, Line 7: soc/intel/cmn/blk/pmc: API to inform PMC about PCI enumeration done
> Please make it a statement by adding a verb in imperative mood: […]
Ack
https://review.coreboot.org/c/coreboot/+/63953/comment/23aa3711_e455d7d6
PS3, Line 10:
> See CB:63954 (the other patch in the train)
marking done as Angel already shared the consumer CL.
File src/soc/intel/common/block/pmc/pmclib.c:
https://review.coreboot.org/c/coreboot/+/63953/comment/4d921e57_4af66a82
PS3, Line 799: printk(BIOS_ERR, "PMC: Failed sending PCI Enumeration Done Command\n");
> What are the consequences, and what should be done in this case?
it's very tough to say as we don't know what PMC does when it doesn't receive this PMC IPC command, for example: so far on ADL FSP, this command was missing and seems like everything is working till date. I believe this is more about informing PMC that we are done with pre-boot phases.
Please let me know if you have some further concerns
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Change subject: soc/intel/fast_spi: Use `need_restore_mtrr()` to clear temp MTRR
......................................................................
Patch Set 2:
(1 comment)
File src/cpu/x86/mtrr/mtrrlib.c:
https://review.coreboot.org/c/coreboot/+/63492/comment/f160da64_4fb21491
PS1, Line 52: /* Need to restore mtrr later using remove_temp_solution. */
: if (ENV_RAMSTAGE)
: need_restore_mtrr();
> Is this still an open? Or can this be merged?
Yes, may be waiting for Arthur to share a feedback.
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63955 )
Change subject: mb/google/brya/var/crota: Enable webcam power
......................................................................
mb/google/brya/var/crota: Enable webcam power
Based on the schematic bernadino 14 adl-p 20220318.pdf to set
GPP_D16 to enable webcam power
BUG=b:230289857
BRANCH=none
TEST=build and notice log kernel v5.10
Signed-off-by: Terry Chen <terry_chen(a)wistron.corp-partner.google.com>
Change-Id: I01c73006d24b00be348655334232bea5eeb312e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63955
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---
M src/mainboard/google/brya/variants/crota/gpio.c
1 file changed, 2 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/crota/gpio.c b/src/mainboard/google/brya/variants/crota/gpio.c
index ee8ee19..a546455 100644
--- a/src/mainboard/google/brya/variants/crota/gpio.c
+++ b/src/mainboard/google/brya/variants/crota/gpio.c
@@ -40,6 +40,8 @@
PAD_NC(GPP_D14, NONE),
/* D15 : ISH_UART0_RTS# ==> NC */
PAD_NC(GPP_D15, NONE),
+ /* D16 : ISH_UART0_CTS# ==> EN_WCAM_PWR */
+ PAD_CFG_GPO_LOCK(GPP_D16, 1, LOCK_CONFIG),
/* D19 : I2S_MCLK1_OUT ==> NC */
PAD_NC(GPP_D19, NONE),
2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
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