Attention is currently required from: Tim Wawrzynczak, Arthur Heymans, Nick Vaccaro, Eric Lai, Werner Zeh.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63492 )
Change subject: soc/intel/fast_spi: Use `need_restore_mtrr()` to clear temp MTRR
......................................................................
Patch Set 2:
(1 comment)
File src/cpu/x86/mtrr/mtrrlib.c:
https://review.coreboot.org/c/coreboot/+/63492/comment/f160da64_4fb21491
PS1, Line 52: /* Need to restore mtrr later using remove_temp_solution. */
: if (ENV_RAMSTAGE)
: need_restore_mtrr();
> Is this still an open? Or can this be merged?
Yes, may be waiting for Arthur to share a feedback.
--
To view, visit https://review.coreboot.org/c/coreboot/+/63492
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I67fd36080b318ace53f3e34da53d747f9a3aa400
Gerrit-Change-Number: 63492
Gerrit-PatchSet: 2
Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com>
Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com>
Gerrit-Comment-Date: Wed, 04 May 2022 13:37:45 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>
Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz>
Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com>
Gerrit-MessageType: comment
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63955 )
Change subject: mb/google/brya/var/crota: Enable webcam power
......................................................................
mb/google/brya/var/crota: Enable webcam power
Based on the schematic bernadino 14 adl-p 20220318.pdf to set
GPP_D16 to enable webcam power
BUG=b:230289857
BRANCH=none
TEST=build and notice log kernel v5.10
Signed-off-by: Terry Chen <terry_chen(a)wistron.corp-partner.google.com>
Change-Id: I01c73006d24b00be348655334232bea5eeb312e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63955
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
---
M src/mainboard/google/brya/variants/crota/gpio.c
1 file changed, 2 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/crota/gpio.c b/src/mainboard/google/brya/variants/crota/gpio.c
index ee8ee19..a546455 100644
--- a/src/mainboard/google/brya/variants/crota/gpio.c
+++ b/src/mainboard/google/brya/variants/crota/gpio.c
@@ -40,6 +40,8 @@
PAD_NC(GPP_D14, NONE),
/* D15 : ISH_UART0_RTS# ==> NC */
PAD_NC(GPP_D15, NONE),
+ /* D16 : ISH_UART0_CTS# ==> EN_WCAM_PWR */
+ PAD_CFG_GPO_LOCK(GPP_D16, 1, LOCK_CONFIG),
/* D19 : I2S_MCLK1_OUT ==> NC */
PAD_NC(GPP_D19, NONE),
2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
--
To view, visit https://review.coreboot.org/c/coreboot/+/63955
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I01c73006d24b00be348655334232bea5eeb312e4
Gerrit-Change-Number: 63955
Gerrit-PatchSet: 5
Gerrit-Owner: Terry Chen <terry_chen(a)wistron.corp-partner.google.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-MessageType: merged
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/64007 )
Change subject: mb/google/brya: Add EC mux device to brya0
......................................................................
mb/google/brya: Add EC mux device to brya0
Add entries to the devicetree override for brya0 and enable the Kconfig
to ensure the Chrome OS EC Mux driver is build tested.
BUG=b:208883648
TEST=None
BRANCH=None
Change-Id: Icf841cd32587f6bd98b15747283b0d331f013532
Signed-off-by: Prashant Malani <pmalani(a)chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64007
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
---
M src/mainboard/google/brya/Kconfig
M src/mainboard/google/brya/variants/brya0/overridetree.cb
2 files changed, 19 insertions(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 6d939ed..8c35ebc 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -21,6 +21,7 @@
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_BOARDID
select EC_GOOGLE_CHROMEEC_ESPI
+ select EC_GOOGLE_CHROMEEC_MUX
select EC_GOOGLE_CHROMEEC_SKUID
select FW_CONFIG
select FW_CONFIG_SOURCE_CHROMEEC_CBI
diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb
index 6f0eb21..c654965 100644
--- a/src/mainboard/google/brya/variants/brya0/overridetree.cb
+++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb
@@ -707,7 +707,24 @@
use conn0 as mux_conn[0]
use conn1 as mux_conn[1]
use conn2 as mux_conn[2]
- device pnp 0c09.0 on end
+ use ecmux0 as retimer_conn[0]
+ use ecmux1 as retimer_conn[1]
+ use ecmux2 as retimer_conn[2]
+ device pnp 0c09.0 on
+ chip ec/google/chromeec/mux
+ device generic 0 on
+ chip ec/google/chromeec/mux/conn
+ device generic 0 alias ecmux0 on end
+ end
+ chip ec/google/chromeec/mux/conn
+ device generic 1 alias ecmux1 on end
+ end
+ chip ec/google/chromeec/mux/conn
+ device generic 2 alias ecmux2 on end
+ end
+ end
+ end
+ end
end
end
device ref pmc hidden
2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
--
To view, visit https://review.coreboot.org/c/coreboot/+/64007
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Icf841cd32587f6bd98b15747283b0d331f013532
Gerrit-Change-Number: 64007
Gerrit-PatchSet: 4
Gerrit-Owner: Prashant Malani <pmalani(a)chromium.org>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: merged
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63793 )
Change subject: ec/google/chromeec: Add retimer handle to Type C conn
......................................................................
ec/google/chromeec: Add retimer handle to Type C conn
Some platforms have retimers which can be configured via the EC. Add a
handle to these retimer devices to the Type C connector device, using
devicetree references.
BUG=b:208883648
TEST=Verify disassembled SSDT on brya.
BRANCH=None
Signed-off-by: Prashant Malani <pmalani(a)chromium.org>
Change-Id: Ic0480b08c6d6a7562cca57192e49b8ea2a33b51e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63793
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
---
M src/acpi/acpigen_usb.c
M src/ec/google/chromeec/chip.h
M src/ec/google/chromeec/ec_acpi.c
M src/include/acpi/acpigen_usb.h
4 files changed, 6 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/acpi/acpigen_usb.c b/src/acpi/acpigen_usb.c
index e32dfc4..e71e6da 100644
--- a/src/acpi/acpigen_usb.c
+++ b/src/acpi/acpigen_usb.c
@@ -106,6 +106,7 @@
add_device_ref(dsd, "orientation-switch", config->orientation_switch);
add_device_ref(dsd, "usb-role-switch", config->usb_role_switch);
add_device_ref(dsd, "mode-switch", config->mode_switch);
+ add_device_ref(dsd, "retimer-switch", config->retimer_switch);
}
void acpigen_write_typec_connector(const struct typec_connector_class_config *config,
diff --git a/src/ec/google/chromeec/chip.h b/src/ec/google/chromeec/chip.h
index 3915cf9..bb03e57 100644
--- a/src/ec/google/chromeec/chip.h
+++ b/src/ec/google/chromeec/chip.h
@@ -11,6 +11,7 @@
struct ec_google_chromeec_config {
/* Pointer to PMC Mux connector for each Type-C port */
DEVTREE_CONST struct device *mux_conn[MAX_TYPEC_PORTS];
+ DEVTREE_CONST struct device *retimer_conn[MAX_TYPEC_PORTS];
};
#endif /* EC_GOOGLE_CHROMEEC_CHIP_H */
diff --git a/src/ec/google/chromeec/ec_acpi.c b/src/ec/google/chromeec/ec_acpi.c
index 7f94626..69b1078 100644
--- a/src/ec/google/chromeec/ec_acpi.c
+++ b/src/ec/google/chromeec/ec_acpi.c
@@ -195,6 +195,7 @@
.orientation_switch = config->mux_conn[i],
.usb_role_switch = config->mux_conn[i],
.mode_switch = config->mux_conn[i],
+ .retimer_switch = config->retimer_conn[i],
.pld = &pld,
};
diff --git a/src/include/acpi/acpigen_usb.h b/src/include/acpi/acpigen_usb.h
index 8042874..b065129 100644
--- a/src/include/acpi/acpigen_usb.h
+++ b/src/include/acpi/acpigen_usb.h
@@ -41,6 +41,8 @@
* host or device, for the USB port
* @mode_switch: Reference to the ACPI device that controls routing of data lines to
* various endpoints (xHCI, DP, etc.) on the SoC.
+ * @retimer_switch: Reference to the ACPI device that controls the configuration
+ * of the retimer in the Type C signal chain.
* @pld: Reference to PLD information.
*/
struct typec_connector_class_config {
@@ -53,6 +55,7 @@
const struct device *orientation_switch;
const struct device *usb_role_switch;
const struct device *mode_switch;
+ const struct device *retimer_switch;
const struct acpi_pld *pld;
};
3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
--
To view, visit https://review.coreboot.org/c/coreboot/+/63793
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ic0480b08c6d6a7562cca57192e49b8ea2a33b51e
Gerrit-Change-Number: 63793
Gerrit-PatchSet: 5
Gerrit-Owner: Prashant Malani <pmalani(a)chromium.org>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Lance Zhao
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-MessageType: merged
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63989 )
Change subject: mb/ocp, soc/intel/xeon_sp: Use common ASL POST defines
......................................................................
mb/ocp, soc/intel/xeon_sp: Use common ASL POST defines
Use common ASL defines for POST code handling.
Change-Id: I5b4c11860a8c33e56edaea0f6de378cbaa63a8c5
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63989
Reviewed-by: Jonathan Zhang <jonzhang(a)fb.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/ocp/deltalake/acpi/platform.asl
M src/mainboard/ocp/tiogapass/acpi/platform.asl
M src/soc/intel/xeon_sp/acpi/iiostack.asl
3 files changed, 3 insertions(+), 15 deletions(-)
Approvals:
build bot (Jenkins): Verified
Lean Sheng Tan: Looks good to me, approved
Jonathan Zhang: Looks good to me, but someone else must approve
Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/ocp/deltalake/acpi/platform.asl b/src/mainboard/ocp/deltalake/acpi/platform.asl
index fa6a451..5a15b29 100644
--- a/src/mainboard/ocp/deltalake/acpi/platform.asl
+++ b/src/mainboard/ocp/deltalake/acpi/platform.asl
@@ -21,13 +21,7 @@
APMS, 8 // APM status
}
-/* Port 80 POST */
-OperationRegion (DBG0, SystemIO, 0x80, 0x02)
-Field (DBG0, ByteAcc, Lock, Preserve)
-{
- IO80, 8,
- IO81, 8
-}
+#include <arch/x86/acpi/post.asl>
/* IO-Trap at 0x800.
* This is the ACPI->SMI communication interface.
diff --git a/src/mainboard/ocp/tiogapass/acpi/platform.asl b/src/mainboard/ocp/tiogapass/acpi/platform.asl
index 9f51fdf..782d2cd 100644
--- a/src/mainboard/ocp/tiogapass/acpi/platform.asl
+++ b/src/mainboard/ocp/tiogapass/acpi/platform.asl
@@ -21,13 +21,7 @@
APMS, 8 // APM status
}
-/* Port 80 POST */
-OperationRegion (DBG0, SystemIO, 0x80, 0x02)
-Field (DBG0, ByteAcc, Lock, Preserve)
-{
- IO80, 8,
- IO81, 8
-}
+#include <arch/x86/acpi/post.asl>
/* IO-Trap at 0x800.
* This is the ACPI->SMI communication interface.
diff --git a/src/soc/intel/xeon_sp/acpi/iiostack.asl b/src/soc/intel/xeon_sp/acpi/iiostack.asl
index 4b2b65b..73f9937 100644
--- a/src/soc/intel/xeon_sp/acpi/iiostack.asl
+++ b/src/soc/intel/xeon_sp/acpi/iiostack.asl
@@ -58,7 +58,7 @@
{ \
/* indicate unrecognized UUID */ \
CDW1 |= 0x04 \
- IO80 = 0xEE \
+ DBG0 = 0xEE \
Return (Arg3) \
} \
} \
--
To view, visit https://review.coreboot.org/c/coreboot/+/63989
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I5b4c11860a8c33e56edaea0f6de378cbaa63a8c5
Gerrit-Change-Number: 63989
Gerrit-PatchSet: 2
Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com>
Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com>
Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com>
Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com>
Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-MessageType: merged