coreboot-gerrit May 2022

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Change in coreboot[master]: mb/google/brya: Add EC mux device to brya0
by Felix Held (Code Review) 04 May '22

04 May '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/64007 ) Change subject: mb/google/brya: Add EC mux device to brya0 ...................................................................... mb/google/brya: Add EC mux device to brya0 Add entries to the devicetree override for brya0 and enable the Kconfig to ensure the Chrome OS EC Mux driver is build tested. BUG=b:208883648 TEST=None BRANCH=None Change-Id: Icf841cd32587f6bd98b15747283b0d331f013532 Signed-off-by: Prashant Malani <pmalani(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64007 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/brya0/overridetree.cb 2 files changed, 19 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 6d939ed..8c35ebc 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -21,6 +21,7 @@ select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_ESPI + select EC_GOOGLE_CHROMEEC_MUX select EC_GOOGLE_CHROMEEC_SKUID select FW_CONFIG select FW_CONFIG_SOURCE_CHROMEEC_CBI diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index 6f0eb21..c654965 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -707,7 +707,24 @@ use conn0 as mux_conn[0] use conn1 as mux_conn[1] use conn2 as mux_conn[2] - device pnp 0c09.0 on end + use ecmux0 as retimer_conn[0] + use ecmux1 as retimer_conn[1] + use ecmux2 as retimer_conn[2] + device pnp 0c09.0 on + chip ec/google/chromeec/mux + device generic 0 on + chip ec/google/chromeec/mux/conn + device generic 0 alias ecmux0 on end + end + chip ec/google/chromeec/mux/conn + device generic 1 alias ecmux1 on end + end + chip ec/google/chromeec/mux/conn + device generic 2 alias ecmux2 on end + end + end + end + end end end device ref pmc hidden 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/64007 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf841cd32587f6bd98b15747283b0d331f013532 Gerrit-Change-Number: 64007 Gerrit-PatchSet: 4 Gerrit-Owner: Prashant Malani <pmalani(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: ec/google/chromeec: Add retimer handle to Type C conn
by Felix Held (Code Review) 04 May '22

04 May '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63793 ) Change subject: ec/google/chromeec: Add retimer handle to Type C conn ...................................................................... ec/google/chromeec: Add retimer handle to Type C conn Some platforms have retimers which can be configured via the EC. Add a handle to these retimer devices to the Type C connector device, using devicetree references. BUG=b:208883648 TEST=Verify disassembled SSDT on brya. BRANCH=None Signed-off-by: Prashant Malani <pmalani(a)chromium.org> Change-Id: Ic0480b08c6d6a7562cca57192e49b8ea2a33b51e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63793 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/acpi/acpigen_usb.c M src/ec/google/chromeec/chip.h M src/ec/google/chromeec/ec_acpi.c M src/include/acpi/acpigen_usb.h 4 files changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/acpi/acpigen_usb.c b/src/acpi/acpigen_usb.c index e32dfc4..e71e6da 100644 --- a/src/acpi/acpigen_usb.c +++ b/src/acpi/acpigen_usb.c @@ -106,6 +106,7 @@ add_device_ref(dsd, "orientation-switch", config->orientation_switch); add_device_ref(dsd, "usb-role-switch", config->usb_role_switch); add_device_ref(dsd, "mode-switch", config->mode_switch); + add_device_ref(dsd, "retimer-switch", config->retimer_switch); } void acpigen_write_typec_connector(const struct typec_connector_class_config *config, diff --git a/src/ec/google/chromeec/chip.h b/src/ec/google/chromeec/chip.h index 3915cf9..bb03e57 100644 --- a/src/ec/google/chromeec/chip.h +++ b/src/ec/google/chromeec/chip.h @@ -11,6 +11,7 @@ struct ec_google_chromeec_config { /* Pointer to PMC Mux connector for each Type-C port */ DEVTREE_CONST struct device *mux_conn[MAX_TYPEC_PORTS]; + DEVTREE_CONST struct device *retimer_conn[MAX_TYPEC_PORTS]; }; #endif /* EC_GOOGLE_CHROMEEC_CHIP_H */ diff --git a/src/ec/google/chromeec/ec_acpi.c b/src/ec/google/chromeec/ec_acpi.c index 7f94626..69b1078 100644 --- a/src/ec/google/chromeec/ec_acpi.c +++ b/src/ec/google/chromeec/ec_acpi.c @@ -195,6 +195,7 @@ .orientation_switch = config->mux_conn[i], .usb_role_switch = config->mux_conn[i], .mode_switch = config->mux_conn[i], + .retimer_switch = config->retimer_conn[i], .pld = &pld, }; diff --git a/src/include/acpi/acpigen_usb.h b/src/include/acpi/acpigen_usb.h index 8042874..b065129 100644 --- a/src/include/acpi/acpigen_usb.h +++ b/src/include/acpi/acpigen_usb.h @@ -41,6 +41,8 @@ * host or device, for the USB port * @mode_switch: Reference to the ACPI device that controls routing of data lines to * various endpoints (xHCI, DP, etc.) on the SoC. + * @retimer_switch: Reference to the ACPI device that controls the configuration + * of the retimer in the Type C signal chain. * @pld: Reference to PLD information. */ struct typec_connector_class_config { @@ -53,6 +55,7 @@ const struct device *orientation_switch; const struct device *usb_role_switch; const struct device *mode_switch; + const struct device *retimer_switch; const struct acpi_pld *pld; }; 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/63793 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0480b08c6d6a7562cca57192e49b8ea2a33b51e Gerrit-Change-Number: 63793 Gerrit-PatchSet: 5 Gerrit-Owner: Prashant Malani <pmalani(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: ec/google/chromeec: Add EC Mux device
by Felix Held (Code Review) 04 May '22

04 May '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63792 ) Change subject: ec/google/chromeec: Add EC Mux device ...................................................................... ec/google/chromeec: Add EC Mux device Introduce an EC Mux ACPI device, which will control retimer and discrete (off-AP) mux configuration. BUG=b:208883648 TEST=None BRANCH=None Change-Id: Ia2022810292783583ee5f09ce29a63b96686dbb8 Signed-off-by: Prashant Malani <pmalani(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63792 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/ec/google/chromeec/Makefile.inc A src/ec/google/chromeec/mux/Kconfig A src/ec/google/chromeec/mux/Makefile.inc A src/ec/google/chromeec/mux/conn/Makefile.inc A src/ec/google/chromeec/mux/conn/conn.c A src/ec/google/chromeec/mux/mux.c 6 files changed, 99 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc index 23e7b3d..f6c53d3 100644 --- a/src/ec/google/chromeec/Makefile.inc +++ b/src/ec/google/chromeec/Makefile.inc @@ -2,6 +2,7 @@ subdirs-y += audio_codec subdirs-y += i2c_tunnel +subdirs-y += mux bootblock-$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDID) += ec_boardid.c verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDID) += ec_boardid.c diff --git a/src/ec/google/chromeec/mux/Kconfig b/src/ec/google/chromeec/mux/Kconfig new file mode 100644 index 0000000..654ff82 --- /dev/null +++ b/src/ec/google/chromeec/mux/Kconfig @@ -0,0 +1,11 @@ +if EC_GOOGLE_CHROMEEC + +config EC_GOOGLE_CHROMEEC_MUX + bool + depends on HAVE_ACPI_TABLES + help + This enables the Cros EC Mux driver that is required to fill the + SSDT nodes for the EC Mux platform device which is used to + configure Type C muxes and retimers. + +endif diff --git a/src/ec/google/chromeec/mux/Makefile.inc b/src/ec/google/chromeec/mux/Makefile.inc new file mode 100644 index 0000000..c4cef75 --- /dev/null +++ b/src/ec/google/chromeec/mux/Makefile.inc @@ -0,0 +1,2 @@ +subdirs-y += conn +ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_MUX) += mux.c diff --git a/src/ec/google/chromeec/mux/conn/Makefile.inc b/src/ec/google/chromeec/mux/conn/Makefile.inc new file mode 100644 index 0000000..1f837ca --- /dev/null +++ b/src/ec/google/chromeec/mux/conn/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_MUX) += conn.c diff --git a/src/ec/google/chromeec/mux/conn/conn.c b/src/ec/google/chromeec/mux/conn/conn.c new file mode 100644 index 0000000..43f5595 --- /dev/null +++ b/src/ec/google/chromeec/mux/conn/conn.c @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpigen.h> + +static const char *conn_acpi_name(const struct device *dev) +{ + static char name[5]; + snprintf(name, sizeof(name), "CON%1X", dev->path.generic.id); + return name; +} + +static void conn_fill_ssdt(const struct device *dev) +{ + const char *name; + name = acpi_device_name(dev); + if (!name) + return; + + acpigen_write_scope(acpi_device_scope(dev)); + acpigen_write_device(name); + + acpigen_write_name_integer("_ADR", dev->path.generic.id); + + acpigen_write_device_end(); + acpigen_write_scope_end(); +} + +static struct device_operations conn_dev_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .acpi_name = conn_acpi_name, + .acpi_fill_ssdt = conn_fill_ssdt, +}; + +static void conn_enable(struct device *dev) +{ + dev->ops = &conn_dev_ops; +} + +struct chip_operations ec_google_chromeec_mux_conn_ops = { + CHIP_NAME("CrosEC Type C Mux device") + .enable_dev = conn_enable, +}; diff --git a/src/ec/google/chromeec/mux/mux.c b/src/ec/google/chromeec/mux/mux.c new file mode 100644 index 0000000..9324d2e --- /dev/null +++ b/src/ec/google/chromeec/mux/mux.c @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpigen.h> + +#define GOOGLE_CHROMEEC_MUX_DEVICE_HID "GOOG001A" +#define GOOGLE_CHROMEEC_MUX_DEVICE_NAME "ECMX" + +static void mux_fill_ssdt(const struct device *dev) +{ + acpigen_write_scope(acpi_device_scope(dev)); + acpigen_write_device(GOOGLE_CHROMEEC_MUX_DEVICE_NAME); + acpigen_write_name_string("_HID", GOOGLE_CHROMEEC_MUX_DEVICE_HID); + acpigen_write_name_string("_DDN", "ChromeOS EC Embedded Controller " + "Mux & Retimer control"); + + acpigen_write_device_end(); + acpigen_write_scope_end(); +} + +static const char *mux_acpi_name(const struct device *dev) +{ + return GOOGLE_CHROMEEC_MUX_DEVICE_NAME; +} + +static struct device_operations mux_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .acpi_name = mux_acpi_name, + .acpi_fill_ssdt = mux_fill_ssdt, + .scan_bus = scan_static_bus, +}; + +static void mux_enable(struct device *dev) +{ + dev->ops = &mux_ops; +} + +struct chip_operations ec_google_chromeec_mux_ops = { + CHIP_NAME("CrosEC Type C Mux device") + .enable_dev = mux_enable +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/63792 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia2022810292783583ee5f09ce29a63b96686dbb8 Gerrit-Change-Number: 63792 Gerrit-PatchSet: 4 Gerrit-Owner: Prashant Malani <pmalani(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: Documentation: Add list of boards maintained on each branch
by Felix Held (Code Review) 04 May '22

04 May '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63797 ) Change subject: Documentation: Add list of boards maintained on each branch ...................................................................... Documentation: Add list of boards maintained on each branch This documents the boards that have been removed from the master branch, and which branch to check out to build or work on them. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: Iee25db13e2c1b0b9131fd2032a26ece45aba4f42 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63797 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- A Documentation/releases/boards_supported_on_branches.md 1 file changed, 326 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved diff --git a/Documentation/releases/boards_supported_on_branches.md b/Documentation/releases/boards_supported_on_branches.md new file mode 100644 index 0000000..08fa689 --- /dev/null +++ b/Documentation/releases/boards_supported_on_branches.md @@ -0,0 +1,326 @@ +# Platforms supported on branches + +For one reason or another, platforms have been deleted from the master +branch at times in the past. Early on, there was no real policy on +removing boards. Now the policy is that boards will only be removed if +they're causing issues in the tree or if they're preventing progress. + +This does not mean that these boards are gone forever. The release or +commit prior to where they were removed can be checked out, and the +boards can still be built there and updated in a release branch if +desired. + +Currently, [jenkins](https://qa.coreboot.org), our continuous +integration system is configured to build the 4.11, 4.12, 4.14, 4.15, +and 4.16 branches. Builders for other branches can be created on +request. Likewise, some releases are only marked with tags, and +branches would need to be created to push new code to. These branches +can also be created on request. + +Patches can be backported from the master branch to any of these other +branches as needed. The coreboot project will take care of backporting +critical security fixes, but other patches will need to handled by +anyone using that release. + +## [4.16 Release](releases/coreboot-4.16-relnotes.md) +Branch created, builder configured + +* No platforms maintained on this release + + +## [4.15 Release](releases/coreboot-4.15-relnotes.md) +Branch created, builder configured + +* No platforms maintained on this release + + +## [4.14 Release](releases/coreboot-4.14-relnotes.md) +Branch created, builder configured + +* No platforms maintained on this release + + +## [4.13 Release](releases/coreboot-4.13-relnotes.md) +Tag only + +| Vendor/Board | Processor | Date added | Brd type | +|-----------------------------|------------------------|------------|----------| +| intel/cannonlake_rvp | INTEL_CANNONLAKE | 2017-07-19 | eval | + + +## [4.12 Release](releases/coreboot-4.12-relnotes.md) + +Branch created, builder configured + +| Vendor/Board | Processor | Date added | Brd type | +|-----------------------------|------------------------|------------|----------| +| bap/ode_e21XX | AMD_PI_00730F01 | 2016-07-30 | eval | +| lippert/toucan-af | AMD_FAMILY14 | 2013-03-02 | half | +| ocp/sonorapass | INTEL_COOPERLAKE_SP | 2020-05-01 | server | + + +## [4.11 Release](releases/coreboot-4.11-relnotes.md) + +Branch created, builder configured + +| Vendor/Board | Processor | Date added | Brd type | +|-----------------------------|------------------------|------------|----------| +| adi/rcc-dff | INTEL_FSP_RANGELEY | 2016-06-08 | eval | +| advansus/a785e-i | AMD_AMDFAM10 | 2011-05-07 | mini | +| amd/bettong | AMD_PI_00660F01 | 2015-06-23 | eval | +| amd/bimini_fam10 | AMD_AMDFAM10 | 2011-01-01 | eval | +| amd/db-ft3b-lc | AMD_PI_00730F01 | 2016-07-20 | eval | +| amd/gardenia | AMD_STONEYRIDGE_FP4 | 2016-12-16 | eval | +| amd/lamar | AMD_PI_00630F01 | 2015-04-23 | eval | +| amd/mahogany_fam10 | AMD_AMDFAM10 | 2010-03-16 | eval | +| amd/olivehillplus | AMD_PI_00730F01 | 2014-09-04 | eval | +| amd/serengeti_cheetah_fam10 | AMD_AMDFAM10 | 2009-10-09 | server | +| amd/tilapia_fam10 | AMD_AMDFAM10 | 2010-04-23 | eval | +| amd/torpedo | AMD_FAMILY12 | 2011-06-28 | eval | +| asus/kcma-d8 | AMD_AMDFAM10 | 2016-02-05 | server | +| asus/kfsn4-dre | AMD_AMDFAM10 | 2015-01-28 | server | +| asus/kgpe-d16 | AMD_AMDFAM10 | 2015-10-28 | server | +| asus/m4a785-m | AMD_AMDFAM10 | 2010-09-13 | desktop | +| asus/m4a785t-m | AMD_AMDFAM10 | 2011-12-02 | desktop | +| asus/m4a78-em | AMD_AMDFAM10 | 2010-12-06 | desktop | +| asus/m5a88-v | AMD_AMDFAM10 | 2011-10-28 | desktop | +| avalue/eax-785e | AMD_AMDFAM10 | 2011-09-14 | desktop | +| esd/atom15 | INTEL_FSP_BAYTRAIL | 2015-12-04 | sbc | +| facebook/watson | INTEL_FSP_BROADWELL_DE | 2018-06-26 | server | +| gigabyte/ma785gm | AMD_AMDFAM10 | 2012-04-23 | desktop | +| gigabyte/ma785gmt | AMD_AMDFAM10 | 2010-08-17 | desktop | +| gigabyte/ma78gm | AMD_AMDFAM10 | 2010-08-17 | desktop | +| google/urara | IMGTEC_PISTACHIO | 2015-03-27 | eval | +| hp/dl165_g6_fam10 | AMD_AMDFAM10 | 2010-09-24 | server | +| iei/kino-780am2-fam10 | AMD_AMDFAM10 | 2010-09-13 | half | +| intel/bayleybay_fsp | INTEL_FSP_BAYTRAIL | 2014-05-30 | eval | +| intel/camelbackmountain_fsp | INTEL_FSP_BROADWELL_DE | 2016-04-15 | eval | +| intel/littleplains | INTEL_FSP_RANGELEY | 2015-11-30 | eval | +| intel/minnowmax | INTEL_FSP_BAYTRAIL | 2014-08-11 | sbc | +| intel/mohonpeak | INTEL_FSP_RANGELEY | 2014-07-30 | eval | +| jetway/pa78vm5 | AMD_AMDFAM10 | 2010-08-17 | desktop | +| msi/ms9652_fam10 | AMD_AMDFAM10 | 2010-03-01 | desktop | +| ocp/monolake | INTEL_FSP_BROADWELL_DE | 2018-05-05 | server | +| ocp/wedge100s | INTEL_FSP_BROADWELL_DE | 2018-05-05 | server | +| opencellular/rotundu | INTEL_FSP_BAYTRAIL | 2018-06-26 | sbc | +| siemens/mc_bdx1 | INTEL_FSP_BROADWELL_DE | 2016-04-29 | misc | +| siemens/mc_tcu3 | INTEL_FSP_BAYTRAIL | 2015-03-05 | misc | +| siemens/mc_tcu3 | INTEL_FSP_BAYTRAIL_MD | 2015-03-05 | misc | +| supermicro/h8dmr_fam10 | AMD_AMDFAM10 | 2009-10-09 | server | +| supermicro/h8qme_fam10 | AMD_AMDFAM10 | 2010-02-03 | server | +| supermicro/h8scm_fam10 | AMD_AMDFAM10 | 2011-03-28 | server | +| tyan/s2912_fam10 | AMD_AMDFAM10 | 2009-10-08 | server | +| via/epia-m850 | VIA_NANO | 2013-06-10 | mini | +| via/epia-m850 | VIA_VX900 | 2013-06-10 | mini | + + +## [4.10 Release](releases/coreboot-4.10-relnotes.md) +Branch created + +| Vendor/Board | Processor | Date added | Brd type | +|-----------------------------|------------------------|------------|----------| +| cubietech/cubieboard | ALLWINNER_A10 | 2014-01-08 | sbc | + + +## [4.9 Release](releases/coreboot-4.9-relnotes.md) +Tag only + +| Vendor/Board | Processor | Date added | Brd type | +|-----------------------------|------------------------|------------|----------| +| pcengines/alix1c | AMD_GEODE_LX | 2009-10-08 | half | +| pcengines/alix1c | AMD_LX | 2009-10-08 | half | +| pcengines/alix2d | AMD_GEODE_LX | 2010-08-31 | half | +| pcengines/alix2d | AMD_LX | 2010-08-31 | half | + + +## [4.8.1 Release](releases/coreboot-4.8.1-relnotes.md) +Branch created + +| Vendor/Board | Processor | Date added | Brd type | +|-----------------------------|------------------------|------------|----------| +| aaeon/pfm-540i_revb | AMD_GEODE_LX | 2011-06-29 | half | +| amd/db800 | AMD_GEODE_LX | 2009-10-09 | eval | +| amd/dbm690t | AMD_AMDK8 | 2009-10-09 | eval | +| amd/f2950 | AMD_GEODE_LX | 2016-07-17 | mini | +| amd/mahogany | AMD_AMDK8 | 2010-03-16 | eval | +| amd/norwich | AMD_GEODE_LX | 2009-10-09 | eval | +| amd/pistachio | AMD_AMDK8 | 2009-10-09 | eval | +| amd/serengeti_cheetah | AMD_AMDK8 | 2009-08-12 | server | +| artecgroup/dbe61 | AMD_GEODE_LX | 2009-10-08 | settop | +| asrock/939a785gmh | AMD_AMDK8 | 2010-04-05 | desktop | +| asus/a8n_e | AMD_AMDK8 | 2009-10-09 | desktop | +| asus/a8v-e_deluxe | AMD_AMDK8 | 2010-11-14 | desktop | +| asus/a8v-e_se | AMD_AMDK8 | 2009-10-09 | desktop | +| asus/k8v-x | AMD_AMDK8 | 2011-12-02 | desktop | +| asus/kfsn4-dre_k8 | AMD_AMDK8 | 2015-10-30 | server | +| asus/m2n-e | AMD_AMDK8 | 2010-12-13 | desktop | +| asus/m2v | AMD_AMDK8 | 2010-11-07 | desktop | +| asus/m2v-mx_se | AMD_AMDK8 | 2009-08-26 | desktop | +| bachmann/ot200 | AMD_GEODE_LX | 2012-07-13 | settop | +| bcom/winnetp680 | VIA_C7 | 2009-10-07 | settop | +| broadcom/blast | AMD_AMDK8 | 2009-10-09 | eval | +| digitallogic/msm800sev | AMD_GEODE_LX | 2009-10-09 | half | +| gigabyte/ga_2761gxdk | AMD_AMDK8 | 2009-10-07 | desktop | +| gigabyte/m57sli | AMD_AMDK8 | 2009-10-03 | desktop | +| google/purin | BROADCOM_CYGNUS | 2015-04-17 | eval | +| google/rotor | MARVELL_MVMAP2315 | 2016-09-13 | laptop | +| google/zoombini | INTEL_CANNONLAKE | 2017-09-28 | laptop | +| hp/dl145_g1 | AMD_AMDK8 | 2010-08-20 | server | +| hp/dl145_g3 | AMD_AMDK8 | 2009-10-09 | server | +| iei/pcisa-lx-800-r10 | AMD_GEODE_LX | 2009-10-08 | half | +| iei/pm-lx2-800-r10 | AMD_GEODE_LX | 2012-10-28 | half | +| iei/pm-lx-800-r11 | AMD_GEODE_LX | 2012-07-06 | half | +| intel/cougar_canyon2 | INTEL_FSP_IVYBRIDGE | 2013-12-04 | eval | +| intel/stargo2 | INTEL_FSP_IVYBRIDGE | 2015-11-10 | eval | +| iwill/dk8_htx | AMD_AMDK8 | 2009-10-09 | server | +| jetway/j7f2 | VIA_C7 | 2014-01-19 | mini | +| kontron/kt690 | AMD_AMDK8 | 2009-10-15 | mini | +| lippert/hurricane-lx | AMD_GEODE_LX | 2010-09-10 | half | +| lippert/literunner-lx | AMD_GEODE_LX | 2010-09-07 | half | +| lippert/roadrunner-lx | AMD_GEODE_LX | 2009-10-08 | half | +| lippert/spacerunner-lx | AMD_GEODE_LX | 2009-10-08 | half | +| lowrisc/nexys4ddr | LOWRISC_LOWRISC | 2016-10-28 | eval | +| msi/ms7135 | AMD_AMDK8 | 2009-10-07 | desktop | +| msi/ms7260 | AMD_AMDK8 | 2009-10-07 | desktop | +| msi/ms9185 | AMD_AMDK8 | 2009-10-07 | server | +| msi/ms9282 | AMD_AMDK8 | 2009-10-07 | server | +| nvidia/l1_2pvv | AMD_AMDK8 | 2009-10-07 | eval | +| siemens/sitemp_g1p1 | AMD_AMDK8 | 2011-05-11 | half | +| sunw/ultra40 | AMD_AMDK8 | 2009-09-25 | desktop | +| sunw/ultra40m2 | AMD_AMDK8 | 2015-11-10 | desktop | +| supermicro/h8dme | AMD_AMDK8 | 2009-09-25 | server | +| supermicro/h8dmr | AMD_AMDK8 | 2009-10-09 | server | +| technexion/tim5690 | AMD_AMDK8 | 2009-10-13 | half | +| technexion/tim8690 | AMD_AMDK8 | 2009-10-08 | half | +| traverse/geos | AMD_GEODE_LX | 2010-05-20 | half | +| tyan/s2912 | AMD_AMDK8 | 2009-10-08 | server | +| via/epia-cn | VIA_C7 | 2009-09-25 | mini | +| via/epia-m700 | VIA_C7 | 2009-09-25 | mini | +| via/pc2500e | VIA_C7 | 2009-09-25 | mini | +| via/vt8454c | VIA_C7 | 2009-08-20 | eval | +| winent/mb6047 | AMD_AMDK8 | 2013-10-19 | half | +| winent/pl6064 | AMD_GEODE_LX | 2010-02-24 | desktop | +| winnet/g170 | VIA_C7 | 2017-08-28 | mini | + + +## [4.7 Release](releases/coreboot-4.7-relnotes.md) +Tag only + +| Vendor/Board | Processor | Date added | Brd type | +|-----------------------------|------------------------|------------|----------| +| abit/be6-ii_v2_0 | INTEL_I440BX | 2009-08-26 | desktop | +| amd/dinar | AMD_FAMILY15 | 2012-02-17 | eval | +| amd/rumba | AMD_GEODE_GX2 | 2009-08-29 | half | +| asus/dsbf | INTEL_I5000 | 2012-07-14 | server | +| asus/mew-am | INTEL_I82810 | 2009-08-28 | desktop | +| asus/mew-vm | INTEL_I82810 | 2009-08-28 | desktop | +| a-trend/atc-6220 | INTEL_I440BX | 2009-08-26 | desktop | +| a-trend/atc-6240 | INTEL_I440BX | 2009-08-26 | desktop | +| azza/pt-6ibd | INTEL_I440BX | 2009-08-26 | desktop | +| biostar/m6tba | INTEL_I440BX | 2009-08-26 | desktop | +| compaq/deskpro_en_sff_p600 | INTEL_I440BX | 2009-08-26 | desktop | +| dmp/vortex86ex | DMP_VORTEX86EX | 2013-07-05 | sbc | +| ecs/p6iwp-fe | INTEL_I82810 | 2010-06-09 | desktop | +| gigabyte/ga-6bxc | INTEL_I440BX | 2009-08-26 | desktop | +| gigabyte/ga-6bxe | INTEL_I440BX | 2010-05-14 | desktop | +| hp/e_vectra_p2706t | INTEL_I82810 | 2009-10-20 | desktop | +| intel/d810e2cb | INTEL_I82810 | 2010-06-21 | desktop | +| intel/eagleheights | INTEL_I3100 | 2009-09-25 | eval | +| intel/mtarvon | INTEL_I3100 | 2009-09-25 | eval | +| intel/truxton | INTEL_I3100 | 2009-09-25 | eval | +| iwave/iWRainbowG6 | INTEL_SCH | 2010-12-18 | half | +| lanner/em8510 | INTEL_I855 | 2010-08-30 | desktop | +| lippert/frontrunner | AMD_GEODE_GX2 | 2009-10-08 | half | +| mitac/6513wu | INTEL_I82810 | 2009-08-28 | desktop | +| msi/ms6119 | INTEL_I440BX | 2009-08-26 | desktop | +| msi/ms6147 | INTEL_I440BX | 2009-08-26 | desktop | +| msi/ms6156 | INTEL_I440BX | 2009-10-13 | desktop | +| msi/ms6178 | INTEL_I82810 | 2009-08-28 | desktop | +| nec/powermate2000 | INTEL_I82810 | 2009-08-28 | desktop | +| nokia/ip530 | INTEL_I440BX | 2010-04-19 | server | +| rca/rm4100 | INTEL_I82830 | 2009-10-07 | settop | +| soyo/sy-6ba-plus-iii | INTEL_I440BX | 2009-08-26 | desktop | +| supermicro/h8qgi | AMD_FAMILY15 | 2011-07-22 | server | +| supermicro/h8scm | AMD_FAMILY15 | 2012-11-30 | server | +| supermicro/x7db8 | INTEL_I5000 | 2012-06-23 | server | +| thomson/ip1000 | INTEL_I82830 | 2009-10-08 | settop | +| tyan/s1846 | INTEL_I440BX | 2009-08-26 | desktop | +| tyan/s8226 | AMD_FAMILY15 | 2012-10-04 | server | +| wyse/s50 | AMD_GEODE_GX2 | 2010-05-08 | settop | + + +## [4.6](releases/coreboot-4.6-relnotes.md) +Tag only + +| Vendor/Board | Processor | Date added | Brd type | +|-----------------------------|------------------------|------------|----------| +| bifferos/bifferboard | RDC_R8610 | 2012-03-27 | half | +| google/cosmos | MARVELL_BG4CD | 2015-04-09 | eval | +| intel/bakersport_fsp | INTEL_FSP_BAYTRAIL | 2014-08-11 | eval | + + +## [4.5](releases/coreboot-4.5-relnotes.md) +Tag only + +| Vendor/Board | Processor | Date added | Brd type | +|-----------------------------|------------------------|------------|----------| +| google/enguarde | INTEL_BAYTRAIL | 2016-09-21 | laptop | +| google/falco | INTEL_HASWELL | 2013-11-25 | laptop | +| google/guado | INTEL_BROADWELL | 2016-01-12 | half | +| google/ninja | INTEL_BAYTRAIL | 2016-05-31 | half | +| google/panther | INTEL_HASWELL | 2014-07-12 | half | +| google/peppy | INTEL_HASWELL | 2013-11-25 | laptop | +| google/rikku | INTEL_BROADWELL | 2016-06-16 | half | +| google/samus | INTEL_BROADWELL | 2014-08-29 | laptop | +| google/tidus | INTEL_BROADWELL | 2016-01-21 | half | + + +## [4.4](releases/coreboot-4.4-relnotes.md) +Branch created + +| Vendor/Board | Processor | Date added | Brd type | +|-----------------------------|------------------------|------------|----------| +| google/bolt | INTEL_HASWELL | 2013-12-12 | eval | +| google/rush | NVIDIA_TEGRA132 | 2015-01-26 | eval | +| google/rush_ryu | NVIDIA_TEGRA132 | 2015-03-05 | eval | +| google/slippy | INTEL_HASWELL | 2013-11-24 | eval | +| intel/amenia | INTEL_APOLLOLAKE | 2016-04-20 | eval | + + +## [4.3](releases/coreboot-4.3-relnotes.md) +Branch created + +* No platforms maintained on this release + + +## [4.2](releases/coreboot-4.2-relnotes.md) +Branch created + +| Vendor/Board | Processor | Date added | Brd type | +|-----------------------------|------------------------|------------|----------| +| arima/hdama | AMD_AMDK8 | 2009-10-09 | server | +| digitallogic/adl855pc | INTEL_I855 | 2009-10-09 | half | +| ibm/e325 | AMD_AMDK8 | 2009-10-09 | server | +| ibm/e326 | AMD_AMDK8 | 2009-10-09 | server | +| intel/sklrvp | INTEL_SKYLAKE | 2015-07-17 | eval | +| iwill/dk8s2 | AMD_AMDK8 | 2009-10-09 | server | +| iwill/dk8x | AMD_AMDK8 | 2009-10-09 | server | +| newisys/khepri | AMD_AMDK8 | 2009-10-07 | server | +| tyan/s2735 | INTEL_E7501 | 2009-10-08 | server | +| tyan/s2850 | AMD_AMDK8 | 2009-09-25 | server | +| tyan/s2875 | AMD_AMDK8 | 2009-09-25 | desktop | +| tyan/s2880 | AMD_AMDK8 | 2009-10-08 | server | +| tyan/s2881 | AMD_AMDK8 | 2009-09-23 | server | +| tyan/s2882 | AMD_AMDK8 | 2009-10-08 | server | +| tyan/s2885 | AMD_AMDK8 | 2009-10-08 | desktop | +| tyan/s2891 | AMD_AMDK8 | 2009-09-22 | server | +| tyan/s2892 | AMD_AMDK8 | 2009-09-22 | server | +| tyan/s2895 | AMD_AMDK8 | 2009-09-22 | desktop | +| tyan/s4880 | AMD_AMDK8 | 2009-10-08 | server | +| tyan/s4882 | AMD_AMDK8 | 2009-10-08 | server | + + +## [4.1](releases/coreboot-4.1-relnotes.md) +Branch Created + +* No platforms maintained on this release -- To view, visit https://review.coreboot.org/c/coreboot/+/63797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee25db13e2c1b0b9131fd2032a26ece45aba4f42 Gerrit-Change-Number: 63797 Gerrit-PatchSet: 4 Gerrit-Owner: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: merged

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Change in coreboot[master]: util/scripts: Add options to update_submodules
by Felix Held (Code Review) 04 May '22

04 May '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60831 ) Change subject: util/scripts: Add options to update_submodules ...................................................................... util/scripts: Add options to update_submodules This extends and adds various options to the update_submodules script. Extensions: - Add help text - Add all options, but specifically allow a single repo to be specified, along with a minimum number of changes instead of being fixed at 10. - Make it a more formal script with main() and functions - Show changes in commit message, unless there are > 65 commits. Options: -c | --changes <#> Specify the minimum number of changes to update a repo -h | --help Print usage and exit -R | --repo <dir> Specify a single repo directory to update -s | --skipsync Assume that repos are already synced -V | --version Print the version and exit This does not fix style issues in the original, which will be fixed in a follow-on commit. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I222103babff7d5f4f8eb02869c598a4e06748a17 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60831 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M util/scripts/update_submodules 1 file changed, 135 insertions(+), 38 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/util/scripts/update_submodules b/util/scripts/update_submodules index 854a943..6b8eb09 100755 --- a/util/scripts/update_submodules +++ b/util/scripts/update_submodules @@ -7,55 +7,152 @@ # number of changes, create a commit to update the submodule to the # new version. +set -eu -o pipefail + +VERSION="1.01" +PROGRAM=$0 +PROGNAME="$(basename "${PROGRAM}")" + export LANG=C export LC_ALL=C export TZ=UTC0 min_commits=10 - TOP=${PWD} SUBMODULES_WITH_UPDATES=0 -submodule_dirs=$(git submodule foreach pwd | grep -v Entering) +submodule_dirs=() +skip_sync="" +max_commits_to_list=65 -( -echo "Checking submodules..." -for submodule in $submodule_dirs; do - cd "$submodule" || exit 1 - initial_commit_id="$(git log --pretty='%h' -n 1)" - initial_commit_description="$(git log --pretty='%ci - (%s)' -n 1)" - git fetch 2>/dev/null - updated_commit_id="$(git log --pretty='%h' -n 1 origin/master)" - updated_commit_description="$(git log --pretty='%ci - (%s)' -n 1 "${updated_commit_id}")" - if [ "${initial_commit_id}" = "${updated_commit_id}" ]; then - # echo "No updates for ${submodule}" - continue +show_version() { + echo "${PROGNAME} version ${VERSION}" + echo +} + +usage() { + echo "Usage: ${PROGNAME} [options]" + echo + echo "Options:" + echo " -c | --changes <#> Specify the minimum number of changes to update a repo" + echo " -h | --help Print usage and exit" + echo " -R | --repo <dir> Specify a single repo directory to update" + echo " -s | --skipsync Assume that repos are already synced" + echo " -V | --version Print the version and exit" + echo +} + +get_args() { + args=$(getopt -l changes:,help,repo:,skipsync,version -o c:hR:sV -- "$@") + getopt_ret=$? + eval set -- "${args}" + + if [ ${getopt_ret} != 0 ]; then + usage + exit 1 fi - SUBMODULES_WITH_UPDATES+=1 - update_count="$(git log --oneline "${initial_commit_id}..${updated_commit_id}" | wc -l)" - echo "${update_count} new commits for ${submodule}" - if [ "${update_count}" -ge "${min_commits}" ]; then - echo "Creating commit to update ${submodule##*/} submodule" - git checkout "${updated_commit_id}" > /dev/null 2>&1 - cd "${TOP}" || exit 1 - sleep 1 - git add "${submodule}" > /dev/null 2>&1 || exit 1 - sleep 1 - git commit -s -F- > /dev/null 2>&1 <<EOF -Update ${submodule##*/} submodule to upstream master -Updating from commit id ${initial_commit_id}: -$initial_commit_description + while true; do + local opt + opt="$1" + shift + case "${opt}" in + -c | --changes) + min_commits="${1}" + shift + ;; + -h | --help) + usage + exit 0 + ;; + -R | --repo) + submodule_dirs=("$(readlink -f "${1}")") + shift + if [[ ! -d "${submodule_dirs[0]}" ]]; then + echo "Error: ${submodule_dirs[0]} is not valid." + usage + exit 1 + fi + ;; + -s | --skipsync) + skip_sync=1 + ;; + -V | --version) + exit 0 + ;; + *) + break + ;; + esac + done +} -to commit id ${updated_commit_id}: -${updated_commit_description} -This brings in ${update_count} new commits. -EOF - sleep 1 +main() { + show_version + get_args "$@" + + if (( ${#submodule_dirs[@]} == 0 )); then + readarray -t submodule_dirs < <(git submodule foreach pwd | grep -v "Entering") fi -done -if [ "${SUBMODULES_WITH_UPDATES}" = "0" ]; then - echo "No submodules with any updates." -fi -) + for submodule in "${submodule_dirs[@]}"; do + echo "Checking submodule ${submodule}" + if ! cd "$submodule"; then + echo "Error: could not cd to $submodule" + exit 1 + fi + + initial_commit_id="$(git log --pretty='%h' -n 1)" + initial_commit_description="$(git log --pretty='%ci - (%s)' -n 1)" + if [[ ${skip_sync} != "1" ]]; then + git fetch 2>/dev/null + fi + + if git branch -a | grep -q "origin/main"; then + branch_name="origin/main" + else + branch_name="origin/master" + fi + + updated_commit_id="$(git log --pretty='%h' -n 1 "${branch_name}" -- )" + updated_commit_description="$(git log --pretty='%ci - (%s)' -n 1 "${updated_commit_id}")" + if [ "${initial_commit_id}" = "${updated_commit_id}" ]; then + echo "No updates for ${submodule}" + continue + fi + SUBMODULES_WITH_UPDATES+=1 + update_log="$(git log --oneline "${initial_commit_id}..${updated_commit_id}")" + update_count="$(echo "${update_log}" | wc -l)" + if [[ "${update_count}" -gt "${max_commits_to_list}" ]]; then + update_log="" + new_commit_terminator="." + else + new_commit_terminator=":" + fi + echo "${update_count} new commits for ${submodule}" + if [ "${update_count}" -ge "${min_commits}" ]; then + echo "Creating commit to update ${submodule##*/} submodule" + git checkout "${updated_commit_id}" > /dev/null 2>&1 + cd "${TOP}" || exit 1 + git add "${submodule}" > /dev/null 2>&1 || exit 1 + git commit -s -F- > /dev/null 2>&1 <<-EOF + Update ${submodule##*/} submodule to upstream master + + Updating from commit id ${initial_commit_id}: + $initial_commit_description + + to commit id ${updated_commit_id}: + ${updated_commit_description} + + This brings in ${update_count} new commits${new_commit_terminator} + ${update_log} + EOF + fi + done + + if [ "${SUBMODULES_WITH_UPDATES}" = "0" ]; then + echo "No submodules with any updates." + fi +} + +main "$@" -- To view, visit https://review.coreboot.org/c/coreboot/+/60831 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I222103babff7d5f4f8eb02869c598a4e06748a17 Gerrit-Change-Number: 60831 Gerrit-PatchSet: 7 Gerrit-Owner: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/ocp, soc/intel/xeon_sp: Use common ASL POST defines
by Felix Held (Code Review) 04 May '22

04 May '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63989 ) Change subject: mb/ocp, soc/intel/xeon_sp: Use common ASL POST defines ...................................................................... mb/ocp, soc/intel/xeon_sp: Use common ASL POST defines Use common ASL defines for POST code handling. Change-Id: I5b4c11860a8c33e56edaea0f6de378cbaa63a8c5 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63989 Reviewed-by: Jonathan Zhang <jonzhang(a)fb.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/ocp/deltalake/acpi/platform.asl M src/mainboard/ocp/tiogapass/acpi/platform.asl M src/soc/intel/xeon_sp/acpi/iiostack.asl 3 files changed, 3 insertions(+), 15 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved Jonathan Zhang: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/ocp/deltalake/acpi/platform.asl b/src/mainboard/ocp/deltalake/acpi/platform.asl index fa6a451..5a15b29 100644 --- a/src/mainboard/ocp/deltalake/acpi/platform.asl +++ b/src/mainboard/ocp/deltalake/acpi/platform.asl @@ -21,13 +21,7 @@ APMS, 8 // APM status } -/* Port 80 POST */ -OperationRegion (DBG0, SystemIO, 0x80, 0x02) -Field (DBG0, ByteAcc, Lock, Preserve) -{ - IO80, 8, - IO81, 8 -} +#include <arch/x86/acpi/post.asl> /* IO-Trap at 0x800. * This is the ACPI->SMI communication interface. diff --git a/src/mainboard/ocp/tiogapass/acpi/platform.asl b/src/mainboard/ocp/tiogapass/acpi/platform.asl index 9f51fdf..782d2cd 100644 --- a/src/mainboard/ocp/tiogapass/acpi/platform.asl +++ b/src/mainboard/ocp/tiogapass/acpi/platform.asl @@ -21,13 +21,7 @@ APMS, 8 // APM status } -/* Port 80 POST */ -OperationRegion (DBG0, SystemIO, 0x80, 0x02) -Field (DBG0, ByteAcc, Lock, Preserve) -{ - IO80, 8, - IO81, 8 -} +#include <arch/x86/acpi/post.asl> /* IO-Trap at 0x800. * This is the ACPI->SMI communication interface. diff --git a/src/soc/intel/xeon_sp/acpi/iiostack.asl b/src/soc/intel/xeon_sp/acpi/iiostack.asl index 4b2b65b..73f9937 100644 --- a/src/soc/intel/xeon_sp/acpi/iiostack.asl +++ b/src/soc/intel/xeon_sp/acpi/iiostack.asl @@ -58,7 +58,7 @@ { \ /* indicate unrecognized UUID */ \ CDW1 |= 0x04 \ - IO80 = 0xEE \ + DBG0 = 0xEE \ Return (Arg3) \ } \ } \ -- To view, visit https://review.coreboot.org/c/coreboot/+/63989 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b4c11860a8c33e56edaea0f6de378cbaa63a8c5 Gerrit-Change-Number: 63989 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: arch/x86/acpi: Consolidate POST code handling
by Felix Held (Code Review) 04 May '22

04 May '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63988 ) Change subject: arch/x86/acpi: Consolidate POST code handling ...................................................................... arch/x86/acpi: Consolidate POST code handling Move ASL POST code declarations into a common file to avoid redundancy. Also, provide a dummy implementation when `POST_IO` is not enabled, as the value of `CONFIG_POST_IO_PORT` can't be used. Change-Id: I891bd8754f10f16d618e76e1ab88c26164776a50 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63988 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- A src/arch/x86/acpi/post.asl M src/mainboard/asus/p2b/dsdt.asl M src/mainboard/intel/cedarisland_crb/acpi/platform.asl M src/soc/intel/common/acpi/platform.asl M src/southbridge/intel/common/acpi/platform.asl 5 files changed, 21 insertions(+), 28 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/arch/x86/acpi/post.asl b/src/arch/x86/acpi/post.asl new file mode 100644 index 0000000..dbdc681 --- /dev/null +++ b/src/arch/x86/acpi/post.asl @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#if CONFIG(POST_IO) + +/* POST code support, typically on port 80 */ +OperationRegion (POST, SystemIO, CONFIG_POST_IO_PORT, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +#else + +/* Dummy placeholder to avoid issues */ +Name (DBG0, 0) + +#endif diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl index 25515d2..5d53c1d 100644 --- a/src/mainboard/asus/p2b/dsdt.asl +++ b/src/mainboard/asus/p2b/dsdt.asl @@ -22,13 +22,7 @@ #include <acpi/dsdt_top.asl> /* \_SB scope defining the main processor is generated in SSDT. */ - /* Port 80 POST */ - - OperationRegion (POST, SystemIO, 0x80, 1) - Field (POST, ByteAcc, Lock, Preserve) - { - DBG0, 8 - } + #include <arch/x86/acpi/post.asl> /* * Intel 82371EB (PIIX4E) datasheet, section 7.2.3, page 142 diff --git a/src/mainboard/intel/cedarisland_crb/acpi/platform.asl b/src/mainboard/intel/cedarisland_crb/acpi/platform.asl index 3bebbff..5f7ffbb 100644 --- a/src/mainboard/intel/cedarisland_crb/acpi/platform.asl +++ b/src/mainboard/intel/cedarisland_crb/acpi/platform.asl @@ -9,13 +9,7 @@ APMS, 8 // APM status } -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} +#include <arch/x86/acpi/post.asl> Name(\APC1, Zero) // IIO IOAPIC diff --git a/src/soc/intel/common/acpi/platform.asl b/src/soc/intel/common/acpi/platform.asl index 3bb2f53..c988e0a 100644 --- a/src/soc/intel/common/acpi/platform.asl +++ b/src/soc/intel/common/acpi/platform.asl @@ -7,13 +7,7 @@ External(\_SB.PCI0.EGPM, MethodObj) External(\_SB.PCI0.RGPM, MethodObj) -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, CONFIG_POST_IO_PORT, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} +#include <arch/x86/acpi/post.asl> /* * The _PTS method (Prepare To Sleep) is called before the OS is diff --git a/src/southbridge/intel/common/acpi/platform.asl b/src/southbridge/intel/common/acpi/platform.asl index ec7d680..e044f04 100644 --- a/src/southbridge/intel/common/acpi/platform.asl +++ b/src/southbridge/intel/common/acpi/platform.asl @@ -9,13 +9,7 @@ APMS, 8 // APM status } -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} +#include <arch/x86/acpi/post.asl> #if CONFIG(ACPI_SOC_NVS) /* SMI I/O Trap */ -- To view, visit https://review.coreboot.org/c/coreboot/+/63988 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I891bd8754f10f16d618e76e1ab88c26164776a50 Gerrit-Change-Number: 63988 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/asus/p2b/dsdt.asl: Align POST code ASL stuff
by Felix Held (Code Review) 04 May '22

04 May '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63987 ) Change subject: mb/asus/p2b/dsdt.asl: Align POST code ASL stuff ...................................................................... mb/asus/p2b/dsdt.asl: Align POST code ASL stuff Align POST code ASL elements with existing code in newer southbridges. The main differences are that `NoLock` is changed to `Lock`, and that names have been changed. The lock type change should not be a problem because the field is only used once in the _PTS method. Change-Id: I8aa362007ff98e5b42add6c7908a8f7beac2222b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63987 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- M src/mainboard/asus/p2b/dsdt.asl 1 file changed, 6 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl index 2c88cf6..25515d2 100644 --- a/src/mainboard/asus/p2b/dsdt.asl +++ b/src/mainboard/asus/p2b/dsdt.asl @@ -22,10 +22,12 @@ #include <acpi/dsdt_top.asl> /* \_SB scope defining the main processor is generated in SSDT. */ - OperationRegion(X80, SystemIO, 0x80, 1) - Field(X80, ByteAcc, NoLock, Preserve) + /* Port 80 POST */ + + OperationRegion (POST, SystemIO, 0x80, 1) + Field (POST, ByteAcc, Lock, Preserve) { - P80, 8 + DBG0, 8 } /* @@ -77,7 +79,7 @@ /* Arms SMI for device 12 */ TO12 = 1 /* Put out a POST code */ - P80 = Arg0 | 0xF0 + DBG0 = Arg0 | 0xF0 } Method (\_WAK, 1, NotSerialized) -- To view, visit https://review.coreboot.org/c/coreboot/+/63987 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8aa362007ff98e5b42add6c7908a8f7beac2222b Gerrit-Change-Number: 63987 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: arch/x86/acpi/debug.asl: Drop POST code stuff
by Felix Held (Code Review) 04 May '22

04 May '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63986 ) Change subject: arch/x86/acpi/debug.asl: Drop POST code stuff ...................................................................... arch/x86/acpi/debug.asl: Drop POST code stuff To pave the way for future refactoring commits, drop POST code elements from the debug.asl file. Only msi/ms7721 includes debug.asl and it does not use any of it anyway. Change-Id: Icd73e5c1f700fd7e735bed1668f02da8f9a3adf3 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63986 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/arch/x86/acpi/debug.asl 1 file changed, 0 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/arch/x86/acpi/debug.asl b/src/arch/x86/acpi/debug.asl index cee85e5..fe71b3e 100644 --- a/src/arch/x86/acpi/debug.asl +++ b/src/arch/x86/acpi/debug.asl @@ -1,10 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* -* 0x80: POST_BASE * 0x3F8: DEBCOM_BASE -* X80: POST_REGION -* P80: PORT80 * * CREG: DEBCOM_REGION * CUAR: DEBCOM_UART @@ -17,12 +14,6 @@ * DEBUG_INIT DINI */ -OperationRegion(X80, SystemIO, 0x80, 1) - Field(X80, ByteAcc, NoLock, Preserve) -{ - P80, 8 -} - OperationRegion(CREG, SystemIO, 0x3F8, 8) Field(CREG, ByteAcc, NoLock, Preserve) { -- To view, visit https://review.coreboot.org/c/coreboot/+/63986 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd73e5c1f700fd7e735bed1668f02da8f9a3adf3 Gerrit-Change-Number: 63986 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: Add SBOM (Software Bill of Materials) Generation
by Maximilian Brune (Code Review) 04 May '22

04 May '22

1 0

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