coreboot-gerrit May 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: drivers/phy/m88e1512: Add new driver for Marvell PHY 88E1512
by Mario Scheithauer (Code Review) 04 May '22

04 May '22

Attention is currently required from: Paul Menzel, Mario Scheithauer, Werner Zeh. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/64024 to look at the new patch set (#4). Change subject: drivers/phy/m88e1512: Add new driver for Marvell PHY 88E1512 ...................................................................... drivers/phy/m88e1512: Add new driver for Marvell PHY 88E1512 This driver enables the usage of an external Marvell PHY 88E1512 which should be connected to a SOC internal MAC controller. In a first step it is only the framework of the driver. Functionality will follow with a second patch. Link to the Marvell PHY 88E1512 datasheet: https://www.marvell.com/content/dam/marvell/en/public-collateral/transceive… Change-Id: Iabe1aef2217dfaee4b5a4bd83782ab588d4be642 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- A src/drivers/phy/m88e1512/Kconfig A src/drivers/phy/m88e1512/Makefile.inc A src/drivers/phy/m88e1512/m88e1512.c 3 files changed, 31 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/64024/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/64024 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabe1aef2217dfaee4b5a4bd83782ab588d4be642 Gerrit-Change-Number: 64024 Gerrit-PatchSet: 4 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/siemens/mc_ehl2: Invert PHY IRQ from falling edge to rising edge
by Mario Scheithauer (Code Review) 04 May '22

04 May '22

Attention is currently required from: Werner Zeh. Hello build bot (Jenkins), Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63889 to look at the new patch set (#5). Change subject: mb/siemens/mc_ehl2: Invert PHY IRQ from falling edge to rising edge ...................................................................... mb/siemens/mc_ehl2: Invert PHY IRQ from falling edge to rising edge There are three external Marvel PHY 88E1512 on this mainboard. The PHY IRQ comes with a falling edge but the EHL MAC side needs a rising edge signal. For that reason, we need an inversion of the IRQ polarity. Change-Id: Id3caf582b4434b046779f5733e6ad9b57528ce35 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/63889/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/63889 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3caf582b4434b046779f5733e6ad9b57528ce35 Gerrit-Change-Number: 63889 Gerrit-PatchSet: 5 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/ehl: Provide function to change PHY-to-MAC IRQ polarity
by Mario Scheithauer (Code Review) 04 May '22

04 May '22

Attention is currently required from: Paul Menzel, Werner Zeh. Hello build bot (Jenkins), Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63888 to look at the new patch set (#5). Change subject: soc/intel/ehl: Provide function to change PHY-to-MAC IRQ polarity ...................................................................... soc/intel/ehl: Provide function to change PHY-to-MAC IRQ polarity EHL MAC side expects a rising edge signal for an IRQ. Based on the mainboard wiring it could be necessary to change the interrupt polarity. This patch provides the functionality to invert a falling edge signal that comes from an external PHY. Change-Id: Ia314014c7cacbeb72629c773c8c0bb5f002a3f54 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/soc/intel/elkhartlake/chip.h M src/soc/intel/elkhartlake/include/soc/tsn_gbe.h M src/soc/intel/elkhartlake/tsn_gbe.c 3 files changed, 121 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/63888/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/63888 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia314014c7cacbeb72629c773c8c0bb5f002a3f54 Gerrit-Change-Number: 63888 Gerrit-PatchSet: 5 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Add SBOM (Software Bill of Materials) Generation
by Maximilian Brune (Code Review) 04 May '22

04 May '22

Attention is currently required from: Nico Huber, Martin L Roth. Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63639 ) Change subject: Add SBOM (Software Bill of Materials) Generation ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/63639 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb7481d4903f95d200eddbfed7728fbec51819d0 Gerrit-Change-Number: 63639 Gerrit-PatchSet: 14 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Christian Walter <christian.walter(a)9elements.com> Gerrit-CC: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <martinroth(a)google.com> Gerrit-Comment-Date: Wed, 04 May 2022 12:05:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/tgl-u: Add Clevo NV4x Tiger Lake laptop support
by Michał Kopeć (Code Review) 04 May '22

04 May '22

Attention is currently required from: Felix Singer, Michał Żygowski, Angel Pons, Michael Niewöhner. Michał Kopeć has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62498 ) Change subject: mb/clevo/tgl-u: Add Clevo NV4x Tiger Lake laptop support ...................................................................... Patch Set 6: (31 comments) Patchset: PS6: Rebased on master, where the correct `clevo/tgl-u` structure is already present. File src/mainboard/clevo/tgl-u/Kconfig: https://review.coreboot.org/c/coreboot/+/62498/comment/efae5f71_a46f450e PS3, Line 14: select NO_UART_ON_SUPERIO > Shouldn't be needed, selecting `INTEL_LPSS_UART_FOR_CONSOLE` should already provide the necessary im […] File removed https://review.coreboot.org/c/coreboot/+/62498/comment/46e7143f_7c412a56 PS3, Line 20: select HAVE_SMI_HANDLER > SoC already selects this File removed https://review.coreboot.org/c/coreboot/+/62498/comment/960893b9_f82e7519 PS3, Line 22: select TPM_MEASURED_BOOT > Why is it necessary to force people to use measured boot? This option is user-configurable, selectin […] File removed https://review.coreboot.org/c/coreboot/+/62498/comment/03986fb8_fbf7bc2a PS3, Line 25: bool "NV4x" > Why does this have a prompt? You can simply omit the line, the type only needs to be specified once […] Prompt removed https://review.coreboot.org/c/coreboot/+/62498/comment/e19327b6_aa632108 PS3, Line 32: string > Type not needed Removed https://review.coreboot.org/c/coreboot/+/62498/comment/5e02c307_8967a233 PS3, Line 36: string > Type not needed Removed https://review.coreboot.org/c/coreboot/+/62498/comment/71c36132_fed960fe PS3, Line 40: string > Type not needed Option removed https://review.coreboot.org/c/coreboot/+/62498/comment/8a239bb1_f3b6985e PS3, Line 43: config MAX_CPUS : int : default 8 > Is this actually needed? Removed https://review.coreboot.org/c/coreboot/+/62498/comment/d0f7c048_c3740be9 PS3, Line 47: config PCIEXP_HOTPLUG : default y > Redundant, given the select statement at the start of the file. Removed https://review.coreboot.org/c/coreboot/+/62498/comment/98fc6ccf_9f0de31c PS3, Line 50: config PCIEXP_HOTPLUG_BUSES : int : default 42 : : config PCIEXP_HOTPLUG_MEM : hex : default 0xc200000 # 194 MiB : : config PCIEXP_HOTPLUG_PREFETCH_MEM : hex : default 0x1c00000 # 448 MiB > Where do these numbers come from? Removed https://review.coreboot.org/c/coreboot/+/62498/comment/65b6a543_52918f75 PS3, Line 63: string > Type not needed Removed https://review.coreboot.org/c/coreboot/+/62498/comment/857dd132_3d0b6b9c PS3, Line 67: string > Type not needed Removed https://review.coreboot.org/c/coreboot/+/62498/comment/cb4cef49_631d83f6 PS3, Line 70: config DIMM_MAX : int : default 4 # Hack to make soc code work > Huh? Removed https://review.coreboot.org/c/coreboot/+/62498/comment/98be4572_ac928063 PS3, Line 75: int > Type probably not needed Removed https://review.coreboot.org/c/coreboot/+/62498/comment/6cdf3e8b_f3dc5af6 PS3, Line 90: string > Type not needed Removed File src/mainboard/clevo/tgl-u/board.fmd: PS1: > Nothing special here. All handled automatically by build system. Michał you can remove the file. Removed File src/mainboard/clevo/tgl-u/bootblock.c: https://review.coreboot.org/c/coreboot/+/62498/comment/ed911ba3_5394eb6a PS1, Line 16: if (onoff) { : gpio_set(DGPU_RST_N, 0); : mdelay(4); : gpio_set(DGPU_PWR_EN, 1); : mdelay(4); : gpio_set(DGPU_RST_N, 1); : } else { : gpio_set(DGPU_RST_N, 0); : mdelay(4); : gpio_set(DGPU_PWR_EN, 0); > the gpios might be mb specific; we still have APIs to handle that in a generic way Removed File src/mainboard/clevo/tgl-u/bootblock.c: https://review.coreboot.org/c/coreboot/+/62498/comment/b6798d58_c71feff2 PS3, Line 14: int > Why not `bool`? Removed - for now, until the nvidia driver is completed https://review.coreboot.org/c/coreboot/+/62498/comment/0c22a704_975e8a37 PS3, Line 14: static void dgpu_power_enable(int onoff) { > > open brace '{' following function definitions go on the next line […] Fixed https://review.coreboot.org/c/coreboot/+/62498/comment/59c60cd2_75468187 PS3, Line 15: %d > I'd use `%s` and print `onoff ? "on" : "off"` Removed File src/mainboard/clevo/tgl-u/cmos.layout: https://review.coreboot.org/c/coreboot/+/62498/comment/dc69a9a1_11d686bf PS3, Line 11: #395 4 e 3 debug_level > Why is this commented out? Removed https://review.coreboot.org/c/coreboot/+/62498/comment/6ec7d02c_fedfc614 PS3, Line 12: 408 1 h 1 preserve_smmstore > What does this do? Removed File src/mainboard/clevo/tgl-u/dsdt.asl: https://review.coreboot.org/c/coreboot/+/62498/comment/90e4167a_fbb4aee0 PS3, Line 4: #include <baseboard/gpio.h> > Is it possible to include this from the file that needs it? File removed https://review.coreboot.org/c/coreboot/+/62498/comment/7c5193eb_478356d9 PS3, Line 12: /* OEM revision */ > Is it, though? Removed https://review.coreboot.org/c/coreboot/+/62498/comment/d32de6df_c37bdbd7 PS3, Line 36: // Mainboard specific > Redundant comment, please kill with fire Killed File src/mainboard/clevo/tgl-u/memory.c: PS1: > Rename this file to romstage. […] Done File src/mainboard/clevo/tgl-u/romstage.c: PS1: > Move this file to variant/nv4x/ Moved File src/mainboard/clevo/tgl-u/romstage.c: https://review.coreboot.org/c/coreboot/+/62498/comment/ad05e6ef_6b1c3b5a PS3, Line 33: const uint8_t vtd = get_uint_option("vtd", 1); : memupd->FspmConfig.VtdDisable = !vtd; : : const uint8_t ht = get_uint_option("hyper_threading", : memupd->FspmConfig.HyperThreading); : memupd->FspmConfig.HyperThreading = ht; > I don't see these in cmos. […] Copy-paste error. Removed File src/mainboard/clevo/tgl-u/variants/baseboard/devicetree.cb: PS1: > +1, the concept of `variants/baseboard` gives me aneurysms. Removed `baseboard` dir File src/mainboard/clevo/tgl-u/variants/baseboard/include/baseboard/variants.h: PS1: > Same here. Move the include folder to mainboard/clevo/tgl-u. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib373d62d9d18bafdfde2e1acb4e00e3a20ae09bc Gerrit-Change-Number: 62498 Gerrit-PatchSet: 6 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Wed, 04 May 2022 11:45:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/tgl-u: Add Clevo NV4x Tiger Lake laptop support
by Michał Kopeć (Code Review) 04 May '22

04 May '22

Attention is currently required from: Felix Singer, Michał Żygowski, Michał Kopeć, Angel Pons. Hello Felix Singer, build bot (Jenkins), Michał Żygowski, Michael Niewöhner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62498 to look at the new patch set (#6). Change subject: mb/clevo/tgl-u: Add Clevo NV4x Tiger Lake laptop support ...................................................................... mb/clevo/tgl-u: Add Clevo NV4x Tiger Lake laptop support Change-Id: Ib373d62d9d18bafdfde2e1acb4e00e3a20ae09bc Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M src/mainboard/clevo/tgl-u/Kconfig M src/mainboard/clevo/tgl-u/Kconfig.name A src/mainboard/clevo/tgl-u/variants/nv40mz/Makefile.inc A src/mainboard/clevo/tgl-u/variants/nv40mz/board_info.txt A src/mainboard/clevo/tgl-u/variants/nv40mz/data.vbt A src/mainboard/clevo/tgl-u/variants/nv40mz/devicetree.cb A src/mainboard/clevo/tgl-u/variants/nv40mz/gpio.c A src/mainboard/clevo/tgl-u/variants/nv40mz/gpio_early.c A src/mainboard/clevo/tgl-u/variants/nv40mz/hda_verb.c A src/mainboard/clevo/tgl-u/variants/nv40mz/ramstage.c A src/mainboard/clevo/tgl-u/variants/nv40mz/romstage.c 11 files changed, 700 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/62498/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/62498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib373d62d9d18bafdfde2e1acb4e00e3a20ae09bc Gerrit-Change-Number: 62498 Gerrit-PatchSet: 6 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/cmn/spi: Add ACPI SSDT extension for fast SPI
by Werner Zeh (Code Review) 04 May '22

04 May '22

Attention is currently required from: Nico Huber, Subrata Banik, Paul Menzel, Arthur Heymans. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63982 ) Change subject: soc/intel/cmn/spi: Add ACPI SSDT extension for fast SPI ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/spi/spi.c: https://review.coreboot.org/c/coreboot/+/63982/comment/7138cbf2_cf931d62 PS1, Line 117: spi_fill_ssdt > Right, we mustn't add a device with _HID if there is a discoverable > PCI device. OK, agree. And yes, APL is kind of different here as the policy is to hide this device, which is hard coded and not bound to a config switch or the like. Even checking for the availability is not doable here as at the time of PCI enumeration the SPI controller _is_ visible. It will be hidden later. -- To view, visit https://review.coreboot.org/c/coreboot/+/63982 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa89cdf41f42d4df5b46f095e22924157d9f3c3f Gerrit-Change-Number: 63982 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 04 May 2022 11:08:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: payloads: Update GRUB2 stable version from 2.04 to 2.06
by Paul Menzel (Code Review) 04 May '22

04 May '22

Attention is currently required from: Martin L Roth, Stefan Reinauer. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55343 ) Change subject: payloads: Update GRUB2 stable version from 2.04 to 2.06 ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Nico and Kyösti analyzed the issue in #coreboot(a)irc.libera.chat. The bug seems to be in GRUB’s mkimage. mkimage and the linking seem to disagree if the entry point should be at a fixed location. Unfortunately, the code is supposedly hard to read. -- To view, visit https://review.coreboot.org/c/coreboot/+/55343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I050a78c769c3cd4c9ae627c7e3124a4894a018d7 Gerrit-Change-Number: 55343 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <martinroth(a)google.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Wed, 04 May 2022 11:08:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Hook up FSP hyper-threading setting to option API
by Nico Huber (Code Review) 04 May '22

04 May '22

Attention is currently required from: Felix Singer, Michael Niewöhner. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60542 ) Change subject: soc/intel/skylake: Hook up FSP hyper-threading setting to option API ...................................................................... Patch Set 3: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/60542/comment/f459bc80_b56ab15c PS2, Line 15: obsolete now. > Done The code you remove is different. That should be mentioned. -- To view, visit https://review.coreboot.org/c/coreboot/+/60542 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1023d1b94acb63f30455c56b394b68059deaaa16 Gerrit-Change-Number: 60542 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Wed, 04 May 2022 10:57:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Hook up FSP hyper-threading setting to option API
by Nico Huber (Code Review) 04 May '22

04 May '22

Attention is currently required from: Felix Singer, Michael Niewöhner. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60544 ) Change subject: soc/intel/cannonlake: Hook up FSP hyper-threading setting to option API ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60544 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I173b87da5ce76549672c50ba30204cd77be8b82f Gerrit-Change-Number: 60544 Gerrit-PatchSet: 10 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Wed, 04 May 2022 10:55:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit May 2022