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Hello Felix Singer, build bot (Jenkins), Michał Żygowski, Michael Niewöhner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/62498
to look at the new patch set (#6).
Change subject: mb/clevo/tgl-u: Add Clevo NV4x Tiger Lake laptop support
......................................................................
mb/clevo/tgl-u: Add Clevo NV4x Tiger Lake laptop support
Change-Id: Ib373d62d9d18bafdfde2e1acb4e00e3a20ae09bc
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
---
M src/mainboard/clevo/tgl-u/Kconfig
M src/mainboard/clevo/tgl-u/Kconfig.name
A src/mainboard/clevo/tgl-u/variants/nv40mz/Makefile.inc
A src/mainboard/clevo/tgl-u/variants/nv40mz/board_info.txt
A src/mainboard/clevo/tgl-u/variants/nv40mz/data.vbt
A src/mainboard/clevo/tgl-u/variants/nv40mz/devicetree.cb
A src/mainboard/clevo/tgl-u/variants/nv40mz/gpio.c
A src/mainboard/clevo/tgl-u/variants/nv40mz/gpio_early.c
A src/mainboard/clevo/tgl-u/variants/nv40mz/hda_verb.c
A src/mainboard/clevo/tgl-u/variants/nv40mz/ramstage.c
A src/mainboard/clevo/tgl-u/variants/nv40mz/romstage.c
11 files changed, 700 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/62498/6
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Change subject: soc/intel/cmn/spi: Add ACPI SSDT extension for fast SPI
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/common/block/spi/spi.c:
https://review.coreboot.org/c/coreboot/+/63982/comment/7138cbf2_cf931d62
PS1, Line 117: spi_fill_ssdt
> Right, we mustn't add a device with _HID if there is a discoverable
> PCI device.
OK, agree.
And yes, APL is kind of different here as the policy is to hide this device, which is hard coded and not bound to a config switch or the like. Even checking for the availability is not doable here as at the time of PCI enumeration the SPI controller _is_ visible. It will be hidden later.
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Change subject: payloads: Update GRUB2 stable version from 2.04 to 2.06
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Nico and Kyösti analyzed the issue in #coreboot(a)irc.libera.chat. The bug seems to be in GRUB’s mkimage. mkimage and the linking seem to disagree if the entry point should be at a fixed location. Unfortunately, the code is supposedly hard to read.
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Change subject: soc/intel/skylake: Hook up FSP hyper-threading setting to option API
......................................................................
Patch Set 3: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60542/comment/f459bc80_b56ab15c
PS2, Line 15: obsolete now.
> Done
The code you remove is different. That should be mentioned.
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Change subject: soc/intel/cannonlake: Hook up FSP hyper-threading setting to option API
......................................................................
Patch Set 10: Code-Review+2
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Change subject: soc/intel/skylake: Move FSP_HYPERTHREADING to common Intel Kconfig
......................................................................
Patch Set 8: Code-Review+1
(1 comment)
File src/soc/intel/common/block/cpu/Kconfig:
https://review.coreboot.org/c/coreboot/+/60543/comment/6da708b6_7d56ca17
PS8, Line 140:
Spurious empty line.
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Change subject: util/mb/google: add support for nissa
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Please help to review the CL adding support for Nissa, thanks!
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Change subject: util/mb/google: add support for nissa
......................................................................
util/mb/google: add support for nissa
Add the file template for creating a new variant of Nissa.
BUG=b:229550821
Signed-off-by: Shou-Chieh Hsu <shouchieh(a)google.com>
Change-Id: I04f75ff91f9851b82641f703ba950b04c22e2e72
---
A util/mainboard/google/nissa/template/include/variant/ec.h
A util/mainboard/google/nissa/template/include/variant/gpio.h
A util/mainboard/google/nissa/template/memory/Makefile.inc
A util/mainboard/google/nissa/template/memory/dram_id.generated.txt
A util/mainboard/google/nissa/template/memory/mem_parts_used.txt
A util/mainboard/google/nissa/template/overridetree.cb
6 files changed, 39 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/64045/1
diff --git a/util/mainboard/google/nissa/template/include/variant/ec.h b/util/mainboard/google/nissa/template/include/variant/ec.h
new file mode 100644
index 0000000..7a2a6ff
--- /dev/null
+++ b/util/mainboard/google/nissa/template/include/variant/ec.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __VARIANT_EC_H__
+#define __VARIANT_EC_H__
+
+#include <baseboard/ec.h>
+
+#endif
diff --git a/util/mainboard/google/nissa/template/include/variant/gpio.h b/util/mainboard/google/nissa/template/include/variant/gpio.h
new file mode 100644
index 0000000..c4fe342
--- /dev/null
+++ b/util/mainboard/google/nissa/template/include/variant/gpio.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <baseboard/gpio.h>
+
+#endif
diff --git a/util/mainboard/google/nissa/template/memory/Makefile.inc b/util/mainboard/google/nissa/template/memory/Makefile.inc
new file mode 100644
index 0000000..eace2e4
--- /dev/null
+++ b/util/mainboard/google/nissa/template/memory/Makefile.inc
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate.
+
+SPD_SOURCES = placeholder
diff --git a/util/mainboard/google/nissa/template/memory/dram_id.generated.txt b/util/mainboard/google/nissa/template/memory/dram_id.generated.txt
new file mode 100644
index 0000000..fa24790
--- /dev/null
+++ b/util/mainboard/google/nissa/template/memory/dram_id.generated.txt
@@ -0,0 +1 @@
+DRAM Part Name ID to assign
diff --git a/util/mainboard/google/nissa/template/memory/mem_parts_used.txt b/util/mainboard/google/nissa/template/memory/mem_parts_used.txt
new file mode 100644
index 0000000..9621137
--- /dev/null
+++ b/util/mainboard/google/nissa/template/memory/mem_parts_used.txt
@@ -0,0 +1,11 @@
+# This is a CSV file containing a list of memory parts used by this variant.
+# One part per line with an optional fixed ID in column 2.
+# Only include a fixed ID if it is required for legacy reasons!
+# Generated IDs are dependent on the order of parts in this file,
+# so new parts must always be added at the end of the file!
+#
+# Generate an updated Makefile.inc and dram_id.generated.txt by running the
+# part_id_gen tool from util/spd_tools.
+# See util/spd_tools/README.md for more details and instructions.
+
+# Part Name
diff --git a/util/mainboard/google/nissa/template/overridetree.cb b/util/mainboard/google/nissa/template/overridetree.cb
new file mode 100644
index 0000000..4f2c04a
--- /dev/null
+++ b/util/mainboard/google/nissa/template/overridetree.cb
@@ -0,0 +1,6 @@
+chip soc/intel/alderlake
+
+ device domain 0 on
+ end
+
+end
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Change subject: soc/intel/cmn/spi: Add ACPI SSDT extension for fast SPI
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/common/block/spi/spi.c:
https://review.coreboot.org/c/coreboot/+/63982/comment/25576543_0cb920eb
PS1, Line 117: spi_fill_ssdt
> > What is the issue in reporting the device even if it is visible? From what I have got the PCI driv […]
Right, we mustn't add a device with _HID if there is a discoverable
PCI device.
However, I have no idea how to check something like that. AFAIK, it's
policy to hide these devices on APL, so always adding the SSDT for
APL should be right?
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