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Change subject: soc/intel/cmn/spi: Add ACPI SSDT extension for fast SPI
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/common/block/spi/spi.c:
https://review.coreboot.org/c/coreboot/+/63982/comment/25576543_0cb920eb
PS1, Line 117: spi_fill_ssdt
> > What is the issue in reporting the device even if it is visible? From what I have got the PCI driv […]
Right, we mustn't add a device with _HID if there is a discoverable
PCI device.
However, I have no idea how to check something like that. AFAIK, it's
policy to hide these devices on APL, so always adding the SSDT for
APL should be right?
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Change subject: nb/amd/agesa/family14: Avoid caching fx devices
......................................................................
Patch Set 1:
(1 comment)
File src/northbridge/amd/agesa/family14/northbridge.c:
https://review.coreboot.org/c/coreboot/+/64010/comment/60bb267a_98830eb4
PS1, Line 44: struct device *f1_dev = get_fx_dev(1);
If the devices are declared in the devicetree, you could also use
`__pci_0_18_1` from <static_devices.h>.
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Change subject: nb/amd/agesa/family14: Clean up fx_devs stuff
......................................................................
Patch Set 1: Code-Review+1
(4 comments)
File src/northbridge/amd/agesa/family14/northbridge.c:
https://review.coreboot.org/c/coreboot/+/64009/comment/28d5e83a_e669ef95
PS1, Line 78: if (fx_devs == 0)
Not needed anymore.
https://review.coreboot.org/c/coreboot/+/64009/comment/c0201d31_7bca1f0d
PS1, Line 86: if (fx_devs == 0)
Dito.
https://review.coreboot.org/c/coreboot/+/64009/comment/06597493_0f22ee30
PS1, Line 88: for (i = 0; i < fx_devs; i++) {
Also not needed anymore.
https://review.coreboot.org/c/coreboot/+/64009/comment/50d6b2d9_89468fd1
PS1, Line 460: base = f1_read_config32(reg);
: limit = f1_read_config32(reg + 0x04);
NB. When were these written?
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Change subject: soc/intel/cmn/spi: Add ACPI SSDT extension for fast SPI
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/common/block/spi/spi.c:
https://review.coreboot.org/c/coreboot/+/63982/comment/9cb696eb_b4cc276b
PS1, Line 117: spi_fill_ssdt
> What is the issue in reporting the device even if it is visible? From what I have got the PCI driver in OS will take precedence over ACPI if available.
How would the OS know that this ACPI device == PCI device?
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Change subject: soc/intel/cmn/spi: Add ACPI SSDT extension for fast SPI
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/common/block/spi/spi.c:
https://review.coreboot.org/c/coreboot/+/63982/comment/97da74fd_47185c45
PS1, Line 117: spi_fill_ssdt
> > The `hidden` keyword is a hack for devices that are hidden from coreboot. […]
What is the issue in reporting the device even if it is visible? From what I have got the PCI driver in OS will take precedence over ACPI if available.
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Change subject: soc/intel/xeon_sp/cpx: Allow creating meminfo for empty DIMM slots
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/64036/comment/be720807_6073d741
PS1, Line 9: Introduce the mainboard-defined `mainboard_dimm_slot_exists()` function
Wouldn't a simple Kconfig number do? It's hard to tell without seeing
the mb implementation.
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Change subject: arch/x86/smbios.c: Allow creating entries for empty DIMM slots
......................................................................
Patch Set 1: Code-Review+1
(3 comments)
File src/arch/x86/smbios.c:
https://review.coreboot.org/c/coreboot/+/64035/comment/9f529515_1bc70150
PS1, Line 281: *current
No need for a pointer, AFAICS.
https://review.coreboot.org/c/coreboot/+/64035/comment/6c28f7be_d62a546a
PS1, Line 291: t->form_factor = 0x2; /* Unknown */
Shouldn't this be DIMM?
https://review.coreboot.org/c/coreboot/+/64035/comment/8d478b22_524824e5
PS1, Line 295: t->manufacturer = smbios_add_string(t->eos, "NO DIMM");
: t->serial_number = smbios_add_string(t->eos, "NO DIMM");
: t->asset_tag = smbios_add_string(t->eos, "NO DIMM");
: t->part_number = smbios_add_string(t->eos, "NO DIMM");
Why set these? Isn't that the job of the consuming application, i.e.
interpret `size == 0` as this?
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Change subject: mb/google/brask/variants/moli: disable ASPM on pcie_rp 6
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
Patchset:
PS2:
We also observed the same behavior on prodrive/atlas (ADL-P). When ASPM is enabled on the i225 RP, coreboot seems to hang when configuring LTR.
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Change subject: soc/intel/cmn/spi: Add ACPI SSDT extension for fast SPI
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/common/block/spi/spi.c:
https://review.coreboot.org/c/coreboot/+/63982/comment/02fbdd02_9d0e7ea6
PS1, Line 117: spi_fill_ssdt
> The `hidden` keyword is a hack for devices that are hidden from coreboot.
> So `dev->hidden` is actually reliable, it has to be. But it serves a different
> purpose.
Would it make sense to just do a basic check: only add ACPI code for B:D:F if B:D:0 is not discoverable to the OS (be it hidden or disabled)?
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Change subject: soc/intel/cmn/spi: Add ACPI SSDT extension for fast SPI
......................................................................
Patch Set 2:
(2 comments)
Patchset:
PS1:
> Hmm. […]
For APL sounds good. There wouldn't be anything to do for the new driver beside
writing the SSDT. So it's not needed for all SoCs. I guess GLK, SKL, KBL and CFL
are candidates for the same fix, but should be tested individually.
File src/soc/intel/common/block/spi/spi.c:
https://review.coreboot.org/c/coreboot/+/63982/comment/3d5d5586_e71f417f
PS1, Line 117: spi_fill_ssdt
> In general yes. […]
The `hidden` keyword is a hack for devices that are hidden from coreboot.
So `dev->hidden` is actually reliable, it has to be. But it serves a different
purpose.
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