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Change subject: soc/intel/skylake: Move FSP_HYPERTHREADING to common Intel Kconfig
......................................................................
Patch Set 8: Code-Review+1
(1 comment)
File src/soc/intel/common/block/cpu/Kconfig:
https://review.coreboot.org/c/coreboot/+/60543/comment/6da708b6_7d56ca17
PS8, Line 140:
Spurious empty line.
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Change subject: util/mb/google: add support for nissa
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Please help to review the CL adding support for Nissa, thanks!
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Change subject: util/mb/google: add support for nissa
......................................................................
util/mb/google: add support for nissa
Add the file template for creating a new variant of Nissa.
BUG=b:229550821
Signed-off-by: Shou-Chieh Hsu <shouchieh(a)google.com>
Change-Id: I04f75ff91f9851b82641f703ba950b04c22e2e72
---
A util/mainboard/google/nissa/template/include/variant/ec.h
A util/mainboard/google/nissa/template/include/variant/gpio.h
A util/mainboard/google/nissa/template/memory/Makefile.inc
A util/mainboard/google/nissa/template/memory/dram_id.generated.txt
A util/mainboard/google/nissa/template/memory/mem_parts_used.txt
A util/mainboard/google/nissa/template/overridetree.cb
6 files changed, 39 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/64045/1
diff --git a/util/mainboard/google/nissa/template/include/variant/ec.h b/util/mainboard/google/nissa/template/include/variant/ec.h
new file mode 100644
index 0000000..7a2a6ff
--- /dev/null
+++ b/util/mainboard/google/nissa/template/include/variant/ec.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __VARIANT_EC_H__
+#define __VARIANT_EC_H__
+
+#include <baseboard/ec.h>
+
+#endif
diff --git a/util/mainboard/google/nissa/template/include/variant/gpio.h b/util/mainboard/google/nissa/template/include/variant/gpio.h
new file mode 100644
index 0000000..c4fe342
--- /dev/null
+++ b/util/mainboard/google/nissa/template/include/variant/gpio.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <baseboard/gpio.h>
+
+#endif
diff --git a/util/mainboard/google/nissa/template/memory/Makefile.inc b/util/mainboard/google/nissa/template/memory/Makefile.inc
new file mode 100644
index 0000000..eace2e4
--- /dev/null
+++ b/util/mainboard/google/nissa/template/memory/Makefile.inc
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate.
+
+SPD_SOURCES = placeholder
diff --git a/util/mainboard/google/nissa/template/memory/dram_id.generated.txt b/util/mainboard/google/nissa/template/memory/dram_id.generated.txt
new file mode 100644
index 0000000..fa24790
--- /dev/null
+++ b/util/mainboard/google/nissa/template/memory/dram_id.generated.txt
@@ -0,0 +1 @@
+DRAM Part Name ID to assign
diff --git a/util/mainboard/google/nissa/template/memory/mem_parts_used.txt b/util/mainboard/google/nissa/template/memory/mem_parts_used.txt
new file mode 100644
index 0000000..9621137
--- /dev/null
+++ b/util/mainboard/google/nissa/template/memory/mem_parts_used.txt
@@ -0,0 +1,11 @@
+# This is a CSV file containing a list of memory parts used by this variant.
+# One part per line with an optional fixed ID in column 2.
+# Only include a fixed ID if it is required for legacy reasons!
+# Generated IDs are dependent on the order of parts in this file,
+# so new parts must always be added at the end of the file!
+#
+# Generate an updated Makefile.inc and dram_id.generated.txt by running the
+# part_id_gen tool from util/spd_tools.
+# See util/spd_tools/README.md for more details and instructions.
+
+# Part Name
diff --git a/util/mainboard/google/nissa/template/overridetree.cb b/util/mainboard/google/nissa/template/overridetree.cb
new file mode 100644
index 0000000..4f2c04a
--- /dev/null
+++ b/util/mainboard/google/nissa/template/overridetree.cb
@@ -0,0 +1,6 @@
+chip soc/intel/alderlake
+
+ device domain 0 on
+ end
+
+end
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Change subject: soc/intel/cmn/spi: Add ACPI SSDT extension for fast SPI
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/common/block/spi/spi.c:
https://review.coreboot.org/c/coreboot/+/63982/comment/25576543_0cb920eb
PS1, Line 117: spi_fill_ssdt
> > What is the issue in reporting the device even if it is visible? From what I have got the PCI driv […]
Right, we mustn't add a device with _HID if there is a discoverable
PCI device.
However, I have no idea how to check something like that. AFAIK, it's
policy to hide these devices on APL, so always adding the SSDT for
APL should be right?
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Change subject: nb/amd/agesa/family14: Avoid caching fx devices
......................................................................
Patch Set 1:
(1 comment)
File src/northbridge/amd/agesa/family14/northbridge.c:
https://review.coreboot.org/c/coreboot/+/64010/comment/60bb267a_98830eb4
PS1, Line 44: struct device *f1_dev = get_fx_dev(1);
If the devices are declared in the devicetree, you could also use
`__pci_0_18_1` from <static_devices.h>.
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Change subject: nb/amd/agesa/family14: Clean up fx_devs stuff
......................................................................
Patch Set 1: Code-Review+1
(4 comments)
File src/northbridge/amd/agesa/family14/northbridge.c:
https://review.coreboot.org/c/coreboot/+/64009/comment/28d5e83a_e669ef95
PS1, Line 78: if (fx_devs == 0)
Not needed anymore.
https://review.coreboot.org/c/coreboot/+/64009/comment/c0201d31_7bca1f0d
PS1, Line 86: if (fx_devs == 0)
Dito.
https://review.coreboot.org/c/coreboot/+/64009/comment/06597493_0f22ee30
PS1, Line 88: for (i = 0; i < fx_devs; i++) {
Also not needed anymore.
https://review.coreboot.org/c/coreboot/+/64009/comment/50d6b2d9_89468fd1
PS1, Line 460: base = f1_read_config32(reg);
: limit = f1_read_config32(reg + 0x04);
NB. When were these written?
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Change subject: soc/intel/cmn/spi: Add ACPI SSDT extension for fast SPI
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/common/block/spi/spi.c:
https://review.coreboot.org/c/coreboot/+/63982/comment/9cb696eb_b4cc276b
PS1, Line 117: spi_fill_ssdt
> What is the issue in reporting the device even if it is visible? From what I have got the PCI driver in OS will take precedence over ACPI if available.
How would the OS know that this ACPI device == PCI device?
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Change subject: soc/intel/cmn/spi: Add ACPI SSDT extension for fast SPI
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/common/block/spi/spi.c:
https://review.coreboot.org/c/coreboot/+/63982/comment/97da74fd_47185c45
PS1, Line 117: spi_fill_ssdt
> > The `hidden` keyword is a hack for devices that are hidden from coreboot. […]
What is the issue in reporting the device even if it is visible? From what I have got the PCI driver in OS will take precedence over ACPI if available.
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Change subject: soc/intel/xeon_sp/cpx: Allow creating meminfo for empty DIMM slots
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/64036/comment/be720807_6073d741
PS1, Line 9: Introduce the mainboard-defined `mainboard_dimm_slot_exists()` function
Wouldn't a simple Kconfig number do? It's hard to tell without seeing
the mb implementation.
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Change subject: arch/x86/smbios.c: Allow creating entries for empty DIMM slots
......................................................................
Patch Set 1: Code-Review+1
(3 comments)
File src/arch/x86/smbios.c:
https://review.coreboot.org/c/coreboot/+/64035/comment/9f529515_1bc70150
PS1, Line 281: *current
No need for a pointer, AFAICS.
https://review.coreboot.org/c/coreboot/+/64035/comment/6c28f7be_d62a546a
PS1, Line 291: t->form_factor = 0x2; /* Unknown */
Shouldn't this be DIMM?
https://review.coreboot.org/c/coreboot/+/64035/comment/8d478b22_524824e5
PS1, Line 295: t->manufacturer = smbios_add_string(t->eos, "NO DIMM");
: t->serial_number = smbios_add_string(t->eos, "NO DIMM");
: t->asset_tag = smbios_add_string(t->eos, "NO DIMM");
: t->part_number = smbios_add_string(t->eos, "NO DIMM");
Why set these? Isn't that the job of the consuming application, i.e.
interpret `size == 0` as this?
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