coreboot-gerrit May 2022

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Change in coreboot[master]: arch/x86/acpi: Consolidate POST code handling
by Felix Held (Code Review) 04 May '22

04 May '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63988 ) Change subject: arch/x86/acpi: Consolidate POST code handling ...................................................................... arch/x86/acpi: Consolidate POST code handling Move ASL POST code declarations into a common file to avoid redundancy. Also, provide a dummy implementation when `POST_IO` is not enabled, as the value of `CONFIG_POST_IO_PORT` can't be used. Change-Id: I891bd8754f10f16d618e76e1ab88c26164776a50 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63988 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- A src/arch/x86/acpi/post.asl M src/mainboard/asus/p2b/dsdt.asl M src/mainboard/intel/cedarisland_crb/acpi/platform.asl M src/soc/intel/common/acpi/platform.asl M src/southbridge/intel/common/acpi/platform.asl 5 files changed, 21 insertions(+), 28 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/arch/x86/acpi/post.asl b/src/arch/x86/acpi/post.asl new file mode 100644 index 0000000..dbdc681 --- /dev/null +++ b/src/arch/x86/acpi/post.asl @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#if CONFIG(POST_IO) + +/* POST code support, typically on port 80 */ +OperationRegion (POST, SystemIO, CONFIG_POST_IO_PORT, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +#else + +/* Dummy placeholder to avoid issues */ +Name (DBG0, 0) + +#endif diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl index 25515d2..5d53c1d 100644 --- a/src/mainboard/asus/p2b/dsdt.asl +++ b/src/mainboard/asus/p2b/dsdt.asl @@ -22,13 +22,7 @@ #include <acpi/dsdt_top.asl> /* \_SB scope defining the main processor is generated in SSDT. */ - /* Port 80 POST */ - - OperationRegion (POST, SystemIO, 0x80, 1) - Field (POST, ByteAcc, Lock, Preserve) - { - DBG0, 8 - } + #include <arch/x86/acpi/post.asl> /* * Intel 82371EB (PIIX4E) datasheet, section 7.2.3, page 142 diff --git a/src/mainboard/intel/cedarisland_crb/acpi/platform.asl b/src/mainboard/intel/cedarisland_crb/acpi/platform.asl index 3bebbff..5f7ffbb 100644 --- a/src/mainboard/intel/cedarisland_crb/acpi/platform.asl +++ b/src/mainboard/intel/cedarisland_crb/acpi/platform.asl @@ -9,13 +9,7 @@ APMS, 8 // APM status } -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} +#include <arch/x86/acpi/post.asl> Name(\APC1, Zero) // IIO IOAPIC diff --git a/src/soc/intel/common/acpi/platform.asl b/src/soc/intel/common/acpi/platform.asl index 3bb2f53..c988e0a 100644 --- a/src/soc/intel/common/acpi/platform.asl +++ b/src/soc/intel/common/acpi/platform.asl @@ -7,13 +7,7 @@ External(\_SB.PCI0.EGPM, MethodObj) External(\_SB.PCI0.RGPM, MethodObj) -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, CONFIG_POST_IO_PORT, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} +#include <arch/x86/acpi/post.asl> /* * The _PTS method (Prepare To Sleep) is called before the OS is diff --git a/src/southbridge/intel/common/acpi/platform.asl b/src/southbridge/intel/common/acpi/platform.asl index ec7d680..e044f04 100644 --- a/src/southbridge/intel/common/acpi/platform.asl +++ b/src/southbridge/intel/common/acpi/platform.asl @@ -9,13 +9,7 @@ APMS, 8 // APM status } -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} +#include <arch/x86/acpi/post.asl> #if CONFIG(ACPI_SOC_NVS) /* SMI I/O Trap */ -- To view, visit https://review.coreboot.org/c/coreboot/+/63988 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I891bd8754f10f16d618e76e1ab88c26164776a50 Gerrit-Change-Number: 63988 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/asus/p2b/dsdt.asl: Align POST code ASL stuff
by Felix Held (Code Review) 04 May '22

04 May '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63987 ) Change subject: mb/asus/p2b/dsdt.asl: Align POST code ASL stuff ...................................................................... mb/asus/p2b/dsdt.asl: Align POST code ASL stuff Align POST code ASL elements with existing code in newer southbridges. The main differences are that `NoLock` is changed to `Lock`, and that names have been changed. The lock type change should not be a problem because the field is only used once in the _PTS method. Change-Id: I8aa362007ff98e5b42add6c7908a8f7beac2222b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63987 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- M src/mainboard/asus/p2b/dsdt.asl 1 file changed, 6 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl index 2c88cf6..25515d2 100644 --- a/src/mainboard/asus/p2b/dsdt.asl +++ b/src/mainboard/asus/p2b/dsdt.asl @@ -22,10 +22,12 @@ #include <acpi/dsdt_top.asl> /* \_SB scope defining the main processor is generated in SSDT. */ - OperationRegion(X80, SystemIO, 0x80, 1) - Field(X80, ByteAcc, NoLock, Preserve) + /* Port 80 POST */ + + OperationRegion (POST, SystemIO, 0x80, 1) + Field (POST, ByteAcc, Lock, Preserve) { - P80, 8 + DBG0, 8 } /* @@ -77,7 +79,7 @@ /* Arms SMI for device 12 */ TO12 = 1 /* Put out a POST code */ - P80 = Arg0 | 0xF0 + DBG0 = Arg0 | 0xF0 } Method (\_WAK, 1, NotSerialized) -- To view, visit https://review.coreboot.org/c/coreboot/+/63987 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8aa362007ff98e5b42add6c7908a8f7beac2222b Gerrit-Change-Number: 63987 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: arch/x86/acpi/debug.asl: Drop POST code stuff
by Felix Held (Code Review) 04 May '22

04 May '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63986 ) Change subject: arch/x86/acpi/debug.asl: Drop POST code stuff ...................................................................... arch/x86/acpi/debug.asl: Drop POST code stuff To pave the way for future refactoring commits, drop POST code elements from the debug.asl file. Only msi/ms7721 includes debug.asl and it does not use any of it anyway. Change-Id: Icd73e5c1f700fd7e735bed1668f02da8f9a3adf3 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63986 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/arch/x86/acpi/debug.asl 1 file changed, 0 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/arch/x86/acpi/debug.asl b/src/arch/x86/acpi/debug.asl index cee85e5..fe71b3e 100644 --- a/src/arch/x86/acpi/debug.asl +++ b/src/arch/x86/acpi/debug.asl @@ -1,10 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* -* 0x80: POST_BASE * 0x3F8: DEBCOM_BASE -* X80: POST_REGION -* P80: PORT80 * * CREG: DEBCOM_REGION * CUAR: DEBCOM_UART @@ -17,12 +14,6 @@ * DEBUG_INIT DINI */ -OperationRegion(X80, SystemIO, 0x80, 1) - Field(X80, ByteAcc, NoLock, Preserve) -{ - P80, 8 -} - OperationRegion(CREG, SystemIO, 0x3F8, 8) Field(CREG, ByteAcc, NoLock, Preserve) { -- To view, visit https://review.coreboot.org/c/coreboot/+/63986 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd73e5c1f700fd7e735bed1668f02da8f9a3adf3 Gerrit-Change-Number: 63986 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: Add SBOM (Software Bill of Materials) Generation
by Maximilian Brune (Code Review) 04 May '22

04 May '22

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Change in coreboot[master]: soc/amd/common/block/psp/psp_gen2: move CORE_2_PSP_MSG_38 defines
by Felix Held (Code Review) 04 May '22

04 May '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/64011 ) Change subject: soc/amd/common/block/psp/psp_gen2: move CORE_2_PSP_MSG_38 defines ...................................................................... soc/amd/common/block/psp/psp_gen2: move CORE_2_PSP_MSG_38 defines CORE_2_PSP_MSG_38_OFFSET and CORE_2_PSP_MSG_38_FUSE_SPL are only used in psp_gen2.c, so move them into this file. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I67cc2ff63d1c0322b514521975f3ce0f9b1cf5b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64011 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M src/soc/amd/common/block/psp/psp_def.h M src/soc/amd/common/block/psp/psp_gen2.c 2 files changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Raul Rangel: Looks good to me, approved Fred Reitberger: Looks good to me, but someone else must approve diff --git a/src/soc/amd/common/block/psp/psp_def.h b/src/soc/amd/common/block/psp/psp_def.h index f171efe..4d860ff 100644 --- a/src/soc/amd/common/block/psp/psp_def.h +++ b/src/soc/amd/common/block/psp/psp_def.h @@ -26,9 +26,6 @@ #define MBOX_BIOS_CMD_SMU_FW 0x19 #define MBOX_BIOS_CMD_SMU_FW2 0x1a -#define CORE_2_PSP_MSG_38_OFFSET 0x10998 -#define CORE_2_PSP_MSG_38_FUSE_SPL BIT(12) - /* command/response format, BIOS builds this in memory * mbox_buffer_header: generic header * mbox_buffer: command-specific buffer format diff --git a/src/soc/amd/common/block/psp/psp_gen2.c b/src/soc/amd/common/block/psp/psp_gen2.c index 12f5fec..80650cb 100644 --- a/src/soc/amd/common/block/psp/psp_gen2.c +++ b/src/soc/amd/common/block/psp/psp_gen2.c @@ -13,6 +13,9 @@ #define PSP_MAILBOX_COMMAND_OFFSET 0x10570 /* 4 bytes */ #define PSP_MAILBOX_BUFFER_OFFSET 0x10574 /* 8 bytes */ +#define CORE_2_PSP_MSG_38_OFFSET 0x10998 /* 4 byte */ +#define CORE_2_PSP_MSG_38_FUSE_SPL BIT(12) + union pspv2_mbox_command { u32 val; struct pspv2_mbox_cmd_fields { -- To view, visit https://review.coreboot.org/c/coreboot/+/64011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67cc2ff63d1c0322b514521975f3ce0f9b1cf5b1 Gerrit-Change-Number: 64011 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/siemens/mc_ehl2: Disable PCI clock outputs on XIO bridge
by Mario Scheithauer (Code Review) 04 May '22

04 May '22

Attention is currently required from: Werner Zeh. Hello build bot (Jenkins), Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63931 to look at the new patch set (#4). Change subject: mb/siemens/mc_ehl2: Disable PCI clock outputs on XIO bridge ...................................................................... mb/siemens/mc_ehl2: Disable PCI clock outputs on XIO bridge On this mainboard there are legacy PCI devices connected behind a PCI-2-PCI bridge. Not all ports are in use. This patch disables the unused PCI clock outputs on the XIO2001 PCI Express to PCI Bridge. Change-Id: Iedbf0abfa554e0a6ad5b1d1741f4e9934103d171 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/63931/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/63931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iedbf0abfa554e0a6ad5b1d1741f4e9934103d171 Gerrit-Change-Number: 63931 Gerrit-PatchSet: 4 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/siemens/mc_ehl2: Disable PCI clock outputs on XIO bridge
by Mario Scheithauer (Code Review) 04 May '22

04 May '22

Attention is currently required from: Werner Zeh. Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63931 ) Change subject: mb/siemens/mc_ehl2: Disable PCI clock outputs on XIO bridge ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63931/comment/7d5270c7_6e215a1b PS2, Line 9: On this mainboard there are legacy PCI device, which are connected to > There is just one bridge on this board. I have reworded the statement. -- To view, visit https://review.coreboot.org/c/coreboot/+/63931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iedbf0abfa554e0a6ad5b1d1741f4e9934103d171 Gerrit-Change-Number: 63931 Gerrit-PatchSet: 3 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Wed, 04 May 2022 12:59:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/siemens/mc_ehl2: Disable PCI clock outputs on XIO bridge
by Mario Scheithauer (Code Review) 04 May '22

04 May '22

Attention is currently required from: Mario Scheithauer. Hello build bot (Jenkins), Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63931 to look at the new patch set (#3). Change subject: mb/siemens/mc_ehl2: Disable PCI clock outputs on XIO bridge ...................................................................... mb/siemens/mc_ehl2: Disable PCI clock outputs on XIO bridge On this mainboard there are legacy PCI devices connected behind a PCI-2-PCI bridge. Not all ports are in use. This patch disables the unused PCI clock outputs on the XIO2001 PCI Express to PCI Bridges. Change-Id: Iedbf0abfa554e0a6ad5b1d1741f4e9934103d171 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/63931/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/63931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iedbf0abfa554e0a6ad5b1d1741f4e9934103d171 Gerrit-Change-Number: 63931 Gerrit-PatchSet: 3 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/ehl: Provide function to change PHY-to-MAC IRQ polarity
by Mario Scheithauer (Code Review) 04 May '22

04 May '22

Attention is currently required from: Paul Menzel, Werner Zeh. Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63888 ) Change subject: soc/intel/ehl: Provide function to change PHY-to-MAC IRQ polarity ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/elkhartlake/Kconfig: https://review.coreboot.org/c/coreboot/+/63888/comment/b8001368_28b0b3d0 PS2, Line 246: config EHL_TSN_PHY2MAC_IRQ_ACTIVE_HIGH > I will have a look at this... Switched to devicetree option. -- To view, visit https://review.coreboot.org/c/coreboot/+/63888 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia314014c7cacbeb72629c773c8c0bb5f002a3f54 Gerrit-Change-Number: 63888 Gerrit-PatchSet: 5 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Wed, 04 May 2022 12:47:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/phy/m88e1512: Add new driver for Marvell PHY 88E1512
by Mario Scheithauer (Code Review) 04 May '22

04 May '22

Attention is currently required from: Nico Huber, Paul Menzel, Werner Zeh. Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64024 ) Change subject: drivers/phy/m88e1512: Add new driver for Marvell PHY 88E1512 ...................................................................... Patch Set 3: (2 comments) File src/drivers/phy/m88e1512/chip.h: https://review.coreboot.org/c/coreboot/+/64024/comment/af48e495_69ef9813 PS3, Line 4: unsigned char device_index; > What does this describe? Something functional? is it related to […] Yes, this is not necessary. I have removed it. File src/soc/intel/elkhartlake/tsn_gbe.c: https://review.coreboot.org/c/coreboot/+/64024/comment/d6962594_504df6c2 PS1, Line 124: .ops_pci = &pci_dev_ops_pci, > That EHL is a(/the?) corresponding SoC is only visible to people […] To the background...I need to modify the status LEDs of the Marvell PHY and for this I wanted to use the functions 'tsn_mdio_read' and 'tsn_mdio_write' from EHL SoC tsn_gbe.c. Since the access is SoC specific, it's better to put that part there too then, right? -- To view, visit https://review.coreboot.org/c/coreboot/+/64024 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabe1aef2217dfaee4b5a4bd83782ab588d4be642 Gerrit-Change-Number: 64024 Gerrit-PatchSet: 3 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Wed, 04 May 2022 12:45:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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coreboot-gerrit May 2022