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Hello build bot (Jenkins), Werner Zeh,
I'd like you to reexamine a change. Please visit
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Change subject: mb/siemens/mc_ehl2: Disable PCI clock outputs on XIO bridge
......................................................................
mb/siemens/mc_ehl2: Disable PCI clock outputs on XIO bridge
On this mainboard there are legacy PCI devices connected behind a
PCI-2-PCI bridge. Not all ports are in use. This patch disables the
unused PCI clock outputs on the XIO2001 PCI Express to PCI Bridge.
Change-Id: Iedbf0abfa554e0a6ad5b1d1741f4e9934103d171
Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
---
M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c
1 file changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/63931/4
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Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63931 )
Change subject: mb/siemens/mc_ehl2: Disable PCI clock outputs on XIO bridge
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63931/comment/7d5270c7_6e215a1b
PS2, Line 9: On this mainboard there are legacy PCI device, which are connected to
> There is just one bridge on this board.
I have reworded the statement.
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Hello build bot (Jenkins), Werner Zeh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63931
to look at the new patch set (#3).
Change subject: mb/siemens/mc_ehl2: Disable PCI clock outputs on XIO bridge
......................................................................
mb/siemens/mc_ehl2: Disable PCI clock outputs on XIO bridge
On this mainboard there are legacy PCI devices connected behind a
PCI-2-PCI bridge. Not all ports are in use. This patch disables the
unused PCI clock outputs on the XIO2001 PCI Express to PCI Bridges.
Change-Id: Iedbf0abfa554e0a6ad5b1d1741f4e9934103d171
Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
---
M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c
1 file changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/63931/3
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Change subject: soc/intel/ehl: Provide function to change PHY-to-MAC IRQ polarity
......................................................................
Patch Set 5:
(1 comment)
File src/soc/intel/elkhartlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/63888/comment/b8001368_28b0b3d0
PS2, Line 246: config EHL_TSN_PHY2MAC_IRQ_ACTIVE_HIGH
> I will have a look at this...
Switched to devicetree option.
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Change subject: drivers/phy/m88e1512: Add new driver for Marvell PHY 88E1512
......................................................................
Patch Set 3:
(2 comments)
File src/drivers/phy/m88e1512/chip.h:
https://review.coreboot.org/c/coreboot/+/64024/comment/af48e495_69ef9813
PS3, Line 4: unsigned char device_index;
> What does this describe? Something functional? is it related to […]
Yes, this is not necessary. I have removed it.
File src/soc/intel/elkhartlake/tsn_gbe.c:
https://review.coreboot.org/c/coreboot/+/64024/comment/d6962594_504df6c2
PS1, Line 124: .ops_pci = &pci_dev_ops_pci,
> That EHL is a(/the?) corresponding SoC is only visible to people […]
To the background...I need to modify the status LEDs of the Marvell PHY and for this I wanted to use the functions 'tsn_mdio_read' and 'tsn_mdio_write' from EHL SoC tsn_gbe.c. Since the access is SoC specific, it's better to put that part there too then, right?
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Hello build bot (Jenkins), Werner Zeh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63888
to look at the new patch set (#5).
Change subject: soc/intel/ehl: Provide function to change PHY-to-MAC IRQ polarity
......................................................................
soc/intel/ehl: Provide function to change PHY-to-MAC IRQ polarity
EHL MAC side expects a rising edge signal for an IRQ. Based on the
mainboard wiring it could be necessary to change the interrupt polarity.
This patch provides the functionality to invert a falling edge signal
that comes from an external PHY.
Change-Id: Ia314014c7cacbeb72629c773c8c0bb5f002a3f54
Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
---
M src/soc/intel/elkhartlake/chip.h
M src/soc/intel/elkhartlake/include/soc/tsn_gbe.h
M src/soc/intel/elkhartlake/tsn_gbe.c
3 files changed, 121 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/63888/5
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Hello build bot (Jenkins), Werner Zeh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63889
to look at the new patch set (#5).
Change subject: mb/siemens/mc_ehl2: Invert PHY IRQ from falling edge to rising edge
......................................................................
mb/siemens/mc_ehl2: Invert PHY IRQ from falling edge to rising edge
There are three external Marvel PHY 88E1512 on this mainboard. The PHY
IRQ comes with a falling edge but the EHL MAC side needs a rising edge
signal. For that reason, we need an inversion of the IRQ polarity.
Change-Id: Id3caf582b4434b046779f5733e6ad9b57528ce35
Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
---
M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/63889/5
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/64024
to look at the new patch set (#4).
Change subject: drivers/phy/m88e1512: Add new driver for Marvell PHY 88E1512
......................................................................
drivers/phy/m88e1512: Add new driver for Marvell PHY 88E1512
This driver enables the usage of an external Marvell PHY 88E1512 which
should be connected to a SOC internal MAC controller. In a first step it
is only the framework of the driver. Functionality will follow with a
second patch.
Link to the Marvell PHY 88E1512 datasheet:
https://www.marvell.com/content/dam/marvell/en/public-collateral/transceive…
Change-Id: Iabe1aef2217dfaee4b5a4bd83782ab588d4be642
Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
---
A src/drivers/phy/m88e1512/Kconfig
A src/drivers/phy/m88e1512/Makefile.inc
A src/drivers/phy/m88e1512/m88e1512.c
3 files changed, 31 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/64024/4
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Change subject: Add SBOM (Software Bill of Materials) Generation
......................................................................
Set Ready For Review
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