Attention is currently required from: Werner Zeh.
Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63931 )
Change subject: mb/siemens/mc_ehl2: Disable PCI clock outputs on XIO bridge
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Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63931/comment/7d5270c7_6e215a1b
PS2, Line 9: On this mainboard there are legacy PCI device, which are connected to
There is just one bridge on this board.
I have reworded the statement.
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