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Change subject: nb/amd/agesa/family14: Clean up fx_devs stuff
......................................................................
Patch Set 1: Code-Review+1
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/59807
to look at the new patch set (#22).
Change subject: nb/amd/agesa/family14: Enable PARALLEL_MP
......................................................................
nb/amd/agesa/family14: Enable PARALLEL_MP
Disable LEGACY_SMP_INIT and enable PARALLEL_MP.
TEST=Boot Debian 11 on PC Engines apu1
Boot time reduced by ~3ms on average.
Inspired by CB:59693
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
Change-Id: I39a0779bdf115eebe31290591152b920acde773e
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
---
M src/cpu/amd/agesa/family14/model_14_init.c
M src/northbridge/amd/agesa/family14/Kconfig
M src/northbridge/amd/agesa/family14/northbridge.c
3 files changed, 20 insertions(+), 35 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/59807/22
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Michał Kopeć has uploaded a new patch set (#21) to the change originally created by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/52781 )
Change subject: cpu/amd/agesa/family14/model_14_init.c: create correct MTRR solution
......................................................................
cpu/amd/agesa/family14/model_14_init.c: create correct MTRR solution
Create the correct MTRR solution based on the physical address space
provided by RESOURCE_ALLOCATOR_V4. Previously CPU initialization did not
account for lost C6 DRAM storage MTRR during postcar frame creation.
The BSP on 2GB has been stripped from UC MTRR covering C6 DRAM and
overlapping with usable DRAM WB MTRR. However this UC MTRR remained on
APs which caused inconsistent MTRRs warning in Linux. Use generic MTRR
function to create correct MTRR solution that propagates to APs. This
also fixes the inconsistent MTRRs warning.
TEST=boot Debian with Linux 4.14 on apu1 2GB
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Change-Id: If706f8851ed0b1d45729e81175d82abb1d9193be
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
---
M src/cpu/amd/agesa/family14/model_14_init.c
1 file changed, 16 insertions(+), 40 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/52781/21
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Michał Kopeć has uploaded a new patch set (#17) to the change originally created by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/52780 )
Change subject: northbridge/amd/agesa/family14: enable RESOURCE_ALLOCATOR_V4
......................................................................
northbridge/amd/agesa/family14: enable RESOURCE_ALLOCATOR_V4
TEST=boot Debian with Linux 4.14 on apu1 2GB
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Change-Id: Ia01c5e238d53f719bb0d15e106517b99432a0c31
---
M src/northbridge/amd/agesa/family14/Kconfig
1 file changed, 0 insertions(+), 1 deletion(-)
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Michał Kopeć has uploaded a new patch set (#16) to the change originally created by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/52935 )
Change subject: nb/amd/agesa/family14/northbridge.c: Report missing resources
......................................................................
nb/amd/agesa/family14/northbridge.c: Report missing resources
Not all resources were being reported, add them:
0xa0000 - 0xbffff: legacy VGA
0xc0000 - 0xfffff: option ROMs and SeaBIOS (if used)
CC6 DRAM
TEST=boot Debian with Linux 4.14 on apu1 2GB
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Change-Id: I0b1b5f585ff6e0c7aecad250a75600e0c76331e1
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
---
M src/northbridge/amd/agesa/family14/northbridge.c
1 file changed, 50 insertions(+), 46 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/52935/16
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Michał Kopeć has uploaded a new patch set (#13) to the change originally created by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/53954 )
Change subject: nb/amd/agesa/family14: Use generic allocation functions for PCI domain
......................................................................
nb/amd/agesa/family14: Use generic allocation functions for PCI domain
Move the DRAM reporting to read_resoures function before the resources
are being set. Use generic PCI domain resource allocation functions
to read and set domain resources.
TEST=boot Debian with Linux 4.14 on apu1 2GB
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Change-Id: Ie322c7eee443646a5690920c1e06851ee5fdfac3
---
M src/northbridge/amd/agesa/family14/northbridge.c
1 file changed, 5 insertions(+), 52 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/53954/13
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Michał Kopeć has uploaded a new patch set (#13) to the change originally created by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/52934 )
Change subject: nb/amd/agesa/family14: Use generic allocation functions for northbridge
......................................................................
nb/amd/agesa/family14: Use generic allocation functions for northbridge
Remove obsolete resource assigning functions. IO and MMIO address
registers are currently set by amd_initcpuio to cover whole PCI hole
under 4G to MMIO and IO 0x0000-0xFFFF is configured to be routed to
southbridge already. Use generic PCI and resource allocation functions
wherever possible to set northbridge resources.
TEST=boot Debian with Linux 4.14 on apu1 2GB
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Change-Id: I74a0ed1fcbbc9e066c42c4d51d30ab1d7138134a
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
---
M src/northbridge/amd/agesa/family14/northbridge.c
1 file changed, 7 insertions(+), 236 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/52934/13
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Hello Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/64042
to look at the new patch set (#2).
Change subject: mb/google/brask/variants/moli: disable ASPM on pcie_rp 6
......................................................................
mb/google/brask/variants/moli: disable ASPM on pcie_rp 6
Currently coreboot will hang on ASPM on pcie_rp 6,
so disable ASPM to let it go into kernel.
BUG=b:231400217
TEST=emerge-brask coreboot.
Signed-off-by: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com>
Change-Id: I79a80d97d168f40e58774e5652967d659daa323c
---
M src/mainboard/google/brya/variants/moli/overridetree.cb
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/64042/2
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Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60547 )
Change subject: soc/intel/alderlake: Hook up FSP hyper-threading setting to option API
......................................................................
Patch Set 13:
(1 comment)
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/60547/comment/77df18bd_9c3dffaa
PS6, Line 162: /* Enable Hyper Threading */
> Please update.
I just deleted it, since it is obsolete anyway.
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Hello build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, Michael Niewöhner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/60547
to look at the new patch set (#14).
Change subject: soc/intel/alderlake: Hook up FSP hyper-threading setting to option API
......................................................................
soc/intel/alderlake: Hook up FSP hyper-threading setting to option API
Select `HAVE_HYPERTHREADING` and hook up the hyper-threading setting
from the FSP to the option API so that related mainboards don't have to
do that. Unless otherwise configured (e.g. the CMOS setting or overriden
by the mainboard code), the value from the Kconfig setting
`FSP_HYPERTHREADING` is used.
Change-Id: I520a936b4c3a8997ba2c6bea0126b3bbcc5d68ce
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/romstage/fsp_params.c
2 files changed, 3 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/60547/14
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