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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64042 )
Change subject: mb/google/brask/variants/moli: disable ASPM on pcie_rp 6
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
Patchset:
PS2:
We also observed the same behavior on prodrive/atlas (ADL-P). When ASPM is enabled on the i225 RP, coreboot seems to hang when configuring LTR.
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Change subject: soc/intel/cmn/spi: Add ACPI SSDT extension for fast SPI
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/common/block/spi/spi.c:
https://review.coreboot.org/c/coreboot/+/63982/comment/02fbdd02_9d0e7ea6
PS1, Line 117: spi_fill_ssdt
> The `hidden` keyword is a hack for devices that are hidden from coreboot.
> So `dev->hidden` is actually reliable, it has to be. But it serves a different
> purpose.
Would it make sense to just do a basic check: only add ACPI code for B:D:F if B:D:0 is not discoverable to the OS (be it hidden or disabled)?
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Change subject: soc/intel/cmn/spi: Add ACPI SSDT extension for fast SPI
......................................................................
Patch Set 2:
(2 comments)
Patchset:
PS1:
> Hmm. […]
For APL sounds good. There wouldn't be anything to do for the new driver beside
writing the SSDT. So it's not needed for all SoCs. I guess GLK, SKL, KBL and CFL
are candidates for the same fix, but should be tested individually.
File src/soc/intel/common/block/spi/spi.c:
https://review.coreboot.org/c/coreboot/+/63982/comment/3d5d5586_e71f417f
PS1, Line 117: spi_fill_ssdt
> In general yes. […]
The `hidden` keyword is a hack for devices that are hidden from coreboot.
So `dev->hidden` is actually reliable, it has to be. But it serves a different
purpose.
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/59807
to look at the new patch set (#22).
Change subject: nb/amd/agesa/family14: Enable PARALLEL_MP
......................................................................
nb/amd/agesa/family14: Enable PARALLEL_MP
Disable LEGACY_SMP_INIT and enable PARALLEL_MP.
TEST=Boot Debian 11 on PC Engines apu1
Boot time reduced by ~3ms on average.
Inspired by CB:59693
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
Change-Id: I39a0779bdf115eebe31290591152b920acde773e
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
---
M src/cpu/amd/agesa/family14/model_14_init.c
M src/northbridge/amd/agesa/family14/Kconfig
M src/northbridge/amd/agesa/family14/northbridge.c
3 files changed, 20 insertions(+), 35 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/59807/22
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Attention is currently required from: Michał Żygowski, Michał Kopeć.
Michał Kopeć has uploaded a new patch set (#21) to the change originally created by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/52781 )
Change subject: cpu/amd/agesa/family14/model_14_init.c: create correct MTRR solution
......................................................................
cpu/amd/agesa/family14/model_14_init.c: create correct MTRR solution
Create the correct MTRR solution based on the physical address space
provided by RESOURCE_ALLOCATOR_V4. Previously CPU initialization did not
account for lost C6 DRAM storage MTRR during postcar frame creation.
The BSP on 2GB has been stripped from UC MTRR covering C6 DRAM and
overlapping with usable DRAM WB MTRR. However this UC MTRR remained on
APs which caused inconsistent MTRRs warning in Linux. Use generic MTRR
function to create correct MTRR solution that propagates to APs. This
also fixes the inconsistent MTRRs warning.
TEST=boot Debian with Linux 4.14 on apu1 2GB
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Change-Id: If706f8851ed0b1d45729e81175d82abb1d9193be
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
---
M src/cpu/amd/agesa/family14/model_14_init.c
1 file changed, 16 insertions(+), 40 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/52781/21
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Michał Kopeć has uploaded a new patch set (#13) to the change originally created by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/53954 )
Change subject: nb/amd/agesa/family14: Use generic allocation functions for PCI domain
......................................................................
nb/amd/agesa/family14: Use generic allocation functions for PCI domain
Move the DRAM reporting to read_resoures function before the resources
are being set. Use generic PCI domain resource allocation functions
to read and set domain resources.
TEST=boot Debian with Linux 4.14 on apu1 2GB
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Change-Id: Ie322c7eee443646a5690920c1e06851ee5fdfac3
---
M src/northbridge/amd/agesa/family14/northbridge.c
1 file changed, 5 insertions(+), 52 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/53954/13
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Michał Kopeć has uploaded a new patch set (#13) to the change originally created by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/52934 )
Change subject: nb/amd/agesa/family14: Use generic allocation functions for northbridge
......................................................................
nb/amd/agesa/family14: Use generic allocation functions for northbridge
Remove obsolete resource assigning functions. IO and MMIO address
registers are currently set by amd_initcpuio to cover whole PCI hole
under 4G to MMIO and IO 0x0000-0xFFFF is configured to be routed to
southbridge already. Use generic PCI and resource allocation functions
wherever possible to set northbridge resources.
TEST=boot Debian with Linux 4.14 on apu1 2GB
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Change-Id: I74a0ed1fcbbc9e066c42c4d51d30ab1d7138134a
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
---
M src/northbridge/amd/agesa/family14/northbridge.c
1 file changed, 7 insertions(+), 236 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/52934/13
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