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Change subject: mb/google/brya/var/craask: Disable LTE-related GPIOs based on fw_config
......................................................................
Patch Set 8:
(1 comment)
File src/mainboard/google/brya/variants/craask/fw_config.c:
https://review.coreboot.org/c/coreboot/+/63893/comment/2f7ddb3a_14fd783d
PS7, Line 23: if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) {
: printk(BIOS_DEBUG, "Disable LTE-related GPIO pins.\n");
: gpio_configure_pads(lte_disable_pads, ARRAY_SIZE(lte_disable_pads));
: }
:
> > This approach leavess a gpio interrupt line (GPP_H19) floating for a short time. […]
Hi Reka,
I see, thank you point out the root cause of floating, learn from you.
And also thanks for point out problem of the method I handle fw_config, I will be careful next time.
Would you mind CC me in the CL of fixing nivviks? In that case I will be informed and would update this method in craask.
Thanks!
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Change subject: lib/spd: Demote log about using default DDR4 params to NOTICE
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS1:
> Sorry, I feel like this is my fault. […]
The stress test just check there no error in FW log. There is interest parts, there is always delay or late release SPD information to the public. Unless someone in the JEDEC can maintain this. Otherwise, we always behind the new memory type release. And this is just trivial information to the user, the real information should still based on SMBios type 17. Thus, I still think this is unimportant log.
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Change subject: mb/google/dedede/var/beadrix: Add a Proximity Sensor SX9324 for SAR
......................................................................
Patch Set 9: Code-Review+1
(2 comments)
Patchset:
PS9:
Hi Simon,
Thank you for your advice.
I correct I2C1 and I2C3 refer to https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/thi…
Best Regards,
Teddy
File src/mainboard/google/dedede/variants/beadrix/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/63652/comment/bb3bf51f_2b77989e
PS8, Line 17: Digitizer
> Please correct I2C1/I2C3 either.
Hi Simon,
Thank you for your advice.
I correct I2C1 and I2C3 refer to https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/thi…
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Change subject: soc/intel/cmn/spi: Add ACPI SSDT extension for fast SPI
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
@werner: what you think about porting UART changes into SPI with proper PNP ID based on the PCI device type.
https://github.com/coreboot/coreboot/blob/b470361e025a59cbdd4bca1631ce6082f…
I guess your problem statement is valid for any PCI device that gets hidden by FSP UPD policy during boot hence, OS is unable to discover the device unless exposed using ASL.
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Change subject: lib/spd: Demote log about using default DDR4 params to NOTICE
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS1:
> Done
Sorry, I feel like this is my fault. There's a bug assigned to me to check whether the DDR4 values are still correct for LPDDR5 (http://b/223341399). I just haven't gotten around to it and I've been out for the last two weeks so I didn't see this thread.
I see that CB:63680 already added a case for LPDDR5, treating it the same as DDR4, but I still want to go through and double check this is correct. I'll get on to it soon.
As for this CL, I completely agree with Julius that it's good to have a test to alert us that the memory type is unsupported and force us to go through and check that the values are still correct for the new memory type. I don't have a strong opinion on exactly what the log level should be, e.g. I see your point that people should still be paying attention to warnings. But I think we should make sure it's still caught by the test. I'm not familiar with what this test does. Does it just check there are no ERROR messages in the coreboot log?
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Change subject: mb/google/volteer: Fix wrong typec_port for voxel
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS1:
> Ooh, that's a good catch, would you mind filing a different bug for this Derek? Nick, this will need […]
I have filed a s different bug for this and update the bug number in the commit message.
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Hello build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/64022
to look at the new patch set (#2).
Change subject: mb/google/volteer: Fix wrong typec_port for voxel
......................................................................
mb/google/volteer: Fix wrong typec_port for voxel
This change fixes wrong type-C port number for voxel. Voxel
uses tcss_usb3_port1 not tcss_usb3_port3.
BUG=b:231344977
TEST=Check the transactions are happening on correct port. Also checked
retimer firmware update on both the ports.
Signed-off-by: Derek Huang <derek.huang(a)intel.corp-partner.google.com>
Change-Id: Iba7b3b15296bed99d3626a6d53dfd59e8d20fe5f
---
M src/mainboard/google/volteer/variants/voxel/overridetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/64022/2
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