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Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60542 )
Change subject: soc/intel/skylake: Hook up FSP hyper-threading setting to option API
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60542/comment/f9f54dc4_de9d0443
PS2, Line 15: obsolete now.
> I think I mentioned that with the following: […]
Done
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Terry Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64043 )
Change subject: mb/google/brya/var/crota: setting for codec reset pin in overridetree
......................................................................
mb/google/brya/var/crota: setting for codec reset pin in overridetree
Crota360 is using a Cirrus CS42L42 for its audio codec; it
requires the reset pin to be deasserted in ramstage for proper
power sequencing.
BUG=b:230074351
BRANCH=none
TEST=build coreboot without error
Signed-off-by: Terry Chen <terry_chen(a)wistron.corp-partner.google.com>
Change-Id: Ica3467fbc8639526bee071d56af854de5e07091e
---
M src/mainboard/google/brya/variants/crota/overridetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/64043/1
diff --git a/src/mainboard/google/brya/variants/crota/overridetree.cb b/src/mainboard/google/brya/variants/crota/overridetree.cb
index 20820ac..d96e0f1 100644
--- a/src/mainboard/google/brya/variants/crota/overridetree.cb
+++ b/src/mainboard/google/brya/variants/crota/overridetree.cb
@@ -131,7 +131,7 @@
device ref i2c0 on
chip drivers/i2c/cs42l42
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A23_IRQ)"
- register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B13)"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B15)"
register "ts_inv" = "true"
register "ts_dbnc_rise" = "RISE_DEB_1000_MS"
register "ts_dbnc_fall" = "FALL_DEB_0_MS"
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Gerrit-Owner: Terry Chen <terry_chen(a)wistron.corp-partner.google.com>
Gerrit-MessageType: newchange
Raihow Shi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64042 )
Change subject: mb/google/brask/variants/moli: disable ASPM on pcie_rp 6
......................................................................
mb/google/brask/variants/moli: disable ASPM on pcie_rp 6
Currently coreboot will hang on ASPM on pcie_rp 6,
so disable ASPM to let it go into kernel.
Signed-off-by: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com>
Change-Id: I79a80d97d168f40e58774e5652967d659daa323c
---
M src/mainboard/google/brya/variants/moli/overridetree.cb
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/64042/1
diff --git a/src/mainboard/google/brya/variants/moli/overridetree.cb b/src/mainboard/google/brya/variants/moli/overridetree.cb
index 2048b61..0783999 100644
--- a/src/mainboard/google/brya/variants/moli/overridetree.cb
+++ b/src/mainboard/google/brya/variants/moli/overridetree.cb
@@ -76,6 +76,7 @@
.clk_src = 5,
.clk_req = 5,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
+ .pcie_rp_aspm = ASPM_DISABLE,
}"
device pci 00.0 on end
end # IntelI225V Ethernet NIC
--
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Change subject: soc/intel/skylake: Move FSP_HYPERTHREADING to common Intel Kconfig
......................................................................
Patch Set 8:
(1 comment)
File src/soc/intel/xeon_sp/Kconfig:
https://review.coreboot.org/c/coreboot/+/60543/comment/715ac731_5e96217e
PS6, Line 38: HAVE_HYPERTHREADING
> Makes sense, yes.
Done
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Hello build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, Michael Niewöhner,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#13).
Change subject: soc/intel/alderlake: Hook up FSP hyper-threading setting to option API
......................................................................
soc/intel/alderlake: Hook up FSP hyper-threading setting to option API
Select `HAVE_HYPERTHREADING` and hook up the hyper-threading setting
from the FSP to the option API so that related mainboards don't have to
do that. Unless otherwise configured (e.g. the CMOS setting or overriden
by the mainboard code), the value from the Kconfig setting
`FSP_HYPERTHREADING` is used.
Change-Id: I520a936b4c3a8997ba2c6bea0126b3bbcc5d68ce
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/romstage/fsp_params.c
2 files changed, 3 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/60547/13
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Hello build bot (Jenkins), Sean Rhodes, Tim Wawrzynczak, Michael Niewöhner,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#12).
Change subject: soc/intel/tigerlake: Hook up FSP hyper-threading setting to option API
......................................................................
soc/intel/tigerlake: Hook up FSP hyper-threading setting to option API
Select `HAVE_HYPERTHREADING` and hook up the hyper-threading setting
from the FSP to the option API so that related mainboards don't have to
do that. Unless otherwise configured (e.g. the CMOS setting or overriden
by the mainboard code), the value from the Kconfig setting
`FSP_HYPERTHREADING` is used.
Also, remove related code from the mainboard starlabs/laptop/tgl, since
it is obsolete now.
Change-Id: I49bbd4a776b4e6c55cb373bbf88a3ca076342e3e
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M src/mainboard/starlabs/labtop/variants/tgl/romstage.c
M src/soc/intel/tigerlake/Kconfig
M src/soc/intel/tigerlake/romstage/fsp_params.c
3 files changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/60545/12
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Hello build bot (Jenkins), Sean Rhodes, Nico Huber, Michael Niewöhner,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#10).
Change subject: soc/intel/cannonlake: Hook up FSP hyper-threading setting to option API
......................................................................
soc/intel/cannonlake: Hook up FSP hyper-threading setting to option API
Select `HAVE_HYPERTHREADING` and hook up the hyper-threading setting
from the FSP to the option API so that related mainboards don't have to
do that. Unless otherwise configured (e.g. the CMOS setting or overriden
by the mainboard code), the value from the Kconfig setting
`FSP_HYPERTHREADING` is used.
Also, remove related code from the following mainboards, since it is
obsolete now.
* siemens/chili
* starlabs/laptop/cml
Change-Id: I173b87da5ce76549672c50ba30204cd77be8b82f
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M src/mainboard/siemens/chili/romstage.c
M src/mainboard/starlabs/labtop/variants/cml/romstage.c
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/cannonlake/romstage/fsp_params.c
4 files changed, 4 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/60544/10
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Hello build bot (Jenkins), Anjaneya "Reddy" Chagam, Nico Huber, Jonathan Zhang, Johnny Lin, Christian Walter, Tim Wawrzynczak, Arthur Heymans, Michael Niewöhner, Tim Chu,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#8).
Change subject: soc/intel/skylake: Move FSP_HYPERTHREADING to common Intel Kconfig
......................................................................
soc/intel/skylake: Move FSP_HYPERTHREADING to common Intel Kconfig
Move the Kconfig option `FSP_HYPERTHREADING` to common Intel Kconfig so
that it can be reused by other SoCs. Since not all SoCs support
hyperthreading, make it conditional on `HAVE_HYPERTHREADING`. SoCs
supporting hyperthreading need to select it so that `FSP_HYPERTHREADING`
is available.
Change-Id: I892d48b488cbf828057f0e9be9edc4352c58bbe7
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M src/soc/intel/common/block/cpu/Kconfig
M src/soc/intel/skylake/Kconfig
2 files changed, 10 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/60543/8
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Change subject: soc/intel/skylake: Move FSP_HYPERTHREADING to common Intel Kconfig
......................................................................
Patch Set 7:
(2 comments)
File src/soc/intel/common/block/cpu/Kconfig:
https://review.coreboot.org/c/coreboot/+/60543/comment/46393516_1ba7b9d6
PS6, Line 144: if HAVE_HYPERTHREADING
> use "depends on".
Done
File src/soc/intel/xeon_sp/Kconfig:
https://review.coreboot.org/c/coreboot/+/60543/comment/6c823235_43c4e210
PS6, Line 38: HAVE_HYPERTHREADING
> Can you select this in patches that hook it up? It looks like only skylake consumes CONFIG_FSP_HYPER […]
Makes sense, yes.
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I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/60543
to look at the new patch set (#7).
Change subject: soc/intel/skylake: Move FSP_HYPERTHREADING to common Intel Kconfig
......................................................................
soc/intel/skylake: Move FSP_HYPERTHREADING to common Intel Kconfig
Move the Kconfig option `FSP_HYPERTHREADING` to common Intel Kconfig so
that it can be reused by other SoCs. Since not all SoCs support
hyperthreading, make it conditional on `HAVE_HYPERTHREADING`. SoCs
supporting hyperthreading need to select it so that `FSP_HYPERTHREADING`
is available.
Also, select `HAVE_HYPERTHREADING` on the following Intel platforms:
* Alderlake
* Cannon Lake
* Ice Lake
* Skylake
* Tiger Lake
* Xeon SP
Change-Id: I892d48b488cbf828057f0e9be9edc4352c58bbe7
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/common/block/cpu/Kconfig
M src/soc/intel/icelake/Kconfig
M src/soc/intel/skylake/Kconfig
M src/soc/intel/tigerlake/Kconfig
M src/soc/intel/xeon_sp/Kconfig
7 files changed, 15 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/60543/7
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