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Change subject: mb/google/brya/var/crota: setting for codec reset pin in overridetree
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/64043/comment/30791ff6_4a678d78
PS1, Line 7: setting for codec reset pin in overridetree
`Fix codec reset pin in overridetree`
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Change subject: util/amdfwtool: Add amdfwread utility
......................................................................
Patch Set 13:
(1 comment)
File util/amdfwtool/Makefile:
https://review.coreboot.org/c/coreboot/+/62795/comment/e6980745_4020711d
PS10, Line 21: HEADER
> This doesn't look like it's defined.
Define HEADER as `amdfwtool.h`
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Change subject: mb/clevo/tgl-u: Add Clevo NV4x Tiger Lake laptop support
......................................................................
Patch Set 6: Code-Review+1
(9 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62498/comment/fc873107_67c576d0
PS6, Line 8:
Are there any known problems?
File src/mainboard/clevo/tgl-u/Kconfig:
https://review.coreboot.org/c/coreboot/+/62498/comment/e7cb17a2_18f3d6ae
PS3, Line 13: MAINBOARD_HAS_LPC_TPM
> MEMORY_MAPPED_TPM
Done
File src/mainboard/clevo/tgl-u/Kconfig.name:
https://review.coreboot.org/c/coreboot/+/62498/comment/e6e25245_84d40d5e
PS1, Line 5: select BOARD_CLEVO_NV4X_BASE
> I saw patches shifting these selects to the Kconfig.name to Kconfig files, e.g. CB:62816 […]
Done
File src/mainboard/clevo/tgl-u/variants/nv40mz/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/62498/comment/7c8728b8_a1c750b4
PS6, Line 13: # Disable DPTF
: register "dptf_enable" = "0"
This can be dropped, default is 0
https://review.coreboot.org/c/coreboot/+/62498/comment/5c13f335_5f0efc7d
PS6, Line 22: required
Is S0ix actually required?
https://review.coreboot.org/c/coreboot/+/62498/comment/d188f389_4cbd7601
PS6, Line 115: device ref peg on
Add "smbios_slot_desc"?
https://review.coreboot.org/c/coreboot/+/62498/comment/48a10365_95451794
PS6, Line 261: Pantone ROM
I wonder what this EEPROM is used for.
https://review.coreboot.org/c/coreboot/+/62498/comment/6f9080e5_948c6f29
PS6, Line 308: register "PcieRpEnable[10]" = "1"
register "PcieRpSlotImplemented[10]" = "1"
Also, add "smbios_slot_desc"?
File src/mainboard/clevo/tgl-u/variants/nv40mz/ramstage.c:
https://review.coreboot.org/c/coreboot/+/62498/comment/cb2398dc_dc924644
PS6, Line 12: params->CpuPcieRpAdvancedErrorReporting[0] = 0;
I'd also add this:
params->CpuPcieRpSlotImplemented[0] = 1;
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Change subject: mb/google/dedede/var/beadrix: Add a Proximity Sensor SX9324 for SAR
......................................................................
Patch Set 9: Code-Review+2
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Hello build bot (Jenkins), Bao Zheng, Raul Rangel, Avinash Alevoor, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/64040
to look at the new patch set (#3).
Change subject: util/amdfwtool: Add IKEK key for Trusted Application
......................................................................
util/amdfwtool: Add IKEK key for Trusted Application
This binary file is required for use by Trusted Applications that
execute in PSP.
BUG=b:229947314
TEST=Build and boot to OS in Skyrim.
Change-Id: I2d05792cfd98fa9c38f5deef1ac3282625983eeb
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
---
M util/amdfwtool/amdfwtool.c
M util/amdfwtool/amdfwtool.h
M util/amdfwtool/data_parse.c
3 files changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/64040/3
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