Attention is currently required from: Felix Singer, Michał Żygowski, Michał Kopeć, Michael Niewöhner. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62498 )
Change subject: mb/clevo/tgl-u: Add Clevo NV4x Tiger Lake laptop support ......................................................................
Patch Set 6: Code-Review+1
(9 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62498/comment/fc873107_67c576d0 PS6, Line 8: Are there any known problems?
File src/mainboard/clevo/tgl-u/Kconfig:
https://review.coreboot.org/c/coreboot/+/62498/comment/e7cb17a2_18f3d6ae PS3, Line 13: MAINBOARD_HAS_LPC_TPM
MEMORY_MAPPED_TPM
Done
File src/mainboard/clevo/tgl-u/Kconfig.name:
https://review.coreboot.org/c/coreboot/+/62498/comment/e6e25245_84d40d5e PS1, Line 5: select BOARD_CLEVO_NV4X_BASE
I saw patches shifting these selects to the Kconfig.name to Kconfig files, e.g. CB:62816 […]
Done
File src/mainboard/clevo/tgl-u/variants/nv40mz/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/62498/comment/7c8728b8_a1c750b4 PS6, Line 13: # Disable DPTF : register "dptf_enable" = "0" This can be dropped, default is 0
https://review.coreboot.org/c/coreboot/+/62498/comment/5c13f335_5f0efc7d PS6, Line 22: required Is S0ix actually required?
https://review.coreboot.org/c/coreboot/+/62498/comment/d188f389_4cbd7601 PS6, Line 115: device ref peg on Add "smbios_slot_desc"?
https://review.coreboot.org/c/coreboot/+/62498/comment/48a10365_95451794 PS6, Line 261: Pantone ROM I wonder what this EEPROM is used for.
https://review.coreboot.org/c/coreboot/+/62498/comment/6f9080e5_948c6f29 PS6, Line 308: register "PcieRpEnable[10]" = "1" register "PcieRpSlotImplemented[10]" = "1"
Also, add "smbios_slot_desc"?
File src/mainboard/clevo/tgl-u/variants/nv40mz/ramstage.c:
https://review.coreboot.org/c/coreboot/+/62498/comment/cb2398dc_dc924644 PS6, Line 12: params->CpuPcieRpAdvancedErrorReporting[0] = 0; I'd also add this:
params->CpuPcieRpSlotImplemented[0] = 1;